Patent Application
20250006126
Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, in particular to a pixel driving circuit and a driving method therefor, a display panel, and a display apparatus.
For a display apparatus, how to reduce power consumption has been a research problem. For an OLED display scheme, one of the schemes to reduce power consumption is to reduce a cross-voltage between VDD (power supply positive voltage) and VSS (power supply negative voltage).
However, with a decrease of a cross-voltage between VDD and VSS, a data voltage range (a voltage range of a data signal) will decrease, which makes some gray scales unable to be displayed. For example, in a L255 display apparatus, reducing the cross-voltage between VDD and VSS will reduce a data voltage required by the L255, which may be a negative value, and at this time, the chip cannot correspond and thus cannot display.
The following is a summary of subject matter described herein in detail. This summary is not intended to limit the protection scope of claims.
In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, including:
In an exemplary embodiment, the writing transistor and the drive transistor are both P-type transistors, and the coupling capacitor is configured to pull down the voltage of the first node in the light emitting phase in response to a voltage control signal.
In an exemplary embodiment, the pixel driving circuit further includes:
In an exemplary embodiment, the light emitting control signal is also used as the voltage control signal.
In an exemplary embodiment, a capacitance value of the coupling capacitor is greater than or equal to 2 fF (flying farad).
In an exemplary embodiment, a capacitance value of the coupling capacitor is less than or equal to 10 fF (flying farad).
In a second aspect, an embodiment of the present disclosure provides a display panel, including a base substrate and the above-described pixel driving circuit located at a side of the base substrate.
In an exemplary embodiment, the display panel includes:
In an exemplary embodiment, the display panel includes:
In an exemplary embodiment, the display panel includes:
In an exemplary embodiment, a planarization layer, an anode layer, a pixel definition layer, a light emitting layer, and a cathode layer are arranged sequentially in a direction of the source-drain electrode layer away from the base substrate, wherein the anode layer includes a plurality of anode units, each of the anode units is electrically connected to a second electrode of a drive transistor in one pixel driving circuit, and the cathode layer is electrically connected to the second power supply terminal.
In an exemplary embodiment, the display panel further includes a buffer layer located between the base substrate and the active layer; and an encapsulation layer located at a side of the cathode layer away from the light emitting layer.
In a third aspect, an embodiment of the present disclosure provides a display apparatus including the above-described display panel.
In a fourth aspect, an embodiment of the present disclosure provides a driving method for driving the above-described pixel driving circuit, and the driving method includes:
In an exemplary embodiment, the driving method further includes:
Other aspects of the present disclosure may be comprehended after the drawings and the detailed descriptions are read and understood.
The abovementioned and/or additional aspects and advantages of the embodiments of the present disclosure will become clear and easily understandable from the following descriptions made to the embodiments with reference to the drawings.
Embodiments of the present disclosure are described below with reference to the accompanying drawings. It should be understood that the implementations set forth below reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present disclosure and are not limited to the technical solutions of the embodiments of the present disclosure.
It can be understood by those skilled in the art that unless otherwise specified, the singular forms “one”, “a/an”, “said”, and “the” used herein may also include plural forms. It should further be understood that wording “include” used in the specification of the present disclosure refers to existence of feature, integer, step, operation, element, and/or component, but does not exclude implementation of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof. It should be understood that when stating an element is “connected” or “coupled” to another element, the element may be directly connected or coupled to the another element, or the element and another element establish a connection relationship through an intermediate element. In addition, “connected” or “coupled” used herein may include wireless connection or wireless coupling. As used herein, the term “and/or” refers to at least one of the items defined by the term, e.g. “A and/or B” may be implemented as “A”, or as “B”, or as “A and B”.
Implementations of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments.
Firstly, several nouns related to this disclosure are introduced and explained.
L255 display apparatus refers to a display apparatus with gray level 256 (gray level 0 to 255). Gray scale is the so-called color scale or gray scale, which refers to a degree of lightness or darkness in brightness. For the L255 display apparatus, enough data voltage range is needed to ensure that each gray level has the corresponding degree of lightness or darkness.
For a cross-voltage between VDD and VSS, VDD refers to a positive voltage of a pixel driving circuit, VSS refers to a negative voltage of the pixel driving circuit, and the cross-voltage between VDD and VSS is a working cross-voltage of the pixel driving circuit.
Standard cross-voltage commonly uses a cross-voltage between VDD and VSS. Taking 1224×2700 OLED display apparatus as an example, a commonly used power supply voltage is: VDD being 4.6 V, VSS being −3.1 V; or VDD being 4.0 V and VSS being −3.7 V; or VDD being 3.5 V, VSS being −4.2V, etc.
For a display apparatus, how to reduce power consumption has been a research problem. For the OLED display scheme, one of the schemes for reducing power consumption is to reduce the cross-voltage between VDD and VSS. However, with the decrease of the cross-voltage between VDD and VSS, the data voltage range will be reduced, which makes some gray scales unable to be displayed. For example, in the L255 display apparatus, reducing the cross-voltage between VDD and VSS will reduce the data voltage required by L255, which may be a negative value, and in this case, the chip cannot correspond to the voltage and thus cannot display.
Taking 1224×2700 OLED display apparatus as an example, simulation data of standard cross-voltage and reduced cross-voltage are shown in Table 1.
VDD being 2.8 V and VSS being −2.8 V is only an exemplary illustration, and appropriate voltage values of VDD and VSS may be selected according to factors such as pixel arrangement and display panel size.
Please refer to Table 1, G0 refers to a gray scale of 0, G255 refers to a gray scale of 255, Vdata_G0 refers to a data voltage at the gray scale of 0, and Vdata_G255 refers to a data voltage at the gray scale of 255.
According to a comparison in Table 1, whether it is red sub-pixel R, green sub-pixel G or blue sub-pixel B, after the Vdd/Vss cross-voltage decreases, the data voltage V data at each gray scale decreases relative to the standard cross-voltage. Although in the simulation data of the embodiments given in Table 1, a negative value of the data voltage does not exist, in other examples, a negative value of the data voltage may exist. However, the drive chip of OLED display panel may only provide a positive data voltage, so when the data is provided according to the simulation results in Table 1 above, the voltage will result in abnormal displaying.
The technical solutions of the present disclosure will be described in detail below. It should be noted that the following implementations may be referred to, drawn upon, or combined with each other, and the same terms, similar features, similar implementation steps and the like in different implementations will not be described repeatedly.
An embodiment of the present disclosure provides a pixel driving circuit, as shown in
A gate of the writing transistor T4 is configured to be electrically connected to a gate signal terminal gate, a first electrode of the writing transistor T4 is configured to be electrically connected to a data signal terminal Vdata, and a second electrode of the writing transistor T4 is configured to be coupled to a first node N1, and the writing transistor T4 is configured to write a data voltage input from the data signal terminal Vdata to the first node N1 in response to a gate signal input from a gate signal terminal gate, such that a voltage of the first node N1 is a first voltage.
One plate of the storage capacitor C1 is configured to be electrically connected to a first power supply terminal (VDD in the figure), the other plate of the storage capacitor C lis configured to be electrically connected to the first node N1, and the storage capacitor C is configured to store the voltage of the first node N1.
One plate of the coupling capacitor C2 is configured to be electrically connected to a control voltage terminal (Con in the figure), the other plate of the coupling capacitor C2 is configured to be electrically connected to the first node N1, and the coupling capacitor C2 is configured to adjust the voltage of the first node N1 during a light emitting stage, such that the voltage of the first node N1 is converted from the first voltage to a second voltage.
A gate of the drive transistor T3 is configured to be electrically connected to the first node N1, a first electrode of the drive transistor T3 is configured to be coupled with the first power supply terminal (VDD in the figure), a second electrode of the drive transistor T3 is configured to be coupled with one end of the light emitting unit, and the drive transistor T3 is configured to generate a drive current according to the second voltage and a first power supply voltage during the light emitting stage.
The other end of the light emitting unit is configured to be electrically connected to a second power supply terminal (VSS in the figure), and the light emitting unit is configured to emit light under driving of the drive current.
The drive current of the light emitting unit (OLED) is idrive=k×(Vgs−Vth)2, where Vgs is a difference between a gate voltage Vg and a source voltage Vs of the drive transistor T3, Vth is a threshold voltage of the drive transistor T3, and k is a proportional constant (k is different in different pixel driving circuits).
During the light emitting stage, Vg is the voltage of the first node N1, and Vs is the voltage of the first power supply terminal Vdd, i.e. idrive=k×(VN1−Vdd−Vth)2. In the present disclosure, the voltage VN1 of the first node N1 during the light emitting stage is the second voltage V2, i.e. idrive=k×(V2−Vdd−Vth)2. That is, the drive current required for emitting light with required brightness by the light emitting unit is idrive=k×(V2−Vdd−Vth)2, and only input data voltage is required such that the first node N1 is the first voltage in a data writing stage. Therefore, the effect of adjusting a value of the input data voltage may be achieved by providing the coupling capacitor C2.
The pixel driving circuit according to this embodiment can adjust the voltage of the first node N1 during the light emitting stage by providing the coupling capacitor C2 at the first node N1, such that the data voltage input into the pixel driving circuit by the drive chip may make the first node N1 be kept at the first voltage in the data writing stage, thereby solving a situation that the required data voltage caused by reducing the cross-voltage between VDD/VSS exceeds a data voltage range provided by the drive chip, and ensuring normal displaying of the OLED display apparatus.
In an exemplary embodiment, as shown in
In an exemplary embodiment, as shown in
A gate of the first light emitting control transistor T5 is configured to be electrically connected to a light emitting control terminal EM, a first electrode of the first light emitting control transistor T5 is configured to be electrically connected to the first power supply terminal VDD, a second electrode of the first light emitting control transistor T5 is configured to be electrically connected to a second node N2, and the first light emitting control transistor T5 is configured to be turned on in response to a light emitting control signal input from the light emitting control terminal EM to make a voltage of the first power supply terminal be written into the second node N2, wherein the second node N2 is electrically connected to the first electrode of the drive transistor T3.
A gate of the second light emitting control transistor T6 is configured to be electrically connected to the light emitting control terminal EM, a first electrode of the second light emitting control transistor T6 is configured to be electrically connected to a third node N3, a second electrode of the second light emitting control transistor T6 is configured to be electrically connected to a fourth node N4, and second light emitting control transistor T6 is configured to be turned on in response to the light emitting control signal to make a voltage of the third node N3 be written into the fourth node N4, wherein the third node N3 is electrically connected to the second electrode of the drive transistor T3, and the fourth node N4 is electrically connected to the first end of the light emitting unit.
A gate of the switching transistor T2 is configured to be electrically connected to the gate signal terminal gate, a first electrode of the switching transistor T2 is configured to be electrically connected to the first node N1, a second electrode of the switching transistor T2 is configured to be electrically connected to the third node N3, and the switching transistor T2 is configured to be turned on in response to the gate signal to make the voltage of the third node N3 be written into the first node N1.
A gate of the first reset transistor T1 is configured to be electrically connected to a reset control terminal Reset, a first electrode of the first reset transistor T1 is configured to be electrically connected to the first node N1, and a second electrode of the first reset transistor T1 is configured to be electrically connected to a reset signal terminal Vint, and the first reset transistor T1 is configured to be turned on in response to a reset control signal input from the reset control terminal Reset to make a reset voltage input from the reset signal terminal Vint be written into the first node N1.
A gate of the second reset transistor T7 is configured to be electrically connected to the reset control terminal Reset, a first electrode of the second reset transistor T7 is configured to be electrically connected to the fourth node N4, a second electrode of the second reset transistor T7 is configured to be electrically connected to the reset signal terminal Vint, and the second reset transistor T7 is configured to write the reset voltage into the fourth node N4 in response to the reset control signal.
In the pixel driving circuit according to this embodiment, the coupling capacitor C2 is added on the basis of 7T1C, so that the coupling capacitor C2 adjusts a potential of the first node N1 during the light emitting stage.
Further, as shown in
In an exemplary embodiment, when each transistor in the pixel driving circuit is a P-type transistor, the P-type transistors are turned on at a low level. As shown in
For ease of understanding, a working process of the pixel driving circuit according to an embodiment of the present disclosure will be described below with reference to
As shown in
As shown in
As shown in
As shown in
In an exemplary embodiment, as shown in
In an exemplary embodiment, a simulation experiment is carried out by using a 1224×2700 OLED display apparatus under a condition that the VDD/VSS is 2.8 V/−2.8V, and the simulation data of the reduced cross-voltage is obtained as shown in Table 2. It should be noted that the data voltage shown in Table 2 is a data voltage required to be input from the data signal terminal Vdata.
As shown in Table 2, when the capacitance of the coupling capacitor C2 is 0 (i.e. there is no coupling capacitor C2) and the brightness is L255_B, the simulation data of the obtained data voltage is 0.04 V, which is too low, and there is a risk that the voltage will exceed an available data voltage range for the driver chip. With the increase of the capacitance of the coupling capacitor C2, the data voltages of different color sub-pixels under different brightness increase, so that the required data voltage can meet a data voltage range which can be provided by the drive chip.
ΔV_R is a data voltage range required by red sub-pixels, ΔV_G is a data voltage range required by green sub-pixels, and ΔV_B is a data voltage range required by blue sub-pixels. As shown in Table 2, a range of ΔV_B is quite different from those of ΔV_R and ΔV_G. Under the condition that the data voltage range that can be provided by the driver chip is unchanged, the greater the difference between the ranges of ΔV_B and ΔV_R, the smaller the adjustable ranges of ΔV_R and ΔV_G, and the more unfavorable it is to achieve high-accuracy brightness adjustment of red sub-pixels and green sub-pixels. However, with the increase of the capacitance of coupling capacitor C2, the difference between the ranges of ΔV_B and ΔV_R gradually decreases. Therefore, design of the coupling capacitor C2 with an appropriate capacitance can not only avoid the risk that the driver chip cannot provide a correct drive voltage, but also improve brightness adjustment accuracy of red sub-pixels and green sub-pixels under the condition that the data voltage range which can be provided by the chip remains unchanged, improving a quality of displayed pictures.
Moreover, a required capacitance value of the coupling capacitor C2 is small, so the purpose of increasing the capacitance of the coupling capacitor C2 can be achieved through a simple design on the basis of the current pixel driving circuit, that is, the technical solution according to the present disclosure has high feasibility.
An embodiment of the present disclosure further provides a display panel. As shown in
In the display panel according to this embodiment, the structure of the pixel driving circuit 2 may be simply modified to achieve a purpose of increasing the capacitance of the coupling capacitor C2 at the first node N1. Since the pixel driving circuit 2 may adopt different layout designs, for convenience of explanation, only the position where the coupling capacitor C2 is formed will be described in detail below.
As shown in
As shown in
As shown in
In the display panel according to this embodiment, the first gate layer 204 is provided with the multiplexing electrode E1, the second gate layer 206 is provided with the storage electrode E2 and the coupling electrode E3, and the second gate insulation layer 205 is simultaneously used as the first dielectric layer and the second dielectric layer, so that the purpose of increasing the capacitance of the coupling capacitor C2 at the first node N1 may be achieved without adding a film layer.
Further, as shown in
As shown in
The active layer 202 is located at a side of the base substrate 1. The first gate insulation layer 203 is located at a side of the active layer 202 away from the base substrate 1. The first gate layer 204 is located at a side of the first gate insulation layer 203 away from the base substrate 1, and includes a plurality of gate lines gate, a plurality of light emitting control lines EM, and a plurality of multiplexing electrodes E1, wherein the gate lines gate and the light emitting control lines EM are alternately arranged. The second gate insulation layer 205 is located at a side of the first gate layer 204 away from the base substrate 1 and is also used as a first dielectric layer. The second gate layer 206 includes a plurality of storage electrodes E2. The interlayer insulation layer 207 is located at a side of the second gate layer 206 away from the base substrate 1, and the interlayer insulation layer 207 and the second gate insulation layer 205 also used as a second dielectric layer. The source-drain electrode layer 208 includes a source electrode S, a drain electrode D, and a coupling electrode E3. The coupling electrode E3 is electrically connected to the light emitting control line EM through a via hole penetrating through the interlayer insulation layer 207 and the second gate insulation layer 205.
In this embodiment, the dielectric layer between the coupling electrode E3 and the multiplexing electrode E1 includes an interlayer insulation layer 207 and a second gate insulation layer 205, that is, the dielectric layer has a strong dielectric effect, which is beneficial to reducing an overlapping area between the coupling electrode E3 and the multiplexing electrode E1, thereby being beneficial to reducing influence of increasing the capacitance of the coupling capacitor C2 on squeezed layout space of the pixel driving circuit 2.
As shown in
An embodiment of the present disclosure further provides a display apparatus, and as shown in
As shown in
An embodiment of the present disclosure further provides a driving method for driving the pixel driving circuit in the above-described embodiment. Based on the pixel driving circuit 2 shown in
At S1, it is a data writing stage, and during the data writing stage, the writing transistor T4 writes a data voltage into the first node N1 in response to a gate signal.
At S2, it is a light emitting stage, and during the light emitting stage, the coupling capacitor C2 makes a second adjustment to the voltage of the first node N1 to adjust a drive current generated by the drive transistor T3, so that the light emitting unit may emit light under driving of the drive current.
The driving method according to this embodiment is used for driving the pixel driving circuit 2 in the above-described embodiment, and based on the adjustment effect of the coupling capacitor C2 in the pixel driving circuit 2 on the potential of the first node N1 during the light emitting stage, a situation that the required data voltage exceeds the data voltage range which can be provided by the drive chip can be avoided after the cross-voltage between VDD/VSS is reduced.
Further, as shown in
For ease of understanding, a working process of the pixel driving circuit 2 according to an embodiment of the present disclosure will be described below with reference to
As shown in
As shown in
As shown in
As shown in
Embodiments of the present disclosure may be applied to at least achieve the following beneficial effects:
The pixel driving circuit, the driving method thereof, the display panel and the display apparatus according to this embodiment can adjust the voltage of the first node during the light emitting stage by providing the coupling capacitor at the first node, such that the data voltage input into the pixel driving circuit by the drive chip can make the first node be kept at the first voltage in the data writing stage, thereby solving a situation that the reduction of the cross-voltage between VDD/VSS exceeds a data voltage range provided by the drive chip, and ensuring anormal displaying of the OLED display apparatus.
Those skilled in the art may understand that steps, measures and schemes in operations, methods, and the process already discussed in the present disclosure may be alternated, changed, combined or deleted. Further, other steps, measures and schemes in operations, methods and processes already discussed in the present disclosure may also be alternated, changed, rearranged, divided, combined or deleted. Further, steps, measures and schemes in the prior arts having the same functions with those in operations, methods and processes disclosed in the present disclosure may also be alternated, changed, rearranged, divided, combined or deleted.
In descriptions of the present disclosure, directions or positional relationships indicated by words “center”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, and the like are based on exemplary directions or positional relationships shown in the drawings, and are for convenience of describing or simplifying embodiments of the present disclosure, but are not intended to indicate or imply that a referred apparatus or components must have a specific orientation, or be constructed and operated in a particular orientation, and therefore they should not be construed as limitations on the present disclosure.
Terms “first” and “second” are only used for description and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined by “first” and “second” may explicitly or implicitly include one or more such features. In the descriptions of the present disclosure, “multiple” means two or more than two, unless otherwise specified.
The features, structures, materials, or characteristics described in the description may be combined in any one or more embodiments or examples in a proper way.
It should be understood that although steps in the flowcharts of the drawings are shown in the order as indicated by arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of embodiments of the present disclosure, the steps in the process may be performed in other order as required. Furthermore, based on the actual implementation scenario, some or all of the steps in the flowchart may include a plurality of sub-steps or a plurality of stages. Part or all of the sub-steps or stages may be executed at the same time or at different times, and under different scenarios of execution time, the execution sequence of these sub-steps or stages may be flexibly configured according to requirements, which is not limited in embodiments of the present disclosure.
The above is only part of the implementations of the present disclosure, and it should be noted that for those of ordinary skills in the art, without departing from the technical conception of the present disclosure, adopting other similar implementation means based on the technical idea of the present disclosure also belongs to the protection scope of embodiments of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210556932.9 | May 2022 | CN | national |
The present application is a U.S. National Phase Entry of International Application PCT/CN2023/093267 filed on May 10, 2023, which claims priority of Chinese patent application No. 202210556932.9, filed to the CNIPA on May 20, 2022 and entitled “Pixel Driving Circuit and Driving Method Therefor, and Display Panel and Display Apparatus”, which are hereby incorporated herein by reference in their entireties.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/093267 | 5/10/2023 | WO |
