Patent Application
20230096851
This application claims priority to Chinese Patent Application No. 202210772995.8 filed Jun. 30, 2022, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technology and, in particular, to a pixel driving circuit and a driving method thereof, a light-emitting panel, and a display device.
With the development of display technology, the application of display panels is becoming more and more widespread. For example, display panels are applied to products such as mobile phones, computers, tablet computers, electronic books, and information inquiry machines and also can be applied to instrument displays (such as an in-vehicle display) and smart home control panels.
A micro light-emitting diode in a micro light-emitting diode display panel is a current-driven element, and a pixel driving circuit is required to provide a drive current to make the micro light-emitting diode emit light. However, during the overall power-on period of the existing pixel driving circuit, due to the current leakage phenomenon of a transistor in the pixel driving circuit, a drive transistor in the pixel driving circuit is abnormally turned on. As a result, the display effect of a display panel is seriously affected.
An embodiment of the present disclosure provides a pixel driving circuit and a driving method thereof, a light-emitting panel, and a display device to avoid a screen flicker phenomenon during the power-on stage of the pixel driving circuit and to prevent the display effect from being affected.
In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit. The pixel driving circuit includes a reset unit, a storage unit, an initialization unit, a drive unit, a threshold compensation unit, and a data write unit.
A first terminal of the drive unit is configured to input the signal output by a first power supply. A second terminal of the drive unit is configured to provide a light-emitting drive signal for a light-emitting unit. The storage unit is connected between the control terminal of the drive unit and the first terminal of the drive unit. The threshold compensation unit is connected between the control terminal of the drive unit and the second terminal of the drive unit.
The data write unit is connected to the first terminal of the drive unit and configured to transmit a data voltage to the drive unit. The initialization unit is connected to the control terminal of the drive unit and a first terminal of the light-emitting unit and configured to transmit a corresponding initialization voltage to the control terminal of the drive unit and the first terminal of the light-emitting unit.
A first terminal of the reset unit is configured to input the signal output by a reset power supply. The second terminal of the reset unit is connected to the control terminal of the drive unit and configured to provide the reset power supply for the control terminal of the drive unit during a power-on period.
In a second aspect, an embodiment of the present disclosure provides a driving method of a pixel circuit. The method is applied by the pixel circuit described in any one of the first aspect. The method includes the steps below.
In a power-on reset stage, the reset unit is controlled to transmit the reset power supply to the control terminal of the drive unit.
In an initialization sub-stage in a scan time period, the initialization unit is controlled to transmit the corresponding initialization voltage to the control terminal of the drive unit and the first terminal of the light-emitting unit.
In a data write stage in the scan time period, the threshold compensation unit is controlled to write the threshold voltage of the drive unit to the control terminal of the drive unit, and the data write unit is controlled to write the data voltage to the control terminal of the drive unit.
In a light emission stage in the scan time period, the first power supply, the drive unit, the light-emitting unit, and a second power supply are controlled to form a path, and the light-emitting unit is driven to emit light.
In a third aspect, an embodiment of the present disclosure provides a light-emitting panel. The panel includes the pixel driving circuit described in any one of the first aspect.
In a fourth aspect, an embodiment of the present disclosure provides a display device. The device includes the light-emitting panel described in the third aspect.
The solutions in embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure from which the solutions will be better understood by those skilled in the art. Apparently, the embodiments described below are part, not all, of the embodiments of the present disclosure. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art on the premise that no creative work is done are within the scope of the present disclosure.
In the related art, in a conventional 7T1C pixel driving circuit, for example, each transistor is a p-type transistor. During the power-on reset stage of the pixel driving circuit, a light emission control signal is always at a low level, so that a light emission control unit connected to the light emission control signal is in an on state. At the same time, due to the influence of the leakage current of an initialization unit, the control terminal of a drive unit receives a low level, so that the drive unit is turned on. Then a path is formed between a first power supply, the light emission control unit, the drive unit, a light-emitting unit, and a second power supply. In this manner, the light-emitting unit is lighted in the power-on reset stage, resulting in the abnormal display of a display panel in a non-display stage.
To solve the preceding technical problems, an embodiment of the present disclosure provides a pixel driving circuit. The pixel driving circuit includes a reset unit, a storage unit, an initialization unit, a drive unit, a threshold compensation unit, and a data write unit. A first terminal of the drive unit is configured to input the signal output by a first power supply. A second terminal of the drive unit is configured to provide a light-emitting drive signal for a light-emitting unit. The storage unit is connected between the control terminal of the drive unit and the first terminal of the drive unit. The threshold compensation unit is connected between the control terminal of the drive unit and the second terminal of the drive unit. The data write unit is connected to the first terminal of the drive unit and configured to transmit a data voltage to the drive unit. The initialization unit is connected to the control terminal of the drive unit and a first terminal of the light-emitting unit and configured to transmit a corresponding initialization voltage to the control terminal of the drive unit and the first terminal of the light-emitting unit. A first terminal of the reset unit is configured to input the signal output by a reset power supply. A second terminal of the reset unit is connected to the control terminal of the drive unit and configured to provide the reset power supply for the control terminal of the drive unit during a power-on period. In a power-on reset stage, the reset unit provides the reset power supply for the drive unit and performs reset control on the drive unit, so that the drive unit is prevented from being abnormally turned on during a power-on stage, thereby avoiding a screen flicker phenomenon.
The above is the core concept of the present disclosure, and the technical solutions in the embodiments of the present disclosure are described clearly and completely hereinafter in conjunction with the drawings in the embodiments of the present disclosure. Based on embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of the present disclosure.
The light-emitting unit 107 may include at least one light-emitting element. For example, the light-emitting element may be a micro light-emitting diode. The micro light-emitting diode may be a micro LED or a mini LED. The micro light-emitting diode is a current-type device and can emit light under the action of a drive current. The drive unit 104 can generate a corresponding drive current according to a data voltage signal Vdata to drive the light-emitting unit 107 to display different grayscales. In this manner, a display panel may display a to-be-displayed image. The specific working process of the pixel driving circuit includes a power-on reset stage, an initialization stage, a data write stage, and a light emission stage. In the power-on reset stage, the reset unit 101 is turned on. The reset unit 101 transmits the signal output by the reset power supply to the control terminal of the drive unit 104 during the power-on period and then performs reset processing on the control terminal of the drive unit 104. In this manner, in the power-on reset stage, the drive unit 104 is always in an off state, thereby preventing the drive unit 104 from being abnormally turned on due to the influence of the leakage current of the initialization unit 103. In the initialization stage, the reset unit 101 is turned off. The initialization unit 103 is connected to the control terminal of the drive unit 104 and the first terminal of the light-emitting unit 107. In the initialization stage, the initialization unit 103 is turned on. The initialization unit 103 outputs the initialization voltage Vref to the control terminal of the drive unit 104 and the control terminal of the light-emitting unit 107 respectively and then initializes the control terminal of the drive unit 104 and the control terminal of the light-emitting unit 107. In this manner, the residual charge of the image of the previous frame may be cleared, thereby improving the display effect of the display panel. In the data write stage, the reset unit 101 and the initialization unit 103 are turned off, and the data write unit 106 and the threshold compensation unit 105 are turned on. The data write unit 106 is connected to the first terminal of the drive unit 104. The data write unit 106 writes the data voltage signal Vdata to the drive unit 104. The threshold compensation unit 105 is connected between the control terminal of the drive unit 104 and the second terminal of the drive unit 104. The threshold compensation unit 105 may capture the threshold voltage of the drive unit 104 and write the threshold voltage to the control terminal of the drive unit 104, thereby implementing the compensation of the threshold voltage. The storage unit 102 is connected between the control terminal of the drive unit and the first terminal of the drive unit 104. The storage unit 102 may maintain the potential of the control terminal of the drive unit 104. In this manner, when the initialization unit 103 is turned off, the potential of the control terminal of the drive unit 104 is prevented from being coupled and changing. In the light emission stage, the reset unit 101, the initialization unit 103, the data write unit 106, and the threshold compensation unit 105 are each turned off, and the drive unit 104 is turned on. The second terminal of the drive unit 104 is connected to the first terminal of a light-emitting element and configured to provide the light-emitting drive signal for the light-emitting unit 107. The light-emitting unit 107 emits light in response to the light-emitting drive signal and displays to-be-displayed brightness.
In this embodiment of the present disclosure, during the power-on period, the reset unit 101 is turned on and provides the reset power supply for the control terminal of the drive unit, so that the drive unit is in the off state during the power-on period. In this manner, the drive unit is prevented from being abnormally turned on in the non-display stage, thereby preventing the light-emitting unit from being lighted. Moreover, the occurrence of the screen flicker phenomenon of the display panel is avoided, and the normal display effect of the display panel is ensured.
Optionally,
The pixel driving circuit also includes a first light emission control unit 108 and a second light emission control unit 109. The first light emission control unit 108 is connected between the first power supply PVDD and the first terminal of the drive unit 104. The second light emission control unit 109 is connected between the second terminal of the drive unit 104 and the first terminal of the light-emitting unit 107. The second terminal of the light-emitting unit 107 is connected to the second power supply PVEE. In the light emission stage, the first light emission control unit 108 and the second light emission control unit 109 are turned on. A voltage difference is generated between the first terminal of the drive unit 104 and the first terminal of the drive unit 104, and then the light-emitting drive signal is output to the first terminal of the light-emitting unit 107. The second terminal of the light-emitting unit 107 is connected to the second power supply PVEE. Then a path is formed between the first power supply PVDD, the first light emission control unit 108, the second light emission control unit 109, the light-emitting unit 107, and the second power supply PVEE. The light-emitting unit 107 emits light and displays the to-be-displayed brightness.
Optionally,
The pixel driving circuit also includes a first initialization unit 1031 and a second initialization unit 1032. The first initialization unit 1031 is connected between the first reference voltage output terminal VREF1 and the control terminal of the drive unit 104. In the initialization stage, the first initialization unit 1031 provides the first initialization voltage Vref1 for the drive unit 104 to clear the residual charge of the image of the previous frame in the control terminal of the drive unit 104, so that the writing of a data signal Vdata in the data write stage is facilitated. The second initialization unit 1032 is connected between a second reference voltage output terminal VREF2 and the first terminal of the light-emitting unit 107 and provides the second initialization voltage Vref2 for the light-emitting unit 107, so that the residual charge of the image of the previous frame in the light-emitting unit 107 may be cleared. In this manner, the light-emitting unit 107 can more accurately display the to-be-display brightness, thereby improving the image quality of the display panel. The control terminal of the second initialization unit 1032 may access a first scan signal line or a second scan signal line, so that the second initialization unit 1032 may initialize the light-emitting unit 107 in the initialization stage or the data write stage. When the first initialization unit 1031 and the second initialization unit 1032 are turned on in the initialization stage, the first initialization voltage Vref1 and the second initialization voltage Vref2 may be each the initialization voltage Vref output by the same initialization output terminal. When the first initialization unit 1031 is turned on in the initialization stage, the first initialization unit 1031 receives the first initialization voltage Vref1. When the second initialization unit 1032 is turned on in the data write stage, the second initialization unit 1032 receives the second initialization voltage Vref2. Although the on time of the first initialization unit 1031 and the second initialization unit 1032 is different, the first initialization voltage Vref1 and the second initialization voltage Vref2 may be the same signal, for example, −3.5V. Of course, the two may also be different signals. For example, the first initialization voltage Vref1 is −3.5V, and the second initialization voltage Vref2 is −3V. In the following embodiments, description is given by using an example in which the first initialization unit 1031 and the second initialization unit 1032 are turned on in the initialization stage, that is, the same initialization voltage Vref is received at the same time. In this manner, the number of signal lines can be reduced, the manufacturing cost can be reduced, and the complexity of the pixel driving circuit can be simplified.
Optionally,
The light-emitting unit 107 may include multiple micro LEDs connected in series. As shown in
Optionally,
The control terminal of the reset unit 101 is connected to the reset scan signal output terminal RESET. The reset scan signal output terminal RESET also serves as the reset signal output terminal RESET1 of the gate driving circuit 111. The output terminal OUT of a shift register may output a low-level signal VGL or a high-level signal VGH. When the first node N1 is at a turn-on level, and a second node N2 is at a turn-off level, the output terminal OUT of the shift register outputs the low-level signal VGL. When the first node N1 is at a turn-off level, and the second node N2 is at a turn-on level, the output terminal OUT of the shift register outputs the high-level signal VGH. Additionally, the reset signal output terminal RESET1 of the gate driving circuit 111 controls an eleventh transistor T11 to turn on during the power-on period. In this manner, the high-level signal VGH can be transmitted to a scan signal output terminal OUT, and the scan signal output terminal OUT of the gate driving circuit 111 is reset. Moreover, the problem of the power-on screen flicker of the display panel is avoided. When the display panel is in a normal scan time period, the reset signal output terminal RESET1 turns off the eleventh transistor T11, and the output terminal OUT of the shift register normally outputs a signal. The gate driving circuit 111 includes various reset signal output terminals RESET1. When a transistor in the reset unit 101 is a p-type transistor, a low-level reset signal in the gate driving circuit 111 may be selected to make the reset unit 101 turned on. When a transistor in the reset unit 101 is an n-type transistor, a high-level reset signal in the gate driving circuit 111 may be selected to make the reset unit 101 turned on. At the same time, the multiplexing of the reset signal output terminal RESET1 of the gate driving circuit 111 may avoid additional disposition of a signal line. In this manner, the number of signal lines can be reduced, the manufacturing cost can be reduced, and the complexity of the pixel driving circuit can be simplified.
Optionally,
The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are each a p-type transistor. A p-type transistor is turned on at a low level and is turned off at a high level. For example, the working principle of the pixel driving circuit is described with reference to
In the initialization stage, the signal S1 on the first scan signal line and the signal S2 on the second scan signal line are each a low level. The signal EMIT on the light emission control signal line EM, the signal S3 on the third scan signal line, the signal S4 on the fourth scan signal line, and the signal Reset output by the reset signal output terminal RESET1 are each a high level. At this time, the fifth transistor T5, and the seventh transistor T7 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are turned off. The potential on the first reference voltage output terminal VREF1 is applied to the first capacitor Cst through the fifth transistor T5, that is, the potential of the first node N1 is the initialization voltage Vref. At this time, the potential of the control terminal of a drive transistor T3 is also the initialization voltage Vref, and the residual charge of the previous frame in the control terminal of the drive transistor T3 is cleared. At the same time, the fifth transistor T5 is a double-gate transistor. Thus, the current leakage phenomenon in the pixel driving circuit is further reduced, and the stability of the potential of the first node N1 is ensured. In the initialization stage, the seventh transistor T7 is also turned on. The seventh transistor T7 writes the potential on the second reference voltage output terminal VREF2 to the first terminal of the light-emitting unit 107, and then the potential on the first terminal of the light-emitting unit 107 is initialized. In this manner, the influence of the voltage of the first terminal of the light-emitting unit 107 of a preceding frame on the voltage of the first terminal of the light-emitting unit 107 of a succeeding frame is reduced, and display uniformity is further improved.
In the data write stage, the signal S3 on the third scan signal line and the signal S4 on the fourth scan signal line are each a low level. The signal S1 on the first scan signal line, the signal S2 on the second scan signal line, the signal EMIT on the light emission control signal line EM and the signal Reset output by the reset signal output terminal RESET1 are each a high level. The second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. At this time, the data signal Vdata is written into the second transistor T2 and the fourth transistor T4. The potential of the control terminal of the drive transistor T3 is the initialization voltage Vref and also a low potential. The third transistor T3 is also turned on. The data signal Vdata on the data signal line DATA is written into the second transistor T2, the third transistor T3, and the fourth transistor T4 and is applied to the first node N1. The potential of the first node N1 is gradually pulled up by the potential on the data signal line DATA. When the gate voltage of the third transistor T3 is pulled up to a voltage, where the voltage difference between this voltage and the voltage of the source of the third transistor is equal to the threshold voltage of the third transistor T3, the third transistor T3 is in an off state, and the data write stage ends. At the same time, the fourth transistor T4 is a double-gate transistor. Thus, the current leakage phenomenon in the pixel driving circuit is reduced, and the stability of the potential of the first node N1 is ensured.
In the light emission stage, the signal EMIT on the light emission control signal line EM is a low level. The signal S1 on the first scan signal line, the signal S2 on the second scan signal line, the signal S3 on the third scan signal line, the signal S4 on the fourth scan signal line, and the signal Reset output by the reset signal output terminal RESET1 are each a high level. At this time, the first transistor T1 and the sixth transistor T6 are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off. A path is formed between the first power supply PVDD and the second power supply PVEE. The third transistor T3 outputs the light-emitting drive signal to the light-emitting unit 107. The light-emitting unit 107 emits light.
In the pixel driving circuit, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are each an n-type transistor. An n-type transistor is turned on at a high level and is turned off at a low level. The principle of the specific working process of the pixel driving circuit is the same as that of the pixel driving circuit in which the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are each a p-type transistor. Repetition is not made herein.
Optionally, with continued reference to
In the power-on reset stage, the first transistor T1, the sixth transistor T6, and the eighth transistor T8 are driven to turn on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh T7 are driven to turn off. In an initialization sub-stage in a scan time period, the fifth transistor T5, and the seventh transistor T7 are driven to turn on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are driven to turn off. In the data write stage in the scan time period, the second transistor T2, the third transistor T3, and the fourth transistor T4 are driven to turn on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are driven to turn off. In the light emission stage in the scan time period, the first transistor T1, the third transistor T3, and the sixth transistor T6 are driven to turn on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are driven to turn off.
In the power-on reset stage, the signal S1 on the first scan signal line, the signal S2 on the second scan signal line, the signal S3 on the third scan signal line, and the signal S4 on the fourth scan signal line are each a high level. The signal Reset output by the reset signal output terminal RESET1 and the signal EMIT on the light emission control signal line EM are each a low level. The first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first transistor T1, the sixth transistor T6, and the eighth transistor T8 are turned on. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh T7 are turned off.
In the initialization sub-stage in the scan time period, the signal S1 on the first scan signal line and the signal S2 on the second scan signal line are each a low level. The signal EMIT on the light emission control signal line EM, the signal S3 on the third scan signal line, the signal S4 on the fourth scan signal line, and the signal Reset output by the reset signal output terminal RESET1 are each a high level. The fifth transistor T5 and the seventh transistor T7 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are turned off.
In the data write stage in the scan time period, the signal S3 on the third scan signal line and the signal S4 on the fourth scan signal line are each a low level. The signal S1 on the first scan signal line, the signal S2 on the second scan signal line, the signal EMIT on the light emission control signal line EM, and the signal Reset output by the reset signal output terminal RESET1 are each a high level. The second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off.
In the light emission stage in the scan time period, the signal EMIT on the light emission control signal line EM is a low level. The signal S1 on the first scan signal line, the signal S2 on the second scan signal line, the signal S3 on the third scan signal line, the signal S4 on the fourth scan signal line, and the signal Reset output by the reset signal output terminal RESET1 are each a high level. The first transistor T1, the third transistor T3, and the sixth transistor T6 are turned on. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off.
Optionally,
Since the fifth transistor T5 and the seventh transistor T7 are each a p-type transistor, in the initialization stage, the fifth transistor T5 and the seventh transistor T7 may be turned on at the same time. At this time, the control terminal of the fifth transistor T5 and the control terminal of the seventh transistor T7 may access the same low-level scan signal. In this manner, the first scan signal line may also serve as the second scan signal line to ensure that in the initialization stage, the fifth transistor T5 and the seventh transistor T7 are turned on at the same time; and in a non-initialization stage, the fifth transistor T5 and the seventh transistor T7 are turned off at the same time. Similarly, since the second transistor T2 and the fourth transistor T4 are each a p-type transistor, in the initialization stage, the second transistor T2 and the fourth transistor T4 may be turned on at the same time. At this time, the control terminal of the second transistor T2 and the control terminal of the fourth transistor T4 may access the same low-level scan signal. In this manner, the third scan signal line may also serve as the fourth scan signal line to ensure that in the data write stage, the second transistor T2 and the fourth transistor T4 are turned on at the same time; and in a non-data write stage, the second transistor T2 and the fourth transistor T4 are turned off at the same time. The multiplexing of scan lines can effectively reduce the number of scan lines, reduce the manufacturing cost, and simplify the complexity of the pixel driving circuit.
Optionally,
The third transistor T3 is a p-type transistor. The third transistor T3 is turned on at a low level and is turned off at a high level. Since in the power-on reset stage, to prevent the third transistor T3 from being abnormally turned on, at this time, it is necessary to write a high level to the control terminal of the third transistor T3. As shown in
Optionally, with continued reference to
As shown in
Optionally,
Since the fifth transistor T5 and the seventh transistor T7 are each an n-type transistor, in the initialization stage, the fifth transistor T5 and the seventh transistor T7 may be turned on at the same time. At this time, the control terminal of the fifth transistor T5 and the control terminal of the seventh transistor T7 may access the same high-level scan signal. In this manner, the first scan signal line may also serve as the second scan signal line to ensure that in the initialization stage, the fifth transistor T5 and the seventh transistor T7 are turned on at the same time; and in the non-initialization stage, the fifth transistor T5 and the seventh transistor T7 are turned off at the same time. Similarly, since the second transistor T2 and the fourth transistor T4 are each an n-type transistor, in the initialization stage, the second transistor T2 and the fourth transistor T4 may be turned on at the same time. At this time, the control terminal of the second transistor T2 and the control terminal of the fourth transistor T4 may access the same high-level scan signal. In this manner, the third scan signal line may also serve as the fourth scan signal line to ensure that in the data write stage, the second transistor T2 and the fourth transistor T4 are turned on at the same time; and in the non-data write stage, the second transistor T2 and the fourth transistor T4 are turned off at the same time. The multiplexing of the scan lines can effectively reduce the number of scan lines, reduce the manufacturing cost, and simplify the complexity of the pixel driving circuit.
Optionally,
The third transistor T3 is an n-type transistor. The third transistor T3 is turned on at a high level and is turned off at a low level. Since in the power-on reset stage, to prevent the third transistor T3 from being abnormally turned on, at this time, it is necessary to write a low level to the control terminal of the third transistor T3. As shown in
Optionally, as shown in
As shown in
Optionally,
The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are each a p-type transistor and are prepared by using an LTPS process. Since the fifth transistor T5 is an n-type transistor, and the seventh transistor T7 is a p-type transistor, in the initialization stage, the fifth transistor T5 and the seventh transistor T7 may be turned on at the same time. At this time, the first scan signal line connected to the control terminal of the fifth transistor T5 is at a high level, and the second scan signal line connected to the control terminal of the seventh transistor T7 is at a low level. In the non-initialization stage, the fifth transistor T5 and the seventh transistor T7 may be turned off at the same time. At this time, the first scan signal line connected to the control terminal of the fifth transistor T5 is at a low level, and the second scan signal line connected to the control terminal of the seventh transistor T7 is at a high level. In this manner, the timing of the signal output by the first scan signal line and the timing of the signal output by the second scan signal line are controlled to be the same, and the direction of the signal output by the first scan signal line and the direction of the signal output by the second scan signal line are controlled to be opposite. Then it is ensured that the fifth transistor T5 and the seventh transistor T7 can be turned on or off at the same time. Since the second transistor T2 is an n-type transistor, and the fourth transistor T4 is a p-type transistor, in the initialization stage, the second transistor T2 and the fourth transistor T4 may be turned on at the same time. At this time, the fourth scan signal line connected to the control terminal of the second transistor T2 is at a low level, and the third scan signal line connected to the control terminal of the fourth transistor T4 is at a high level. In the non-initialization stage, the second transistor T2 and the fourth transistor T4 may be turned off at the same time. At this time, the fourth scan signal line connected to the control terminal of the second transistor T2 is at a high level, and the third scan signal line connected to the control terminal of the fourth transistor T4 is at a low level. In this manner, the timing of the signal output by the third scan signal line and the timing of the signal output by the fourth scan signal line are controlled to be the same, and the direction of the signal output by the third scan signal line and the direction of the signal output by the fourth scan signal line are controlled to be opposite. Then it is ensured that the second transistor T2 and the fourth transistor T4 can be turned on or off at the same time. The fourth transistor T4 and the fifth transistor T5 are converted into double-gate n-type transistors. In this manner, the current leakage phenomenon in the pixel driving circuit can be effectively avoided, and the stability of the potential of the first node N1 is ensured. Moreover, the normal working of the pixel driving circuit is ensured, and the display effect of the display panel is ensured.
Optionally,
The third transistor T3 is a p-type transistor. The third transistor T3 is turned on at a high level and is turned off at a low level. Since in the power-on reset stage, to prevent the third transistor T3 from being abnormally turned on, at this time, it is necessary to write a low level to the control terminal of the third transistor T3. As shown in
In S101, in the power-on reset stage, the reset unit is controlled to transmit the reset power supply to the control terminal of the drive unit.
The reset unit writes the signal output by the reset power supply to the control terminal of the drive unit before the scan time period, so that in the power-on reset stage, the drive unit is in the off state. In this manner, there is no abnormally turn-on phenomenon, thereby ensuring the normal display of the display panel, and avoiding the occurrence of the screen flicker phenomenon.
In S102, in the initialization sub-stage in the scan time period, the initialization unit is controlled to transmit the corresponding initialization voltage to the control terminal of the drive unit and the first terminal of the light-emitting unit.
The control terminal of the drive unit is initialized before the data write stage to clear the gate potential of the transistor in the drive unit in the previous frame. In this manner, the data voltage in the data write stage is written. Thus, the display effect of the display panel is ensured.
In S103, in the data write stage in the scan time period, the threshold compensation unit is controlled to write the threshold voltage of the drive unit to the control terminal of the drive unit, and the data write unit is controlled to write the data voltage to the control terminal of the drive unit.
In the data write stage, the threshold compensation unit captures the threshold voltage of the drive unit and writes the threshold voltage to the control terminal of the drive unit, thereby implementing the compensation of the threshold voltage. At the same time, the data write unit writes the data voltage to the control terminal of the drive unit, thereby ensuring the display uniformity of the display panel.
In S104, in the light emission stage in the scan time period, the first power supply, the drive unit, the light-emitting unit, and the second power supply are controlled to form a path, and the light-emitting unit is driven to emit light.
In the light emission stage, the drive unit generates a driving circuit according to the data voltage, and the light-emitting unit emits light in response to a drive current, thereby implementing the to-be-displayed brightness.
In this embodiment of the present disclosure, a power-on reset operation is performed on the drive unit before the scan time period, so that the drive unit may not be abnormally turned on in a non-scan time period. In this manner, the light-emitting unit may not be abnormally lighted, and the screen flicker phenomenon of the display panel may not be caused. Thus, the display effect of the display panel is ensured.
Optionally, after each power-on operation, the power-on reset stage is executed once, and the scan time period is executed multiple times. For example, the scan time period may be cyclically executed merely after the power-on reset stage during the power-on period to effectively save scan time and increase a refresh frequency. After each power-on operation is executed by the pixel circuit, the operation of the power-on reset stage is executed before the scan time period, so that the drive unit may not be abnormally turned on before the scan time period. In this manner, the change in the display brightness of the light-emitting unit in the non-display stage may not be occurs, and the normal display effect of the display panel may not be affected. Alternatively, before each scan time period, the preceding power-on reset stage may be performed to further improve the display effect of the display panel.
Based on the same inventive concept, an embodiment of the present disclosure provides a light-emitting panel.
It is to be noted that since the display device provided by this embodiment has the same or corresponding beneficial effects as the display panel according to the preceding embodiment, the details are not repeated here. The display device 300 provided by this embodiment of the present disclosure may be a phone shown in
It is to be noted that the preceding are only preferred embodiments of the present disclosure and the technical principles used therein. It is to be understood by those skilled in the art that the present disclosure is not limited to the embodiments described herein. For those skilled in the art, various apparent modifications, adaptations, and substitutions can be made without departing from the scope of the present disclosure. Therefore, while the present disclosure is described in detail in connection with the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210772995.8 | Jun 2022 | CN | national |
