Pixel-driving circuit

Abstract

A pixel driving circuit includes a first pixel, a second pixel, and a data driving circuit. Each pixel includes a main region and a sub region. The main region stores a gray level voltage and the sub region stores a gray level voltage corresponding to the gray level voltage stored in the main region when the main region and the sub region display image. In the data driving circuit, first, second, third, and fourth gray level voltages are generated by means of a first selecting circuit outputting first digital data corresponding to the first pixel and second digital data corresponding to the second pixel to the corresponding digital-to-analog converters. The first, second, third, and fourth gray level voltages are distributed to the main and sub regions of the first and second pixels by a second selecting circuit, thereby reducing the number of digital-to-analog converters.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to a pixel driving circuit, and more particularly, to a pixel driving circuit in which a number of digital-to-analog converters required by a data driving circuit can be reduced.

2. Description of the Prior Art

Please refer to FIG. 1. FIG. 1 is a diagram illustrating a pixel driving circuit 100 of the prior art for reducing color washout. The pixel driving circuit 100 comprises a plurality of pixels, data lines DL₁-DL_M, scan lines SL₁-SL_N, a data driving circuit 110 and a scan driving circuit 120. Pixels PIX₁ and PIX₂ are utilized to exemplify structures of the plurality of pixels. The pixel PIX₁ comprises transistors Q₁ and Q₂, a main region MR₁ and a sub region SR₁. The transistor Q₁ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₁ is coupled to the data line DL_X, the second electrode 2 of the transistor Q₁ is coupled to the main region MR₁, and the gate end G of the transistor Q₁ is coupled to a scan line SL_Y. The transistor Q₂ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₂ is coupled to the data line DL_(X+1), the second electrode 2 of the transistor Q₂ is coupled to the sub region SR₁, and the gate end G of the transistor Q₂ is coupled to the scan line SL_Y. The pixel PIX₂ comprises transistors Q₃ and Q₄, a main region MR₂ and a sub region SR₂. The transistor Q₃ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₃ is coupled to the data line DL_(X+2), the second electrode 2 of the transistor Q₃ is coupled to the sub region SR₂, and the gate end G of the transistor Q₃ is coupled to the scan line SL_Y. The transistor Q₄ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₄ is coupled to the data line DL_(X+3), the second electrode 2 of the transistor Q₄ is coupled to the main region MR₂, and the gate end G of the transistor Q₂ is coupled to the scan line SL_Y.

When a scan driving circuit 120 drives the scan line SL_Y, transistors Q₁-Q₄ are turned on, for the main region MR₁ to couple to the data line DL_X via the transistor Q₁, the sub region SR₁ to couple to the data line DL_(X+1) via the transistor Q₂, the sub region SR₂ to couple to the data line DL_(X+2) via the transistor Q₃, and the main region MR₂ to couple to the data line DL_(X+3) via the transistor Q₄.

Assume the pixel PIX₁ is to display frames corresponding to digital data DA₁, and the pixel PIX₂ is to display frames corresponding to digital data DA₂. For the pixel PIX₁, the main region MR₁ and the sub region SR₁ receive and store gray level voltages corresponding to the digital data DA₁ from the data driving circuit 110 via data lines D_X and D_(X+1) respectively. For the pixel PIX₂, the main region MR₂ and the sub region SR₂ receive and store gray level voltages corresponding to the digital data DA₂ from the data driving circuit 110 via data lines D_(X+3) and D_(X+2) respectively. Further, a voltage level of the gray level voltage stored in the main region MR₁ corresponds to a voltage level of the gray level voltage stored in the sub region SR₁, and a voltage level of the gray level voltage stored in the main region MR₂ also corresponds to a voltage level of the gray level voltage stored in the sub region SR₂, so as to reduce color offset when viewing the pixel driving circuit 100 from different viewing angles.

However, since in the pixel driving circuit 100, the gray level voltage stored in the main region MR₁ is different from that of the sub region SR₁, the gray level voltage stored in the main region MR₂ is different from that of the sub region SR₂, and a rotating polarity for each region (MR₁, MR₂, SR₁, SR₂) can be positive or negative, the data driving circuit 110 requires a corresponding digital-to-analog converter and a corresponding negative digital-to-analog converter for each of the data lines DL_X-DL_(X+3), for providing positive and negative gray level voltages to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂. In other words, when the pixel driving circuit 100 comprises M data lines, the data driving circuit 110 requires 2*M digital-to-analog converters. Since digital-to-analog converters occupy substantial circuit area, the cost of the data driving circuit 110 and the power consumption of the pixel driving circuit 100 are significantly increased, causing inconvenience to the user.

SUMMARY OF THE INVENTION

The present invention discloses a pixel driving circuit. The pixel driving circuit comprises a first pixel, a second pixel and a data driving circuit. The first pixel comprises a first main region and a first sub region. The first main region is coupled to a first data line and a scan line. The first sub region is coupled to a second data line and the scan line. Each of the first main region and the first sub region stores a gray level voltage corresponding to first digital data. The second pixel comprises a second main region and a second sub region. The second sub region is coupled to a third data line and the scan line. The second main region is coupled to a fourth data line and the scan line. Each of the second main region and the second sub region stores a gray level voltage corresponding to second digital data. The data driving circuit comprises a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, a fourth digital-to-analog converter, a first selecting circuit and a second selecting circuit. The first digital-to-analog converter is for converting the first digital data or the second digital data to a first gray level voltage according to a positive main region gamma voltage. The second digital-to-analog converter is for converting the first digital data or the second digital data to a second gray level voltage according to a positive sub region gamma voltage. The third digital-to-analog converter is for converting the first digital data or the second digital data to a third gray level voltage according to a negative sub region gamma voltage. The fourth digital-to-analog converter is for converting the first digital data or the second digital data to a fourth gray level voltage according to a negative main region gamma voltage. The first selecting circuit is for selecting the first digital data according to a gamma voltage selecting signal and a polarity signal, for inputting the first digital data into two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters, and inputting the second digital data into the other two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters. The second selecting circuit is for distributing the first, the second, the third and the fourth gray level voltages to the first main region, the second main region, the first sub region and the second sub region via the first, the second, the third and the fourth data lines, according to the gamma voltage selecting signal and the polarity signal.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a pixel driving circuit of prior art for reducing color washout.

FIG. 2 is a diagram illustrating a pixel driving circuit according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a partial structure of a data driving circuit in FIG. 2.

FIG. 4 is a diagram illustrating operation of the data driving circuit when rotating polarities of the main region, the sub region, the sub region and the main region of the pixel driving circuit are positive, negative, positive, and negative respectively.

FIG. 5 is a diagram illustrating operation of the data driving circuit when the rotating polarities of the main region, the sub region, the sub region and the main region of the pixel driving circuit are negative, positive, negative and positive respectively.

FIG. 6 is a diagram illustrating a pixel driving circuit according to another embodiment of the present invention.

FIG. 7 is a diagram illustrating operation of the data driving circuit when the rotating polarities of the sub region, the main region, the main region and the sub region of the pixel driving circuit are positive, negative, positive, and negative respectively.

FIG. 8 is a diagram illustrating operation of the data driving circuit when the rotating polarities of the sub region, the main region, the main region and the sub region of the pixel driving circuit are negative, positive, negative and positive respectively.

FIG. 9 is a diagram illustrating a pixel driving circuit according to another embodiment of the present invention.

FIG. 10 is a diagram illustrating a partial structure of a data driving circuit of the pixel driving circuit of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2 and FIG. 3. FIG. 2 is a diagram illustrating a pixel driving circuit 200 according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a partial structure of a data driving circuit 210 in FIG. 2. The pixel driving circuit 200 comprises a plurality of pixels, data lines DL₁-DL_m, scan lines SL₁-SL_N, a data driving circuit 210 and a scan driving circuit 220. Pixels PIX₁ and PIX₂ are utilized to exemplify structures of the plurality of pixels. The pixel PIX₁ comprises transistors Q₁ and Q₂, a main region MR₁ and a sub region SR₁. The transistor Q₁ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₁ is coupled to the data line DL_X, the second electrode 2 of the transistor Q₁ is coupled to the main region MR₁, and the gate end G of the transistor Q₁ is coupled to a scan line SL_Y. The transistor Q₂ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₂ is coupled to the data line DL_(X+1), the second electrode 2 of the transistor Q₂ is coupled to the sub region SR₁, and the gate end G of the transistor Q₂ is coupled to the scan line SL_Y. The pixel PIX₂ comprises transistors Q₃ and Q₄, a main region MR₂ and a sub region SR₂. The transistor Q₃ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₃ is coupled to the data line DL_(X+2), the second electrode 2 of the transistor Q₃ is coupled to the sub region SR₂, and the gate end G of the transistor Q₃ is coupled to the scan line SL_Y. The transistor Q₄ comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q₄ is coupled to the data line DL_(X+3), the second electrode 2 of the transistor Q₄ is coupled to the main region MR₂, and the gate end G of the transistor Q₂ is coupled to the scan line SL_Y.

When a scan driving circuit 220 drives the scan line SL_Y, transistors Q₁-Q₄ are turned on for the main region MR₁ to couple to the data line DL_X via the transistor Q₁, the sub region SR₁ to couple to the data line DL_(X+1) via the transistor Q₂, the sub region SR₂ to couple to the data line DL_(X+2) via the transistor Q₃, and the main region MR₂ to couple to the data line DL_(X+3) via the transistor Q₄.

Assume the pixel PIX₁ is to display frames corresponding to digital data DA₁, and the pixel PIX₂ is to display frames corresponding to digital data DA₂. For the pixel PIX₁, the main region MR₁ and the sub region SR₁ receive and store gray level voltages corresponding to the digital data DA₁ from the data driving circuit 210 via data lines D_X and D_(X+1) respectively. For the pixel PIX₂, the main region MR₂ and the sub region SR₂ receive and store gray level voltages corresponding to the digital data DA₂ from the data driving circuit 210 via data lines D_(X+3) and D_(X+2), respectively, for reducing a color offset issue when viewing the pixel driving circuit 200 from different viewing angles.

FIG. 3 illustrates the structure of the data driving circuit 210 utilized to drive the data lines DL_X-DL_(X+3). Structures of the data driving circuit 210 utilized to drive other data lines can be extrapolated accordingly. The data driving circuit 210 comprises digital-to-analog converters DAC₁-DAC₄, selecting circuits 211 and 212, data latches DH₁-DH₄ and level shifters LS₁-LS₄. The selecting circuit 211 selects the digital data DA₁ according to a gamma voltage selecting signal S_G—SEL and a polarity signal S_POL, for inputting the digital data DA₁ into two digital-to-analog converters of the digital-to-analog converters DAC₁-DAC₄, and inputting the digital data DA₂ into the other two digital-to-analog converters of the digital-to-analog converters DAC₁-DAC₄. The data latches DH₁-DH₄ are for latching digital data outputted by the selecting circuit 211. The level shifters LS₁-LS₄ are for increasing a voltage level of digital data outputted by the data latches DH₁-DH₄.

The digital-to-analog converter DAC₁ converts the digital data (DA₁ or DA₂) outputted by the level shifter LS₁ to a gray level voltage V_G1 according to a positive main region gamma voltage V_PA. The digital-to-analog converter DAC₂ converts the digital data (DA₁ or DA₂) outputted by the level shifter LS₂ to a gray level voltage V_G2 according to a positive sub region gamma voltage V_PB. The digital-to-analog converter DAC₃ converts the digital data (DA₁ or DA₂) outputted by the level shifter LS₃ to a gray level voltage V_G3 according to a negative sub region gamma voltage V_NB. The digital-to-analog converter DAC₄ converts the digital data (DA₁ or DA₂) outputted by the level shifter LS₄ to a gray level voltage V_G4 according to a negative main region gamma voltage V_NA.

The selecting circuit 212 distributes the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂ via the data lines DL_X-DL_(X+3) according to the gamma voltage selecting signal S_G—SEL and the polarity signal S_POL. In the data driving circuit 210, the selecting circuit 211 is utilized to input the digital data DA₁ (corresponding to the pixel PIX₁) and the digital data DA₂ (corresponding to the pixel PIX₂) into corresponding digital-to-analog converters for generating gray level voltages V_G1-V_G4, and the selecting circuit 212 is utilized to distribute the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂ in pixels PIX₁ and PIX₂. This way, number of digital-to-analog converters required by the data driving circuit 210 can be reduced. The relative operation principle is further explained below.

The selecting circuit 211 comprises an XOR gate 2111 and multiplexers MUX₁-MUX₄. The XOR gate 211 performs logic calculations according to the gamma voltage selecting signal S_{G SEL} and the polarity signal S_POL for generating a control signal S_C. When the gamma voltage selecting signal S_G—SELand the polarity signal S_POL, are both logic “0” or “1”, the control signal S_C is logic “0”; when the gamma voltage selecting signal S_G—SEL is logic “0” and the polarity signal S_POL is logic “1”, the control signal S_C is logic “1”; and when the gamma voltage selecting signal S_G—SEL is logic “1” and the polarity signal S_POL is logic “0”, the control signal S_C is logic “1”.

The multiplexer MUX₁ comprises an input end I₁ for receiving the digital data DA₂, an input end I₂ for receiving the digital data DA₁ and a control end C for receiving the control signal S_C. The multiplexer MUX₁ couples the input end I₁ or I₂ of the multiplexer MUX₁ to an output end O of the multiplexer MUX₁ according to the control signal S_C. The multiplexer MUX₂ comprises an input end I₁ for receiving the digital data DA₁, an input end I₂ for receiving the digital data DA₂ and a control end C for receiving the control signal S_C. The multiplexer MUX₂ couples the input end I₁ or I₂ of the multiplexer MUX₂ to an output end O of the multiplexer MUX₂ according to the control signal S_C. The multiplexer MUX₃ comprises an input end I₁ for receiving the digital data DA₂, an input end I₂ for receiving the digital data DA₁ and a control end C for receiving the control signal S_C. The multiplexer MUX₃ couples the input end I₁ or I₂ of the multiplexer MUX₃ to an output end O of the multiplexer MUX₃ according to the control signal S_C. The multiplexer MUX₄ comprises an input end I₁ for receiving the digital data DA₁, an input end I₂ for receiving the digital data DA₂ and a control end C for receiving the control signal S_C. The multiplexer MUX₄ couples the input end I₁ or I₂ of the multiplexer MUX₄ to an output end O of the multiplexer MUX₄ according to the control signal S_C.

In the present embodiment, when the control signal S_C is logic “0”, the input ends I₁ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively; and when the control signal S_C is logic “1”, the input ends I₂ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively.

The data latches DH₁-DH₄ are coupled between the selecting circuit 211 and level shifters LS₁-LS₄ respectively. The data latches DH₁-DH₄ are for latching the digital data outputted from the selecting circuit 211 to the digital-to-analog converters DAC₁-DAC₄ respectively. The level shifters LS₁-LS₄ are coupled between the selecting circuit 211 (via the data latches DH₁-DH₄) and the digital-to-analog converters DAC₁-DAC₄ respectively. The level shifters LS₁-LS₄ are for increasing the voltage level of the digital data outputted from the selecting circuit 211 to the digital-to-analog converters DAC₁-DAC₄ respectively.

The selecting circuit 212 comprises multiplexers MUX₅-MUX₈, buffers BUF₁-BUF₄ and polarity selecting circuits 2121 and 2122. The multiplexer MUX₅ comprises an input end I₁ for receiving the gray level voltage V_G2, an input end I₂ for receiving the gray level voltage V_G1, a control end C for receiving the control signal S_C and an output end O. The multiplexer MUX₅ couples the input end I₁ or I₂ of the multiplexer MUX₅ to the output end O of the multiplexer MUX₅ according to the control signal S_C. The multiplexer MUX₆ comprises an input end I₁ for receiving the gray level voltage V_G4, an input end I₂ for receiving the gray level voltage V_G3, a control end C for receiving the control signal S_C and an output end O. The multiplexer MUX₆ couples the input end I₁ or I₂ of the multiplexer MUX₆ to the output end O of the multiplexer MUX₆ according to the control signal S_C. The multiplexer MUX₇ comprises an input end I₁ for receiving the gray level voltage V_G1, an input end I₂ for receiving the gray level voltage V_G2, a control end C for receiving the control signal S_C and an output end O. The multiplexer MUX₇ couples the input end I₁ or I₂ of the multiplexer MUX₇ to the output end O of the multiplexer MUX₇ according to the control signal S_C. The multiplexer MUX₈ comprises an input end I₁ for receiving the gray level voltage V_G3, an input end I₂ for receiving the gray level voltage V_G4, a control end C for receiving the control signal S_C and an output end O. The multiplexer MUX₈ couples the input end I₁ or I₂ of the multiplexer MUX₈ to the output end O of the multiplexer MUX₈ according to the control signal S_C.

When the control signal S_C is logic “0”, the input ends I₁ of the multiplexers MUX₅-MUX₈ are coupled to the output ends O of the multiplexers MUX₅-MUX₈ respectively; and when the control signal S_C is logic “1”, the input ends I₂ of the multiplexers MUX₅-MUX₈ are coupled to the output ends O of the multiplexers MUX₅-MUX₈ respectively.

The polarity selecting circuit 2121 comprises an input end I₁ coupled to the output end O of the multiplexer MUX₅, an input end I₂ coupled to the output end O of the multiplexer MUX₆, an output end O₁ coupled to the data line DL_X, an output end O₂ coupled to the data line DL_(X+1), and a control end C for receiving the polarity signal S_POL. The polarity selecting circuit 2121 couples one of the input ends I₁ and I₂ of the polarity selecting circuit 2121 to the output end O₁ of the polarity selecting circuit 2121, and couples the other input end to the output end O₂ of the polarity selecting circuit 2121, according to the polarity signal S_POL. The polarity selecting circuit 2122 comprises an input end I₁ coupled to the output end O of the multiplexer MUX₇, an input end I₂ coupled to the output end O of the multiplexer MUX₈, an output end O₁ coupled to the data line DL_(X+2), an output end O₂ coupled to the data line DL_(X+3), and a control end C for receiving the polarity signal S_POL. The polarity selecting circuit 2122 couples one of the input ends I₁ and I₂ of the polarity selecting circuit 2122 to the output end O₁ of the polarity selecting circuit 2122, and couples the other input end to the output end O₂ of the polarity selecting circuit 2122, according to the polarity signal S_POL.

When the polarity signal S_POL is logic “0”, the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively. When the polarity signal S_POL, is logic “1”, the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively.

Buffer BUF₁ is coupled between the output end O of the multiplexer MUX₅ and the input end I₁ of the polarity selecting circuits 2121, for buffering a gray level voltage outputted by the output end O of the multiplexer MUX₅. Buffer BUF₂ is coupled between the output end O of the multiplexer MUX₆ and the input end I₂ of the polarity selecting circuits 2121, for buffering a gray level voltage outputted by the output end O of the multiplexer MUX₆. Buffer BUF₃ is coupled between the output end O of the multiplexer MUX₇ and the input end I₁ of the polarity selecting circuits 2122, for buffering a gray level voltage outputted by the output end O of the multiplexer MUX₇. Buffer BUF₄ is coupled between the output end O of the multiplexer MUX₈ and the input end I₂ of the polarity selecting circuits 2122, for buffering a gray level voltage outputted by the output end O of the multiplexer MUX₈.

Please refer to FIG. 4. FIG. 4 is a diagram illustrating operation of the data driving circuit 210 when rotating polarities of the main region MR₁, the sub region SR₁, the sub region SR₂ and the main region MR₂ of the pixel driving circuit 200 are positive, negative, positive, and negative respectively. At first, the gamma voltage selecting signal S_G—SEL is logic “0” and the polarity signal S_POL, is logic “1”, so the XOR gate 2111 outputs the control signal S_C of logic “1”. When the control signal S_C is logic “1”, the input ends I₂ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively. This way, the multiplexer MUX₁ outputs the digital data DA₁ to the digital-to-analog converter DAC₁ via the data latch DH₁ and the level shifter LS₁, the multiplexer MUX₂ outputs the digital data DA₂ to the digital-to-analog converter DAC₂ via the data latch DH₂ and the level shifter LS₂, the multiplexer MUX₃ outputs the digital data DA₁ to the digital-to-analog converter DAC₃ via the data latch DH₃ and the level shifter LS₃, and the multiplexer MUX₄ outputs the digital data DA₂ to the digital-to-analog converter DAC₄ via the data latch DH₄ and the level shifter LS₄.

The digital-to-analog converter DAC₁ converts the digital data DA₁ to the gray level voltage V_G1 according to the positive main region gamma voltage V_PA. The digital-to-analog converter DAC₂ converts the digital data DA₂ to the gray level voltage V_G2 according to the positive sub region gamma voltage V_PB. The digital-to-analog converter DAC₃ converts the digital data DA₁ to the gray level voltage V_G3 according to the negative sub region gamma voltage V_NB. The digital-to-analog converter DAC₄ converts the digital data DA₂ to the gray level voltage V_G4 according to the negative main region gamma voltage V_NA. At that moment, the multiplexers MUX₅-MUX₈ couple the input ends I₂ of the multiplexers MUX₅-MUX₈ to the output ends O of the multiplexers MUX₅-MUX₈ respectively, according to the control signal S_C at logic “1”. This way, the multiplexer MUX₅ outputs the gray level voltage V_G1 to the input end I₁ of the polarity selecting circuit 2121 via the buffer BUF₁, the multiplexer MUX₆ outputs the gray level voltage V_G3 to the input end I₂ of the polarity selecting circuit 2121 via the buffer BUF₂, the multiplexer MUX₇ outputs the gray level voltage V_G2 to the input end I₁ of the polarity selecting circuit 2122 via the buffer BUF₃, and the multiplexer MUX₈ outputs the gray level voltage V_G4 to the input end I₂ of the polarity selecting circuit 2122 via the buffer BUF₄.

Since the polarity signal S_POL, is logic “1”, the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively. This way, the polarity selecting circuit 2121 outputs the gray level voltage V_G1 which is obtained from converting the digital data DA₁ according to the positive main region gamma voltage V_PA to the main region MR₁ via the data line DL_X, and the polarity selecting circuit 2121 outputs the gray level voltage V_G3 which is obtained from converting the digital data DA₁ according to the negative sub region gamma voltage V_NB to the sub region SR₁ via the data line DL_(X+1). The polarity selecting circuit 2122 outputs the gray level voltage V_G2 which is obtained from converting the digital data DA₂ according to the positive sub region gamma voltage V_PB to the sub region SR₂ via the data line DL_(X+2), and the polarity selecting circuit 2122 outputs the gray level voltage V_G4 which is obtained from converting the digital data DA₂ according to the negative main region gamma voltage V_NA to the main region MR₂ via the data line DL_(X+3).

Therefore, when rotating polarities of the main region MR₁, the sub region SR₁, the sub region SR₂ and the main region MR₂ of the pixel driving circuit 200 are positive, negative, positive, and negative respectively, the selecting circuit 211 can be controlled to input the digital data DA₁ and DA₂ to the corresponding digital-to-analog converters according to the gamma voltage selecting signal S_G—SEL at logic “0” and the polarity signal S_POL, at logic “1”, for generating gray level voltages V_G1-V_G4, and controlling the selecting circuit 212 to correctly distribute the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂.

Please refer FIG. 5. FIG. 5 is a diagram illustrating operation of the data driving circuit 210 when the rotating polarities of the main region MR₁, the sub region SR₁, the sub region SR₂ and the main region MR₂ of the pixel driving circuit 200 are negative, positive, negative and positive respectively. At that moment, the gamma voltage selecting signal S_G—SEL is logic “0” and the polarity signal S_POL, is logic “0”, so the XOR gate 2111 outputs the control signal S_C of logic “0”. When the control signal S_C is logic “0”, the input ends I₁ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively. This way, the multiplexer MUX₁ outputs the digital data DA₂ to the digital-to-analog converter DAC₁ via the data latch DH₁ and the level shifter LS₁, the multiplexer MUX₂ outputs the digital data DA₁ to the digital-to-analog converter DAC₂ via the data latch DH₂ and the level shifter LS₂, the multiplexer MUX₃ outputs the digital data DA₂ to the digital-to-analog converter DAC₃ via the data latch DH₃ and the level shifter LS₃, and the multiplexer MUX₄ outputs the digital data DA₁ to the digital-to-analog converter DAC₄ via the data latch DH₄ and the level shifter LS₄.

The digital-to-analog converter DAC₁ converts the digital data DA₂ to the gray level voltage V_G1 according to the positive main region gamma voltage V_PA. The digital-to-analog converter DAC₂ converts the digital data DA₁ to the gray level voltage V_G2 according to the positive sub region gamma voltage V_PB. The digital-to-analog converter DAC₃ converts the digital data DA₂ to the gray level voltage V_G3 according to the negative sub region gamma voltage V_NB. The digital-to-analog converter DAC₄ converts the digital data DA₁ to the gray level voltage V_G4 according to the negative main region gamma voltage V_NA. At that moment, the multiplexers MUX₅-MUX₈ couple the input ends I₁ of the multiplexers MUX₅-MUX₈ to the output ends O of the multiplexers MUX₅-MUX₈ respectively, according to the control signal S_C of logic “0”. This way, the multiplexer MUX₅ outputs the gray level voltage V_G2 to the input end I₁ of the polarity selecting circuit 2121 via the buffer BUF₁, the multiplexer MUX₆ outputs the gray level voltage V_G4 to the input end I₂ of the polarity selecting circuit 2121 via the buffer BUF₂, the multiplexer MUX₇ outputs the gray level voltage V_G1 to the input end I₁ of the polarity selecting circuit 2122 via the buffer BUF₃, and the multiplexer MUX₈ outputs the gray level voltage V_G3 to the input end I₂ of the polarity selecting circuit 2122 via the buffer BUF₄.

Since the polarity signal S_POL is logic “0” , the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively. This way, the polarity selecting circuit 2121 outputs the gray level voltage V_G4 which is obtained from converting the digital data DA₁ according to the negative main region gamma voltage V_NA to the main region MR₁ via the data line DL_X, and the polarity selecting circuit 2121 outputs the gray level voltage V_G2 which is obtained from converting the digital data DA₁ according to the positive sub region gamma voltage V_PB to the sub region SR₁ via the data line DL_(X+1). The polarity selecting circuit 2122 outputs the gray level voltage V_G3 which is obtained from converting the digital data DA₂ according to the negative sub region gamma voltage V_NB to the sub region SR₂ via the data line DL_(X+2), and the polarity selecting circuit 2122 outputs the gray level voltage V_G1 which is obtained from converting the digital data DA₂ according to the positive main region gamma voltage V_PA to the main region MR₂ via the data line DL_(X+3).

Therefore, when the rotating polarities of the main region MR₁, the sub region SR₁, the sub region SR₂ and the main region MR₂ in the pixel driving circuit 200 are negative, positive, negative and positive respectively, the selecting circuit 211 can be controlled to input the digital data DA₁ and DA₂ to the corresponding digital-to-analog converters according to the gamma voltage selecting signal S_G—SEL at logic “0” and the polarity signal S_POL at logic “0” for generating gray level voltages V_G1-V_G4, and controlling the selecting circuit 212 to correctly distribute the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂.

Therefore, regarding data lines DL_X-DL_(X+3) in the pixel driving circuit 200 of the present invention, the data driving circuit 210 only requires four digital-to-analog converters DAC₁-DAC₄ for providing the correct gray level voltages to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂. In other words, when the pixel driving circuit 200 comprises M data lines, the data driving circuit 210 only requires M digital-to-analog converters. Hence, the pixel driving circuit 200 can reduce the number of digital-to-analog converters required compared to the pixel driving circuit 100 of the prior art, and relative power consumption and cost are reduced.

Please refer to FIG. 6. FIG. 6 is a diagram illustrating a pixel driving circuit 600 according to another embodiment of the present invention. The pixel driving circuit 600 is different from the pixel driving circuit 200 in that the second end of the transistor Q₁ is coupled to the sub region SR₁, the second end of the transistor Q₂ is coupled to the main region MR₁, the second end of the transistor Q₃ is coupled to the main region MR₂ and the second end of the transistor Q₄ is coupled to the sub region SR₂. The data driving circuit 210 can still be utilized to correctly distribute gray level voltages to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂. The relative operation principle is further explained below.

Please refer to FIG. 7. FIG. 7 is a diagram illustrating operation of the data driving circuit 210 when the rotating polarities of the sub region SR₁, the main region MR₁, the main region MR₂ and the sub region SR₂ of the pixel driving circuit 600 are positive, negative, positive, and negative respectively. At that moment, the gamma voltage selecting signal S_G—SEL is logic “1” and the polarity signal S_POL, is logic “1”, so the XOR gate 2111 outputs the control signal S_C of logic “0”. When the control signal S_C is logic “0”, the input ends I₁ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively. This way, the multiplexer MUX₁ outputs the digital data DA₂ to the digital-to-analog converter DAC₁ via the data latch DH₁ and the level shifter LS₁, the multiplexer MUX₂ outputs the digital data DA₁ to the digital-to-analog converter DAC₂ via the data latch DH₂ and the level shifter LS₂, the multiplexer MUX₃ outputs the digital data DA₂ to the digital-to-analog converter DAC₃ via the data latch DH₃ and the level shifter LS₃, and the multiplexer MUX₄ outputs the digital data DA₁ to the digital-to-analog converter DAC₄ via the data latch DH₄ and the level shifter LS₄.

The digital-to-analog converter DAC₁ converts the digital data DA₂ to the gray level voltage V_G1 according to the positive main region gamma voltage V_PA. The digital-to-analog converter DAC₂ converts the digital data DA₁ to the gray level voltage V_G2 according to the positive sub region gamma voltage V_PB. The digital-to-analog converter DAC₃ converts the digital data DA₂ to the gray level voltage V_G3 according to the negative sub region gamma voltage V_NB. The digital-to-analog converter DAC₄ converts the digital data DA₁ to the gray level voltage V_G4 according to the negative main region gamma voltage V_NA. At that moment, the multiplexers MUX₅-MUX₈ couple the input ends I₁ of the multiplexers MUX₅-MUX₈ to the output ends O of the multiplexers MUX₅-MUX₈, respectively, according to the control signal S_C of logic “0”. This way, the multiplexer MUX₅ outputs the gray level voltage V_G2 to the input end I₁ of the polarity selecting circuit 2121 via the buffer BUF₁, the multiplexer MUX₆ outputs the gray level voltage V_G4 to the input end I₂ of the polarity selecting circuit 2121 via the buffer BUF₂, the multiplexer MUX₇ outputs the gray level voltage V_G1 to the input end I₁ of the polarity selecting circuit 2122 via the buffer BUF₃, and the multiplexer MUX₈ outputs the gray level voltage V_G3 to the input end I₂ of the polarity selecting circuit 2122 via the buffer BUF₄.

Since the polarity signal S_POT, is logic “1”, the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively. This way, the polarity selecting circuit 2121 outputs the gray level voltage V_G2 which is obtained from converting the digital data DA₂ according to the positive sub region gamma voltage V_PB to the sub region SR₁ via the data line DL_X, and the polarity selecting circuit 2121 outputs the gray level voltage V_G4 which is obtained from converting the digital data DA₁ according to the negative main region gamma voltage V_NA to the main region MR₁ via the data line DL_(X+1). The polarity selecting circuit 2122 outputs the gray level voltage V_G1 which is obtained from converting the digital data DA₂ according to the positive main region gamma voltage V_PA to the sub region MR₂ via the data line DL_(X+2), and the polarity selecting circuit 2122 outputs the gray level voltage V_G3 which is obtained from converting the digital data DA₂ according to the negative sub region gamma voltage V_NB to the sub region SR₂ via the data line DL_(X+3).

Therefore, when the rotating polarities of the sub region SR₁, the main region MR₁, the main region MR₂ and the sub region SR₂ of the pixel driving circuit 600 are positive, negative, positive and negative respectively, the selecting circuit 211 can be controlled to input the digital data DA₁ and DA₂ to the corresponding digital-to-analog converters according to the gamma voltage selecting signal S_G—SEL at logic “1” and the polarity signal S_POL at logic “1” for generating gray level voltages V_G1-V_G4, and controlling the selecting circuit 212 to correctly distribute the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂.

Please refer to FIG. 8. FIG. 8 is a diagram illustrating operation of the data driving circuit 210 when the rotating polarities of the sub region SR₁, the main region MR₁, the main region MR₂ and the sub region SR₂ of the pixel driving circuit 600 are negative, positive, negative and positive respectively. At that moment, the gamma voltage selecting signal S_G—SEL is logic “1” and the polarity signal S_POL, is logic “0”, so the XOR gate 2111 outputs the control signal S_C of logic “1”. When the control signal S_C is logic “1”, the input ends I₂ of the multiplexers MUX₁-MUX₄ are coupled to the output ends O of the multiplexers MUX₁-MUX₄ respectively. This way, the multiplexer MUX₁ outputs the digital data DA₁ to the digital-to-analog converter DAC₁ via the data latch DH₁ and the level shifter LS₁, the multiplexer MUX₂ outputs the digital data DA₂ to the digital-to-analog converter DAC₂ via the data latch DH₂ and the level shifter LS₂, the multiplexer MUX₃ outputs the digital data DA₁ to the digital-to-analog converter DAC₃ via the data latch DH₃ and the level shifter LS₃, and the multiplexer MUX₄ outputs the digital data DA₂ to the digital-to-analog converter DAC₄ via the data latch DH₄ and the level shifter LS₄.

The digital-to-analog converter DAC₁ converts the digital data DA₁ to the gray level voltage V_G1 according to the positive main region gamma voltage V_PA. The digital-to-analog converter DAC₂ converts the digital data DA₂ to the gray level voltage V_G2 according to the positive sub region gamma voltage V_PB. The digital-to-analog converter DAC₃ converts the digital data DA₁ to the gray level voltage V_G3 according to the negative sub region gamma voltage V_NB. The digital-to-analog converter DAC₄ converts the digital data DA₂ to the gray level voltage V_G4 according to the negative main region gamma voltage V_NA. At that moment, the multiplexers MUX₅-MUX₈ couple the input ends I₂ of the multiplexers MUX₅-MUX₈ to the output ends O of the multiplexers MUX₅-MUX₈, respectively, according to the control signal S_C at logic “1”. This way, the multiplexer MUX₅ outputs the gray level voltage V_G1 to the input end I₁ of the polarity selecting circuit 2121 via the buffer BUF₁, the multiplexer MUX₆ outputs the gray level voltage V_G3 to the input end I₂ of the polarity selecting circuit 2121 via the buffer BUF₂, the multiplexer MUX₇ outputs the gray level voltage V_G2 to the input end I₁ of the polarity selecting circuit 2122 via the buffer BUF₃, and the multiplexer MUX₈ outputs the gray level voltage V_G4 to the input end I₂ of the polarity selecting circuit 2122 via the buffer BUF₄.

Since the polarity signal S_POL is logic “0”, the input ends I₁ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₂ of the polarity selecting circuits 2121 and 2122 respectively, and the input ends I₂ of the polarity selecting circuits 2121 and 2122 are coupled to the output ends O₁ of the polarity selecting circuits 2121 and 2122 respectively. This way, the polarity selecting circuit 2121 outputs the gray level voltage V_G3 which is obtained from converting the digital data DA₁ according to the negative sub region gamma voltage V_NB to the sub region SR₁ via the data line DL_X, and the polarity selecting circuit 2121 outputs the gray level voltage V_G1 which is obtained from converting the digital data DA₁ according to the positive main region gamma voltage V_PA to the main region MR₁ via the data line DL_(X+1). The polarity selecting circuit 2122 outputs the gray level voltage V_G4 which is obtained from converting the digital data DA₂ according to the negative main region gamma voltage V_NA to the sub region MR₂ via the data line DL_(X+2), and the polarity selecting circuit 2122 outputs the gray level voltage V_G2 which is obtained from converting the digital data DA₂ according to the positive sub region gamma voltage V_PB to the sub region SR₂ via the data line DL_(X+3).

Therefore, when the rotating polarities of the sub region SR₁, the main region MR₁, the main region MR₂ and the sub region SR₂ of the pixel driving circuit 600 are negative, positive, negative and positive respectively, the selecting circuit 211 can be controlled to input the digital data DA₁ and DA₂ to the corresponding digital-to-analog converters according to the gamma voltage selecting signal S_G—SEL of logic “1” and the polarity signal S_POL at logic “0” for generating gray level voltages V_G1-V_G4, and controlling the selecting circuit 212 to correctly distribute the gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂.

Similarly, regarding data lines DL_X-DL_(X+3) in the pixel driving circuit 600 of the present invention, the data driving circuit 210 only requires four digital-to-analog converters DAC₁-DAC₄ for providing the correct gray level voltages to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂. In other words, when the pixel driving circuit 600 comprises M data lines, the data driving circuit 210 only requires M digital-to-analog converters. Hence, the pixel driving circuit 600 can reduce the number of digital-to-analog converters required compared to the pixel driving circuit 100 of the prior art, and relative power consumption and cost are reduced.

Furthermore, coupling relations between pixels and data lines are not limited to those shown in FIG. 2 or FIG. 6. For instance, please refer to FIG. 9 and FIG. 10. FIG. 9 is a diagram illustrating a pixel driving circuit 900 according to another embodiment of the present invention. FIG. 10 is a diagram illustrating a partial structure of a data driving circuit 910 of the pixel driving circuit 900 of the present invention. Compared to the pixel driving circuit 200, in the pixel driving circuit 900 the main region MR₁ is coupled to the data line DL_X via the transistor Q₁, the sub region SR₁ is coupled to the data line _DL(_X+1) via the transistor Q₂, the main region MR₂ is coupled to the data line DL_(X+2) via the transistor Q₃ and the sub region SR₂ is coupled to the data line DL_(X+3) via the transistor Q₄.

As shown in FIG. 10, the data driving circuit 901 is different from the data driving circuit 210 in that the output end O₁ of the polarity selecting circuit 2122 is coupled to the data line DL(_X+3) and the output end O₂ of the polarity selecting circuit 2122 is coupled to the data line DL_(X+2). This way, for either pixel driving circuit 200 or 900, the output end O₁ of the polarity selecting circuit 2122 is coupled to the sub region SR₂, and the output end O₂ of the polarity selecting circuit 2122 is coupled to the main region MR₂. Therefore, the data driving circuit 901 can distribute correct gray level voltages V_G1-V_G4 to the main regions MR₁ and MR₂ and sub regions SR₁ and SR₂ according to methods explained in FIG. 4 and FIG. 5. In other words, even if the coupling relationships between pixels and data lines are changed in the pixel driving circuit, as long as the structure of the data driving circuit is adjusted correspondingly, the data driving circuit can still distribute correct gray level voltages to the main regions and the sub regions of each pixel.

In summary, the pixel driving circuit provided in the present invention comprises a first pixel, a second pixel, and a data-driving circuit. Each pixel comprises a main region and a sub region. The main region stores a gray level voltage and the sub region stores a gray level voltage corresponding to the gray level voltage stored in the main region when the main region and the sub region display images. In the data driving circuit, a first, a second, a third, and a fourth gray level voltage are generated by means of a first selecting circuit outputting first digital data corresponding to the first pixel and second digital data corresponding to the second pixel to the corresponding digital-to-analog converters, respectively. The first, the second, the third, and the fourth gray level voltages are distributed to the main and sub regions of the first and second pixels by a second selecting circuit. This way, the number of digital-to-analog converters required by the data driving circuit can be reduced, and the cost and power consumption of the pixel driving circuit are reduced.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A pixel driving circuit, comprising: a first pixel, comprising a first main region and a first sub region, wherein the first main region is coupled to a first data line and a scan line, the first sub region is coupled to a second data line and the scan line, and each of the first main region and the first sub region stores a gray level voltage corresponding to first digital data;a second pixel, comprising a second main region and a second sub region, wherein the second sub region is coupled to a third data line and the scan line, the second main region is coupled to a fourth data line and the scan line, and each of the second main region and the second sub region stores a gray level voltage corresponding to second digital data; anda data driving circuit, comprising: a first digital-to-analog converter, for converting the first digital data or the second digital data to a first gray level voltage according to a positive main region gamma voltage;a second digital-to-analog converter, for converting the first digital data or the second digital data to a second gray level voltage according to a positive sub region gamma voltage;a third digital-to-analog converter, for converting the first digital data or the second digital data to a third gray level voltage according to a negative sub region gamma voltage;a fourth digital-to-analog converter, for converting the first digital data or the second digital data to a fourth gray level voltage according to a negative main region gamma voltage;a first selecting circuit, for simultaneously distributing the first digital data and the second digital data according to a gamma voltage selecting signal and a polarity signal such that the first digital data is inputted into two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters while the second digital data is inputted into the other two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters; anda second selecting circuit, for distributing the first, the second, the third and the fourth gray level voltages to the first main region, the second main region, the first sub region and the second sub region via the first, the second, the third and the fourth data lines, according to the gamma voltage selecting signal and the polarity signal.

2. The pixel driving circuit of claim 1, wherein the data driving circuit further comprises: a first level shifter, coupled between the first selecting circuit and the first digital-to-analog converter;a second level shifter, coupled between the first selecting circuit and the second digital-to-analog converter;a third level shifter, coupled between the first selecting circuit and the third digital-to-analog converter; anda fourth level shifter, coupled between the first selecting circuit and the fourth digital-to-analog converter.

3. The pixel driving circuit of claim 1, wherein the data driving circuit further comprises: a first data latch, coupled between the first selecting circuit and the first level shifter;a second data latch, coupled between the first selecting circuit and the second level shifter;a third data latch, coupled between the first selecting circuit and the third level shifter; anda fourth data latch, coupled between the first selecting circuit and the fourth level shifter.

4. The pixel driving circuit of claim 1, wherein: when both of the gamma voltage selecting signal and the polarity signal are a first predetermined logic or a second predetermined logic, the first selecting circuit outputs the second digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the first digital data to the second and the fourth digital-to-analog converters;when the gamma voltage selecting signal is the first predetermined logic and the polarity signal is the second predetermined logic, the first selecting circuit outputs the first digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the second digital data to the second and the fourth digital-to-analog converters; andwhen the gamma voltage selecting signal is the second predetermined logic and the polarity signal is the first predetermined logic, the first selecting circuit outputs the first digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the second digital data to the second and the fourth digital-to-analog converters.

5. The pixel driving circuit of claim 4, wherein the first selecting circuit comprises: an XOR gate, for generating a control signal according to the gamma voltage selecting signal and the polarity signal;a first multiplexer, comprising a first input end for receiving the second digital data, a second input end for receiving the first digital data, a control end for receiving the control signal and an output end, wherein the first multiplexer is for coupling the first input end or the second input end of the first multiplexer to the output end of the first multiplexer according to the control signal;a second multiplexer, comprising a first input end for receiving the first digital data, a second input end for receiving the second digital data, a control end for receiving the control signal and an output end, wherein the second multiplexer is for coupling the first input end or the second input end of the second multiplexer to the output end of the second multiplexer according to the control signal;a third multiplexer, comprising a first input end for receiving the second digital data, a second input end for receiving the first digital data, a control end for receiving the control signal and an output end, wherein the third multiplexer is for coupling the first input end or the second input end of the third multiplexer to the output end of the third multiplexer according to the control signal; anda fourth multiplexer, comprising a first input end for receiving the first digital data, a second input end for receiving the second digital data, a control end for receiving the control signal and an output end, wherein the fourth multiplexer is for coupling the first input end or the second input end of the fourth multiplexer to the output end of the fourth multiplexer according to the control signal.

6. The pixel driving circuit of claim 5, wherein: when both of the gamma voltage selecting signal and the polarity signal are the first predetermined logic or the second predetermined logic, the control signal is the first predetermined logic;when the gamma voltage selecting signal is the first predetermined logic and the polarity signal is the second predetermined logic, the control signal is the second predetermined logic; andwhen the gamma voltage selecting signal is the second predetermined logic and the polarity signal is the first predetermined logic, the control signal is the second predetermined logic.

7. The pixel driving circuit of claim 6, wherein: when the control signal is the first predetermined logic, the first input end of the first multiplexer is coupled to the output end of the first multiplexer, the first input end of the second multiplexer is coupled to the output end of the second multiplexer, the first input end of the third multiplexer is coupled to the output end of the third multiplexer, and the first input end of the fourth multiplexer is coupled to the output end of the fourth multiplexer; andwhen the control signal is the second predetermined logic, the second input end of the first multiplexer is coupled to the output end of the first multiplexer, the second input end of the second multiplexer is coupled to the output end of the second multiplexer, the second input end of the third multiplexer is coupled to the output end of the third multiplexer, and the second input end of the fourth multiplexer is coupled to the output end of the fourth multiplexer.

8. The pixel driving circuit of claim 6, wherein the second selecting circuit comprises: a fifth multiplexer, comprising a first input end for receiving the second gray level voltage, a second input end for receiving the first gray level voltage, a control end for receiving the control signal and an output end, wherein the fifth multiplexer is for coupling the first input end or the second input end of the fifth multiplexer to the output end of the fifth multiplexer according to the control signal;a sixth multiplexer, comprising a first input end for receiving the fourth gray level voltage, a second input end for receiving the third gray level voltage, a control end for receiving the control signal and an output end, wherein the sixth multiplexer is for coupling the first input end or the second input end of the sixth multiplexer to the output end of the sixth multiplexer according to the control signal;a seventh multiplexer, comprising a first input end for receiving the first gray level voltage, a second input end for receiving the second gray level voltage, a control end for receiving the control signal and an output end, wherein the seventh multiplexer is for coupling the first input end or the second input end of the seventh multiplexer to the output end of the seventh multiplexer according to the control signal;an eighth multiplexer, comprising a first input end for receiving the third gray level voltage, a second input end for receiving the fourth gray level voltage, a control end for receiving the control signal and an output end, wherein the eighth multiplexer is for coupling the first input end or the second input end of the eighth multiplexer to the output end of the eighth multiplexer according to the control signal;a first polarity selecting circuit, comprising a first input end coupled to the output end of the fifth multiplexer, a second input end coupled to the output end of the sixth multiplexer, a first output end, a second output end, and a control end for receiving the polarity signal, wherein the first polarity selecting circuit is for coupling one input end of the first input end and the second input end of the first polarity selecting circuit to the first output end of the first polarity selecting circuit, and coupling the other input end to the second output end of the first polarity selecting circuit according to the polarity signal; anda second polarity selecting circuit, comprising a first input end coupled to the output end of the seventh multiplexer, a second input end coupled to the output end of the eighth multiplexer, a first output end, a second output end, and a control end for receiving the polarity signal, wherein the second polarity selecting circuit is for coupling one input end of the first input end and the second input end of the second polarity selecting circuit to the first output end of the second polarity selecting circuit, and coupling the other input end to the second output end of the second polarity selecting circuit according to the polarity signal.

9. The pixel driving circuit of claim 8, wherein: when the control signal is the first predetermined logic, the first input end of the fifth multiplexer is coupled to the output end of the fifth multiplexer, the first input end of the sixth multiplexer is coupled to the output end of the sixth multiplexer, the first input end of the seventh multiplexer is coupled to the output end of the seventh multiplexer, and the first input end of the eighth multiplexer is coupled to the output end of the eighth multiplexer; andwhen the control signal is the second predetermined logic, the second input end of the fifth multiplexer is coupled to the output end of the fifth multiplexer, the second input end of the sixth multiplexer is coupled to the output end of the sixth multiplexer, the second input end of the seventh multiplexer is coupled to the output end of the seventh multiplexer, and the second input end of the eighth multiplexer is coupled to the output end of the eighth multiplexer.

10. The pixel driving circuit of claim 8, wherein: when the polarity signal is the first predetermined logic, the first input end of the first polarity selecting circuit is coupled to the second output end of the first polarity selecting circuit, the second input end of the first polarity selecting circuit is coupled to the first output end of the first polarity selecting circuit, the first input end of the second polarity selecting circuit is coupled to the second output end of the second polarity selecting circuit, and the second input end of the second polarity selecting circuit is coupled to the first output end of the second polarity selecting circuit; andwhen the polarity signal is the second predetermined logic, the first input end of the first polarity selecting circuit is coupled to the first output end of the first polarity selecting circuit, the second input end of the first polarity selecting circuit is coupled to the second output end of the first polarity selecting circuit, the first input end of the second polarity selecting circuit is coupled to the first output end of the second polarity selecting circuit, and the second input end of the second polarity selecting circuit is coupled to the second output end of the second polarity selecting circuit.

11. The pixel driving circuit of claim 8, wherein the second selecting circuit further comprises: a first buffer, coupled between the output end of the fifth multiplexer and the first input end of the first polarity selecting circuit, wherein the first buffer is for buffering a gray level voltage outputted by the output end of the fifth multiplexer;a second buffer, coupled between the output end of the sixth multiplexer and the second input end of the first polarity selecting circuit, wherein the second buffer is for buffering a gray level voltage outputted by the output end of the sixth multiplexer;a third buffer, coupled between the output end of the seventh multiplexer and the first input end of the second polarity selecting circuit, wherein the third buffer is for buffering a gray level voltage outputted by the output end of the seventh multiplexer; anda fourth buffer, coupled between the output end of the eighth multiplexer and the second input end of the second polarity selecting circuit, wherein the fourth buffer is for buffering a gray level voltage outputted by the output end of the eighth multiplexer.

12. The pixel driving circuit of claim 8, wherein the first output end of the first polarity selecting circuit is coupled to the first data line, the second output end of the first polarity selecting circuit is coupled to the second data line, the first output end of the second polarity selecting circuit is coupled to the third data line, and the second output end of the second polarity selecting circuit is coupled to the fourth data line.

13. The pixel driving circuit of claim 12, wherein: when the gamma voltage selecting signal is the first predetermined logic and the polarity signal is the second predetermined logic, the second selecting circuit provides the first gray level voltage to the first main region via the first data line, provides the third gray level voltage to the first sub region via the second data line, provides the second gray level voltage to the second sub region via the third data line, and provides the fourth gray level voltage to the second main region via the fourth data line; andwhen both the gamma voltage selecting signal and the polarity signal are the first predetermined logic, the second selecting circuit provides the fourth gray level voltage to the first main region via the first data line, provides the second gray level voltage to the first sub region via the second data line, provides the third gray level voltage to the second sub region via the third data line, and provides the first gray level voltage to the second main region via the fourth data line.

14. The pixel driving circuit of claim 8, wherein the first output end of the first polarity selecting circuit is coupled to the second data line, the second output end of the first polarity selecting circuit is coupled to the first data line, the first output end of the second polarity selecting circuit is coupled to fourth data line, and the second output end of the second polarity selecting circuit is coupled to the third data line.

15. The pixel driving circuit of claim 14, wherein: when both the gamma voltage selecting signal and the polarity signal are the second predetermined logic, the second selecting circuit provides the fourth gray level voltage to the first main region via the first data line, provides the second gray level voltage to the first sub region via the second data line, provides the third gray level voltage to the second sub region via the third data line, and provides the first gray level voltage to the second main region via the fourth data line; andwhen the gamma voltage selecting signal is the second predetermined logic and the polarity signal is the first predetermined logic, the second selecting circuit provides the first gray level voltage to the first main region via the first data line, provides the third gray level voltage to the first sub region via the second data line, provides the second gray level voltage to the second sub region via the third data line, and provides the fourth gray level voltage to the second main region via the fourth data line.

16. A pixel driving circuit, comprising: a first pixel, comprising a first main region and a first sub region, wherein the first main region is coupled to a first data line and a scan line, the first sub region is coupled to a second data line and the scan line, and each of the first main region and the first sub region stores a gray level voltage corresponding to first digital data;a second pixel, comprising a second main region and a second sub region, wherein the second sub region is coupled to a third data line and the scan line, the second main region is coupled to a fourth data line and the scan line, and each of the second main region and the second sub region stores a gray level voltage corresponding to second digital data; anda data driving circuit, comprising: a first digital-to-analog converter, for converting the first digital data or the second digital data to a first gray level voltage according to a positive main region gamma voltage;a second digital-to-analog converter, for converting the first digital data or the second digital data to a second gray level voltage according to a positive sub region gamma voltage;a third digital-to-analog converter, for converting the first digital data or the second digital data to a third gray level voltage according to a negative sub region gamma voltage;a fourth digital-to-analog converter, for converting the first digital data or the second digital data to a fourth gray level voltage according to a negative main region gamma voltage;a first selecting circuit, for selecting the first digital data according to a gamma voltage selecting signal and a polarity signal, for inputting the first digital data into two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters, and inputting the second digital data into the other two digital-to-analog converters of the first, the second, the third and the fourth digital-to-analog converters; anda second selecting circuit, for distributing the first, the second, the third and the fourth gray level voltages to the first main region, the second main region, the first sub region and the second sub region via the first, the second, the third and the fourth data lines, according to the gamma voltage selecting signal and the polarity signal;wherein when both of the gamma voltage selecting signal and the polarity signal are a first predetermined logic or a second predetermined logic, the first selecting circuit outputs the second digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the first digital data to the second and the fourth digital-to-analog converters;wherein when the gamma voltage selecting signal is the first predetermined logic and the polarity signal is the second predetermined logic, the first selecting circuit outputs the first digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the second digital data to the second and the fourth digital-to-analog converters; andwherein when the gamma voltage selecting signal is the second predetermined logic and the polarity signal is the first predetermined logic, the first selecting circuit outputs the first digital data to the first and the third digital-to-analog converters, and the first selecting circuit outputs the second digital data to the second and the fourth digital-to-analog converters.

17. The pixel driving circuit of claim 16, wherein the data driving circuit further comprises: a first level shifter, coupled between the first selecting circuit and the first digital-to-analog converter;a second level shifter, coupled between the first selecting circuit and the second digital-to-analog converter;a third level shifter, coupled between the first selecting circuit and the third digital-to-analog converter; anda fourth level shifter, coupled between the first selecting circuit and the fourth digital-to-analog converter.

18. The pixel driving circuit of claim 16, wherein the data driving circuit further comprises: a first data latch, coupled between the first selecting circuit and the first level shifter;a second data latch, coupled between the first selecting circuit and the second level shifter;a third data latch, coupled between the first selecting circuit and the third level shifter; anda fourth data latch, coupled between the first selecting circuit and the fourth level shifter.

19. The pixel driving circuit of claim 16, wherein the first selecting circuit comprises: an XOR gate, for generating a control signal according to the gamma voltage selecting signal and the polarity signal;a first multiplexer, comprising a first input end for receiving the second digital data, a second input end for receiving the first digital data, a control end for receiving the control signal and an output end, wherein the first multiplexer is for coupling the first input end or the second input end of the first multiplexer to the output end of the first multiplexer according to the control signal;a second multiplexer, comprising a first input end for receiving the first digital data, a second input end for receiving the second digital data, a control end for receiving the control signal and an output end, wherein the second multiplexer is for coupling the first input end or the second input end of the second multiplexer to the output end of the second multiplexer according to the control signal;a third multiplexer, comprising a first input end for receiving the second digital data, a second input end for receiving the first digital data, a control end for receiving the control signal and an output end, wherein the third multiplexer is for coupling the first input end or the second input end of the third multiplexer to the output end of the third multiplexer according to the control signal; anda fourth multiplexer, comprising a first input end for receiving the first digital data, a second input end for receiving the second digital data, a control end for receiving the control signal and an output end, wherein the fourth multiplexer is for coupling the first input end or the second input end of the fourth multiplexer to the output end of the fourth multiplexer according to the control signal.

20. The pixel driving circuit of claim 19, wherein: when both of the gamma voltage selecting signal and the polarity signal are the first predetermined logic or the second predetermined logic, the control signal is the first predetermined logic;when the gamma voltage selecting signal is the first predetermined logic and the polarity signal is the second predetermined logic, the control signal is the second predetermined logic; andwhen the gamma voltage selecting signal is the second predetermined logic and the polarity signal is the first predetermined logic, the control signal is the second predetermined logic.