The present application is a US national phase of International patent application No. PCT/CN2021/078857 filed on Mar. 3, 2021, which claims priority to Chinese Patent Application No. 2020102117439 filed on Mar. 24, 2020 to CNIPA, the contents of which are incorporated here in its entirety by reference.
One or more embodiments of the present disclosure relates to pixel driving circuits and display devices.
Due to advantages such as high brightness, long service life, small volume, etc., micro inorganic light emitting diodes are usually applied to display devices and thus have broad development prospect in the display field. However, such micro inorganic light emitting diodes in the display devices may flicker due to a short total light emission time length and non-uniform light emission time within time of one frame in some scenarios, for example, the micro inorganic light emitting diodes perform display at low-gray-level (i.e. low brightness).
At least one embodiment of the present disclosure provides a pixel driving circuit configured to provide a signal for a to-be-driven element. The pixel driving circuit includes: a current control sub-circuit, configured to transmit a current signal; a time length control sub-circuit, configured to transmit a time signal; and an output sub-circuit, electrically connected with the time length control sub-circuit and the current control sub-circuit respectively. The time length control sub-circuit is further configured to control the output sub-circuit to be turned on or off based on the time signal. The output sub-circuit is configured to, when turned on, control a current applied to the to-be-driven element based on the current signal, where duration of two adjacent turn-ons of the output sub-circuit is same and duration of two adjacent turn-offs of the output sub-circuit is same.
In some embodiments of the present disclosure, the time length control sub-circuit includes a comparator, and the comparator is configured to compare the time signal and a reference voltage signal to generate a comparison signal and control the output sub-circuit to be turned on or off based on the comparison signal, where the comparison signal is a periodic square wave signal.
In some embodiments of the present disclosure, the comparator includes a non-inverting input terminal, an inverting input terminal and an output terminal; the non-inverting input terminal is configured to receive one of the time signal and the reference voltage signal; the inverting input terminal is configured to receive other of the time signal and the reference voltage signal; the output terminal is connected with the output sub-circuit.
In some embodiments of the present disclosure, the reference voltage signal includes one of a ramp signal, a triangle wave signal, a sawtooth wave signal, a sine wave signal and a cosine wave signal.
In some embodiments of the present disclosure, the reference voltage signal is a high frequency signal, and a frequency of the reference voltage signal is equal to or greater than 750 Hz and equal to or smaller than 7500 Hz.
In some embodiments of the present disclosure, the time length control sub-circuit further includes a time length write sub-circuit and a time length storage capacitor; the time length write sub-circuit is connected with the non-inverting input terminal or the inverting input terminal of the comparator; a first terminal of the time length storage capacitor is grounded and a second terminal of the time length storage capacitor is connected with the time length write sub-circuit and connected with the comparator.
In some embodiments of the present disclosure, the current control sub-circuit includes a current write sub-circuit and a compensation sub-circuit. The compensation sub-circuit is connected with the current write sub-circuit and the output sub-circuit. A first terminal of the current write sub-circuit is configured to receive the current signal and a second terminal of the current write sub-circuit is connected with the compensation sub-circuit. A first terminal of the compensation sub-circuit is connected with the current write sub-circuit and a second terminal of the compensation sub-circuit is connected with the output sub-circuit.
In some embodiments of the present disclosure, the compensation sub-circuit includes a compensation transistor, a current storage capacitor and a first drive transistor. A first electrode of the first drive transistor is connected with the current write sub-circuit, a second electrode of the first drive transistor is connected with a first electrode of the compensation transistor, a gate electrode of the first drive transistor and a second electrode of the compensation transistor are both connected with the current storage capacitor, and a gate electrode of the compensation transistor is connected with a data write control signal line.
In some embodiments of the present disclosure, a width-length ratio of the first drive transistor is greater than 3.
In some embodiments of the present disclosure, the current write sub-circuit includes a current write transistor.
In some embodiments of the present disclosure, the pixel driving circuit further includes a work control sub-circuit. The work control sub-circuit includes a first control transistor; a first electrode of the first control transistor is connected with the current control sub-circuit; a second electrode of the first control transistor is connected with the output sub-circuit; a gate electrode of the first control transistor is connected with a work control signal line. The work control signal line is configured to input a work control signal to the first control transistor so as to control the first control transistor to be turned on or off; where the first control transistor is configured to, when turned on, transmit the current signal to the output sub-circuit.
In some embodiments of the present disclosure, the work control sub-circuit further includes a second control transistor. A first electrode of the second control transistor is connected with a power supply terminal, and a second electrode of the second control transistor is connected with the current control sub-circuit.
In some embodiments of the present disclosure, the work control sub-circuit further includes a third control transistor. A first electrode of the third control transistor is connected with the output sub-circuit, and a second electrode of the third control transistor is connected with the to-be-driven element.
In some embodiments of the present disclosure, the output sub-circuit includes an output transistor. A first electrode of the output transistor is connected with the second electrode of the first control transistor, and a second electrode of the output transistor is connected with the first electrode of the third control transistor.
In some embodiments of the present disclosure, the pixel driving circuit further includes a reset sub-circuit. The reset sub-circuit includes a reset transistor, a gate electrode of the reset transistor is connected with a reset control line, a first electrode of the reset transistor is connected with a reset signal terminal, and a second electrode of the reset transistor is connected with at least one of the current control sub-circuit, the time length control sub-circuit and the to-be-driven element and configured to reset the current control sub-circuit, the time length control sub-circuit and the to-be-driven element.
At least one embodiment of the present disclosure provides a display device. The display device includes a to-be-driven element and the above pixel driving circuit. The pixel driving circuit is configured to provide signals for the to-be-driven element and the to-be-driven element is a current driven light emitting diode.
It should be understood that the above general descriptions and subsequent detailed descriptions are merely illustrative and explanatory rather than limiting of the present disclosure.
Numerals of drawings are described below:
Exemplary embodiments will be described in detail herein, with the illustrations thereof represented in the drawings. When the following descriptions involve the drawings, like numerals in different drawings refer to like or similar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
The terms used in the present disclosure are for the purpose of describing particular embodiments only, and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the present disclosure should have general meanings that can be understood by ordinary persons of skill in the art. “One” or “a” and the like do not represent quantity limitation but represent at least one. “Multiple” represents two or more. Unless otherwise stated, “include” or “contain” or the like is intended to refer to that an element or object appearing before “include” or “contain” covers an element or object or its equivalents listed after “include” or “contain” and does not preclude other elements or objects. “Connect” or “connect with” or the like is not limited to physical or mechanical connection but includes direct or indirect electrical connection. The singular forms such as “a”, ‘said”, and “the” used in the present disclosure and the appended claims are also intended to include multiple, unless the context clearly indicates otherwise. It is also to be understood that the term “and/or” as used herein refers to any or all possible combinations that include one or more associated listed items.
At least one embodiment of the present disclosure provides a display device which is applied to an electronic apparatus having display function such as mobile phone, computer, tablet computer, electronic paper or wrist watch.
As shown in
It is noted that the number of the pixels 1 in the display device 2 is very huge but
At the same time, in each time period, it is required to write data one time in the pixel driving circuit 10. In this case, it is required to write data several times in the pixel driving circuit 10 in time of one frame, occupying a large amount of time. If time of one frame contains n time periods, it is required to write data n times in the pixel driving circuit 10 in time of one frame.
At least one embodiment of the present disclosure provides a pixel driving circuit configured to provide a signal to to-be-driven elements. The pixel driving circuit includes a current control sub-circuit, configured to transmit a current signal; a time length control sub-circuit, configured to transmit a time signal; and an output sub-circuit, electrically connected with the time length control sub-circuit and the current control sub-circuit respectively. The time length control sub-circuit is further configured to control the output sub-circuit to be turned on or off based on the time signal; the output sub-circuit is configured to, when turned on, control a current applied to the to-be-driven element based on the current signal, where duration of two adjacent turn-ons of the output sub-circuit is same and duration of two adjacent turn-offs of the output sub-circuit is same.
As shown in
The time length control sub-circuit 200 is further configured to control the output sub-circuit 300 to be turned on or off based on the time signal Vdata_T. The output sub-circuit 300 is configured to, when turned on, control a current flowing through the to-be-driven elements 20 based on the current signal Vdata_I. Duration of two adjacent turn-ons of the output sub-circuit 300 is same and duration of two adjacent turn-offs of the output sub-circuit 300 is same.
As shown in
Further, when the to-be-driven element 20 needs to be driven to emit light, in time of one frame, a number of turn-ons of the output sub-circuit 300 should be equal to or greater than 10. The number of turn-ons in time of one frame may be 12, 14, 15, 18, 20 and the like. As shown in
As shown in
In this embodiment, the non-inverting input terminal 211 is connected with a time length signal line 11 and configured to receive the time signal Vdata_T; the inverting input terminal 212 is connected with a reference signal line 12 and configured to receive the reference voltage signal Vramp_T. In this circuit structure, when the time signal Vdata_T is greater than the reference voltage signal Vramp_T, the comparator 210 outputs a comparison signal of low level, that is, the output terminal 213 transmits a comparison signal of low level to the output sub-circuit 300, and the output sub-circuit 300 is turned on. When the time signal Vdata_T is smaller than the reference voltage signal Vramp_T, the comparator 210 outputs a comparison signal of high level, that is, the output terminal 213 transmits a comparison signal of high level to the output sub-circuit 300, and the output sub-circuit 300 is turned off. Of course, in some embodiments of the present disclosure, the non-inverting input terminal 211 may be connected with the reference signal line 12 and configured to receive the reference voltage signal Vramp_T; the inverting input terminal 212 is connected with the time length signal line 11 and configured to receive the time signal Vdata_T. In this case, when the time signal Vdata_T is greater than the reference voltage signal Vramp_T, the comparator 210 outputs a comparison signal of high level; when the time signal Vdata_T is smaller than the reference voltage signal Vramp_T, the comparator 210 outputs a comparison signal of low level.
It is noted that the comparison signal is a periodic square wave signal. Only when the comparison signal is the periodic square wave signal, it can be ensured that the time lengths of two adjacent turn-ons of the output sub-circuit 300 are same and the time lengths of two adjacent turn-offs are same. In this way, it is ensured that the time lengths of two adjacent light emission of the to-be-driven element 20 in time of one frame are same and the time lengths of two adjacent non-lightings are same as well. Thus, the flicker phenomenon visible to naked eyes generated by the to-be-driven element 20 in time of one frame during displaying can be mitigated or avoided.
In combination with
In one embodiment of the present disclosure, the time signal Vdata_T obtained by the comparator 210 is a fixed voltage value in time of one frame, and the reference voltage signal Vramp_T is a ramp signal. By the above disposal, it can be ensured that the comparison signal output by the comparator 210 is a periodic square wave signal. In an actual use, by adjusting a magnitude of the time signal Vdata_T, the comparison signals (i.e. periodic square wave signals) of different duty cycles can be obtained (refer to
Of course, in some embodiments of the present disclosure, the reference voltage signal Vramp_T may also be a triangle wave signal, a sawtooth wave signal, a sine wave signal or a cosine wave signal or the like.
In combination with
Furthermore, the reference voltage signal Vramp_T is a high frequency signal. In an embodiment of the present disclosure, the reference voltage signal Vramp_T is a high frequency ramp signal. A frequency of the reference voltage signal Vramp_T is equal to or greater than 750 Hz and equal to or smaller than 7500 Hz. In the above disposal, by limiting the frequency of the reference voltage signal Vramp_T, the reference voltage signal Vramp_T is maintained to change at high frequency. In an embodiment of the present disclosure, the frequency of the reference voltage signal Vramp_T is 800 Hz. Of course, in some embodiments of the present disclosure, the frequency of the reference voltage signal Vramp_T may also be 900 Hz, 1000 Hz, 1500 Hz, 2000 Hz, 3000 Hz, 4000 Hz, 4500 Hz, 5000 Hz, 6000 Hz, 7000 Hz, or any frequency within the range equal to or greater than 750 Hz and equal to or smaller than 7500 Hz. No matter when the reference voltage signal Vramp_T is input, the duty cycle of the comparison signal obtained by comparing the reference voltage signal Vramp_T and the time signal Vdata_T through the comparator 210 is relatively stable. In other words, in time of one frame, the light emission time length of the to-be-driven element 20 will not change due to different times in which the reference voltage signal Vramp_T is input, thus ensuring the brightness of the to-be-driven element 20 is identical to a preset brightness. In this case, when the display device performs displaying, after data is written and registered in a row of pixels, the registered time signal Vdata_T and the reference voltage signal Vramp_T can be directly compared so that the row of pixels can directly emit light without awaiting the last row of pixels to be data-written. With the above disposal, lagged displaying may be avoided or mitigated, which is helpful to achieve high resolution display of the display device.
In an embodiment of the present disclosure, as shown in
In an embodiment of the present disclosure, the time length control sub-circuit 200 further includes a reference voltage write transistor T9. The reference signal line 12 is connected with the comparator 210 through the reference voltage write transistor T9. A first electrode of the reference voltage write transistor T9 is connected with the reference signal line 12, a second electrode of the reference voltage write transistor T9 is connected with the inverting input terminal 212 of the comparator 210, and a gate electrode of the reference voltage write transistor T9 is connected with the work control signal line 15. The work control signal line 15 writes the work control signal EM into the reference voltage write transistor T9. When the work control signal EM is of low level, the reference voltage write transistor T9 is turned on to input the reference voltage signal Vramp_T to the inverting input terminal 212 of the comparator 210. When the work control signal EM is of high level, the reference voltage write transistor T9 is turned off.
With continued reference to
The current write transistor T2, the time length write transistor T10 and the compensation transistor T3 are all controlled to be turned on or off by the data write control signal line 13. When the data write control signal Gate output by the data write control signal line 13 is of low level, the current write transistor T2, the time length write transistor T10 and the compensation transistor T3 are all turned on. When the data write control signal Gate output by the data write control signal line 13 is of high level, the current write transistor T2, the time length write transistor T10 and the compensation transistor T3 are all turned off.
When the current write transistor T2 is turned on, the current signal Vdata_I is written into the first electrode of the first drive transistor T4 through the current write transistor T2. Due to the characteristics of the first drive transistor T4, when a potential of the gate electrode of the first drive transistor T4 is lower than a potential of its first electrode, the first drive transistor T4 is turned on and the current signal Vdata_I charges the current storage capacitor C1 through the first drive transistor T4 and the compensation transistor T3. In this way, the current storage capacitor C1 stores the current signal Vdata_I. The voltage on the first electrode of the first drive transistor T4 is maintained as Vdata_I and the voltage on the gate electrode of the first drive transistor T4 is increasing. When the voltage on the gate electrode of the first drive transistor T4 is Vdata+Vth, the first drive transistor T4 is turned off, where Vdata represents a voltage of the current signal Vdata_I and Vth represents a threshold voltage of the first drive transistor T4.
As shown in
With continued reference to
It is noted that μ is an electron mobility, Cox is a capacitance of gate oxide layer, VGS is a voltage of the gate electrode relative to a source electrode, and
is a width-length ratio of the first drive transistor T4.
The working current generated and applied to the to-be-driven element 20 by the first drive transistor T4 can directly determine a luminous intensity of the to-be-driven element 20. According to the formula, the magnitude of the working current is irrelevant to the threshold voltage Vth of the first drive transistor T4 but relevant to the current signal Vdata_I and the characteristics (μ, Cox and VGS) of the first drive transistor T4. Due to the characteristics of the to-be-driven element 20, such as a micro LED and a mini LED, its light emission efficiency, brightness of emitted rays and color coordinate may change along with change of a current density under a low current density, further leading to displaying quality problem. Because a current of large current density can drive the to-be-driven element 20 to emit stable light, to ensure the light emission efficiency, the current of large current density may be used to drive the to-be-driven element 20 to emit light so as to display an image. The current generated by the first drive transistor T4 should enable the to-be-driven element 20 to work in a high current density region to avoid the problems of drift of a main wave peak along with the change of the current density, poor brightness uniformity under the low current density and the like. It is known from experiments that when the width-length ratio of the first drive transistor T4 is greater than 3, the brightness displayed by the to-be-driven element 20 has good uniformity. In an embodiment of the present disclosure, the width-length ratio of the first drive transistor T4 is 4. Of course, in some embodiments of the present disclosure, the width-length ratio of the first drive transistor T4 may alternatively be any value greater than 3, for example, 5, 6, 7, 8, 9.1 or the like.
Further, as shown in
A first electrode of the first control transistor T6 is connected with the current control sub-circuit 100; a second electrode of the first control transistor T6 is connected with the output sub-circuit 300. The first control transistor T6 is configured to, when turned on, transmit the current signal Vdata_I to the output sub-circuit 300. By disposing the first control transistor T6, relative independence of the current control sub-circuit 100 and the time length control sub-circuit 200 is guaranteed, thus avoiding mutual influence of both.
A first electrode of the second control transistor T5 is connected with the power supply terminal VDD1, and a second electrode of the second control transistor T5 is connected with the current write transistor T2 in the current write sub-circuit 110. When the work control signal EM is of low level, the second control transistor T5 is turned on, and the power supply terminal VDD1 is in communication with the second electrode of the current write transistor T2. By disposing the second control transistor T5, a voltage can be provided to the current control sub-circuit 100.
A first electrode of the third control transistor T8 is connected with the output sub-circuit 300 and a second electrode of the third control transistor T8 is connected with the to-be-driven element 20. When the work control signal EM is of low level, the third control transistor T8 is turned on and the third control transistor T8 is configured to supply power to the to-be-driven element 20, namely, the current signal Vdata_I and the time signal Vdata_T are transmitted to the to-be-driven element 20. In this way, the current and the light emission time length of the to-be-driven element 20 in time of one frame are determined and thus the luminous intensity and the light emission time of the to-be-driven element 20 are determined, namely, the displaying brightness of the to-be-driven element in the time of the frame is determined.
In an embodiment of the present disclosure, the output sub-circuit 300 includes an output transistor T7. A first electrode of the output transistor T7 is connected with the current control sub-circuit 100 through the first control transistor T6, and a second electrode of the output transistor T7 is connected with the to-be-driven element 20 through the third control transistor T8. A gate electrode of the output transistor T7 is connected with the output terminal 213 of the comparator 210 in the time length control sub-circuit 200.
Further, with continued reference to
As shown in
It is noted that the reset voltage Vint may be a voltage of low potential, for example, grounded. In
As shown in
It is noted that, in
As shown in
It is noted that, in
Since the method embodiments basically correspond to the apparatus embodiments, reference may be made to the descriptions of the apparatus embodiments for relevant parts. The method embodiments and the apparatus embodiments are mutually supplemented.
The foregoing disclosure is merely illustrative of preferred embodiments of the present disclosure but not intended to limit the present disclosure, and any modifications, equivalent substitutions and improvements thereof made within the spirit and principles of the present disclosure shall be encompassed in the scope of protection of one or more embodiments in the present disclosure.
Number | Date | Country | Kind |
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202010211743.9 | Mar 2020 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2021/078857 | 3/3/2021 | WO |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2021/190263 | 9/20/2021 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
5506529 | Baldwin | Apr 1996 | A |
10796665 | Hsieh et al. | Oct 2020 | B1 |
20020140659 | Mikami | Oct 2002 | A1 |
20160118971 | Sugiyama | Apr 2016 | A1 |
20170069264 | Dai | Mar 2017 | A1 |
20190156751 | Zhang | May 2019 | A1 |
20200380910 | He | Dec 2020 | A1 |
20210027699 | Zheng et al. | Jan 2021 | A1 |
20210366354 | Li | Nov 2021 | A1 |
20210366364 | Xuan | Nov 2021 | A1 |
20220005403 | Yue | Jan 2022 | A1 |
20220076616 | Liu et al. | Mar 2022 | A1 |
20220139315 | Lin et al. | May 2022 | A1 |
Number | Date | Country |
---|---|---|
WO 2020220613 | Nov 2015 | CN |
108538241 | Sep 2018 | CN |
109410832 | Mar 2019 | CN |
110021263 | Jul 2019 | CN |
110310594 | Oct 2019 | CN |
110782831 | Feb 2020 | CN |
WO 2020098034 | May 2020 | CN |
111243499 | Jun 2020 | CN |
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---|
CN2020102117439 first office action. |
CN2020102117439 second office action. |
PCT/CN2021/078857 international search report. |
PCT/CN2021/078857 Written Opinion. |
Number | Date | Country | |
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20230043626 A1 | Feb 2023 | US |