Patent Application
20100245343
This application claims the benefit of Japanese Patent Application No. 2009-087471 filed Mar. 31, 2009, the entire disclosure of which is incorporated herein by reference.
This invention relates to a pixel driving device, a light emitting device and a light emitting device driving control method.
An Organic Electro-Luminescence Element (an Organic EL Element) is formed by an organic compound of fluorescence to be emitted through the addition of the electric field. A display device including a display panel having Organic Light emitting Diode (hereinafter referred to as an OLED) elements in each pixel is attracting attention as a next-generation display device.
This OLED is a current driving element and emits luminance in proportion to the flow of the current. The display device equipped with such OLED has drive transistors that are configured by the field-effect transistors (thin-film transistors) in each pixel, and controls current values of the current supplied to the OLED according to the voltage applied to the gates.
A capacitor is connected between the gate and the source in the drive transistor in each pixel, while the voltage corresponding to a video signal supplied from an external source is written into this capacitor in order to retain the voltage.
After the voltage is applied between the drain and the source, the drive transistor supplies the current to the OLED while controlling the current value at this gate voltage Vgs as the voltage Vgs (hereinafter referred to as a “gate voltage”) between the gate and the source.
The current value of the current to be supplied from the drive transistor to the OLED is determined according to the gate voltage Vgs value and the characteristics values of the applicable drive transistor (the threshold voltage Vth and the current gain β). The threshold voltage Vth is known to vary according to the past drive records in the pixel. When the variation in threshold voltage Vth occurs, the luminance of the OLED varies even if the gate voltage Vgs is the same, and consequently the quality of display image may be degraded.
Therefore, for the display device having light emitting elements such as the OLED in a pixel, the threshold voltage value Vth in each pixel is acquired, and the voltage value at the voltage to be applied between the gate and the source in the drive transistor is corrected according to the video signals based on the acquired threshold voltage value Vth. Therefore the development of the display device is pursued in order to improve quality display images.
However, as for an example of the current gain β, variations among the pixels may occur due to manufacturing processes. If the current gain β varies among the pixels, and even if the voltage value at the voltage to be applied between the gate and the source in the drive transistor is corrected after the threshold voltage Vth in each pixel is acquired, the degradation in display image quality caused by the variation of the current gain β among the pixels is not resolved.
This invention advantageously provides a pixel driving device, a light emitting device and a light emitting device driving control method capable of controlling the degradation of the display image quality caused by the variations of the threshold voltage value in each pixel and the variation of the current gain in each pixel.
In order to obtain the advantage, the pixel driving device for driving pixels of the present application is a pixel driving device for driving pixels in accordance with image data, wherein the pixel includes a light emitting element, a driving element and a capacitor, wherein the driving element has a control terminal and one end of a current path connected to one terminal of the light emitting element and electrically connected to a signal line, and the capacitor is connected between the control terminal of the driving element and the one end of the current path of the driving element, the pixel driving device comprising: a first measuring circuit which acquires a threshold voltage of the driving element, on the basis of a voltage value at the terminal of the signal line, a voltage value being acquired after an initial voltage having a voltage value that exceeds the threshold voltage of the driving element is applied to the terminal of the signal line and a predetermined relaxation time is elapsed after the initial voltage to the signal line is cut off; a second measuring circuit which acquires a voltage-current characteristics of the driving element and acquires a current gain value of the driving element by the acquired voltage-current characteristics of the driving element and the threshold voltage of the driving element acquired by the first measurement circuit; and a correction processing circuit which corrects the image data to be supplied from an external source on the basis of the threshold voltage and the current gain of the driving element acquired by the first measuring circuit and the second measuring circuit.
In order to obtain the advantage, the light emitting device for emitting light in accordance with image data of the present application is a light emitting device for emitting light in accordance with image data, comprising: a pixel array including a plurality of pixels and a plurality of signal lines, wherein each pixel includes a light-emitting element, a driving element and a capacitor, wherein the driving element has one end of a current path connected to one terminal of the light-emitting element, and electrically connected to each signal line, and the capacitor is connected between a control terminal of the driving element and the one end of the current path of the driving element; a first measuring circuit which acquires a threshold voltage of the driving element of each pixel, on the basis of a voltage value at the terminal of each signal line, wherein the voltage value is acquired after an initial voltage having a voltage that exceeds the threshold voltage of the driving element is applied to the terminal of each signal line and a predetermined relaxation time is elapsed after the initial voltage to each signal line is cut off; a second measuring circuit which acquires a voltage-current characteristics of the driving element of each pixel and acquires a current gain value of the driving element of each pixel by the acquired voltage-current characteristics of the driving element of each pixel and the threshold voltage of the driving element acquired by the first measurement circuit; and a correction processing circuit which corrects the image data to be supplied from an external source on the basis of the threshold voltage and the current gain of the driving element of each pixel acquired from the first measuring circuit and the second measuring circuit.
In order to obtain the advantage, the light emitting device driving control method for emitting light device control method of the present application is a light emitting device driving control method for emitting light in accordance with image data, wherein the light emitting device includes a pixel array having a plurality of pixels and a plurality of signal lines, wherein each pixel includes a light-emitting element, a driving element and a capacitor, wherein the driving element has one end of a current path connected to one terminal of the light-emitting element, and electrically connected to each signal line, and the capacitor is connected between a control terminal of the driving element and the one end of the current path of the driving element, the light emitting device driving control method comprising: an initial voltage applying step that applies an initial voltage having a voltage that exceeds the threshold voltage of the driving element to a terminal of each signal line; a threshold voltage acquiring step that acquires a voltage value at the terminal of each signal line when a predetermined relaxation time is elapsed after the initial voltage to each signal line is cut off as the threshold voltage of the driving element of each pixel; a voltage-current characteristics acquiring step that acquires a voltage-current characteristics of the driving element of each pixel; a current gain acquiring step that acquires a current gain value of the driving element of each pixel on the basis of the voltage-current characteristics acquired in the voltage-current characteristics acquiring step and the threshold voltage of the driving element acquired in the threshold voltage acquiring step; and a correction step that corrects the image data to be supplied from an external source on the basis of the acquired threshold voltage and the acquired current gain of the driving element of each pixel.
A more complete understanding of this application can be acquired when the following detailed description is considered in conjunction with the following drawings, in which:
The following describes a light emitting device according to an embodiment of this invention with reference to the drawings. Note that the following describes the light emitting device as a display device in this embodiment.
The OEL panel 11 includes multiple pixel circuits 11(i, j) (i=1 to m, j=1 to n, m and n; natural numbers).
Each pixel circuit 11(i, j) is a display pixel that corresponds to one pixel of an image, and is placed in a matrix form. Each pixel circuit 11(i, j) includes a pixel circuit that has a circuit structure shown in
The OLED 111 is a current control-type light emitting element (a display element) used to emit light by means of the exciter generated through the recombination of an electron and an electron hole, which are injected into the organic compound, and emits light with luminance corresponding to the value of the current thus supplied.
The OLED 111 has a pixel electrode and a pole electrode. The current flows from the pixel electrode in the direction into the pole electrode. The pixel electrode and the pole electrode become the anode electrode and the cathode electrode, respectively, and the cathode voltage Vcath is applied in this cathode electrode. The cathode voltage Vcath is set to 0 V in this embodiment.
The transistors T1, T2 and T3 in the pixel driving circuit DC are TFTs (Thin-Film Transistors) configured by n channel-type FETs (Field Effect Transistors), and are formed by, for instance, amorphous silicon or a polysilicon TFT.
The transistor T3 is a drive transistor (a driving element) used to control the current value of the current that is supplied to the OLED 111. The source on the first terminal on a current path (between the drain and the source) in the transistor T3 is connected to the anode in the OLED 111, and the drain on the second terminal on the current path in the transistor T3 is connected to the voltage line Lv(j).
The transistor T3 supplies the current of the current value corresponding to the gate voltage Vgs as the control voltage.
The transistor T1 is a switch transistor used to connect or disconnect between the gate (a control terminal) and the drain of the transistor T3.
The drain (a terminal) on the first terminal on a current path (between the drain and the source) in the transistor T1 in each pixel circuit (i, j) is connected to the voltage line Lv(j) (the drain in the transistor T3), while the source (a terminal) on the second terminal on the current path in the transistor T1 is connected to the gate as the control terminal in the transistor T3.
The gate (a terminal) in the transistor T1 of the pixel circuits 11(1, 1) through 11(m, 1) is connected to the select line Ls(1). Similarly, the gates in transistor T1 of the pixel circuits 11(1, 2) through 11(m, 2) and the gates in transistor T1 of the pixel circuits 11(1, n) through 11(m, n) are connected to the select line Ls(2) and the select line Ls(n), respectively.
In the case of the pixel circuit 11(1,1), when the high-level select signal Vselect(1) is output from the select driver 14 to the select line Ls(1), the transistor T1 is turned on, and then the gate and the drain are connected in the transistor T3 to set the diode connection state.
When the low-level select signal Vselect(1) is output to the select line Ls(1), the transistor T1 is turned off.
The transistor T2 is turned on/off by the select driver 14. The transistor T2 is a switch transistor used to connect or disconnect among the source in the transistor T3 and the anode in the OLED 111, and the data driver 16 via the data line Ld(i).
The drain on the second terminal on a current path (between the drain and the source) in the transistor T2 in each pixel circuit 11(i, j) is connected to the anode (an electrode) in the OLED 111.
The gates in the transistor T2 of the pixel circuits 11(1, 1) through 11(m, 1) are connected to the select line Ls(1). Similarly, the gates in the transistor T2 of the pixel circuits 11(2, 2) through 11(m, 2) are connected to the select line Ls(2), and the gates in the transistor T2 of the pixel circuits 11(1, n) through 11(m, n) are connected to the select line Ls(n).
Furthermore, the sources on the first terminal on the current path in the transistor T2 of the pixel circuits 11(1, 1) through 11(1, n) are connected to the data line Ld(1) as a signal line. Similarly, the sources in the transistor T2 of the pixel circuits 11(2, 1) through 11(2, n) are connected to the data line Ld(2), while the sources in the transistor T2 of the pixel circuits 11(m, 1) through 11(m, n) are connected to the data line Ld(m).
In the case of the pixel circuit 111,1), when the high-level select signal Vselect(1) is output from the select driver 14 to the select line Ls(1), the transistor T2 is turned on to connect the anode in the OLED 111 and the data line Ld(1).
When the low-level select signal Vselect(1) is output to the select line Ls(1), the transistor T2 is turned off to disconnect the anode in the OLED 111 and the data line Ld(1).
The capacitor C1 is connected between the gate in the transistor T3 and the source, and is a capacity component used to retain the gate voltage Vgs. One terminal in the capacitor C1 is connected to the source in the transistor T1 and the gate in the transistor T3, while the other terminal is connected to the source in the transistor T3 and the anode in the OLED 111.
When the drain current Id flows from the voltage line Lv(j) toward the drain in the transistor T2, the transistor T3 is turned on, and the capacitor C1 is charged with the gate voltage Vgs of the transistor T3 to which the charge is accumulated.
When the transistors T1 and T2 are turned off, the capacitor C1 retains the gate voltage Vgs of the transistor T3.
For example, a video signal Image, such as a composite video signal or a component video signal, is supplied from the external source in
The controller 13 supplies the control signals, and the like to each section, and controls the write processing and the light emitting operation for the OLED 111.
The write processing is used to write the voltage corresponding to a gradation value of the image data Pic to the capacitor C1 in each pixel circuit 11(i, j), whereas the light emitting operation is used to make the OLED 111 emit light.
The following describes the general display characteristics during the image display operation. If the visual characteristics of a person are considered, based on the characteristic that the luminance L of the display is in direct proportion to the input signal intensity Sig, the luminance L tends to darken as the input signal intensity Sig weakens.
Thus, it is desirable to set the display characteristic to the characteristic (y>1) shown in the following Formula 1:
L=SigY (1)
The characteristic shown in Formula 1 is collectively called the Gamma characteristic of display in which γ called the Gamma value, is set to 2, for example.
If the display device 1 using this OLED 111 has the Gamma characteristic (γ=2), the voltage value corresponding to the gradation value of the image data Pic will be represented as Vcode, and the input signal intensity Sig is shown in Formula 2. In this case, βm is a gain as a proportional coefficient.
Sig=√{square root over (βm)}×Vcode (2)
The luminance L of the display corresponds to the light emitting luminance of the OLED 111. Also, the light emitting luminance of the OLED 111 is proportional to the current value Iel of the current that flows into the OLED 111. Therefore, when the relationship between the input signal intensity Sig and the voltage Vcode corresponding to the gradation value of the image data Pic is represented in Formula 2, it is necessary to represent the relationship between the current value Iel of the current that flows into the OLED 111 and the voltage value Vcode in Formula 3 below:
Iel=βm×Vcode2 (3)
Meanwhile, the current that flows into the OLED 111 during the light emitting operation for each pixel 11(i, j) in this embodiment is nearly equivalent to the drain current Id that flows into the transistor T3 during the write operation. The drain current Id and the voltage Vdata to be applied to the data line Ld(i) have the relationship shown in Formula 4 below:.
Id=β×(Vdata−Vth 2) (4)
Accordingly, because the drain current Id in Formula 4 and the current Iel that flows into the OLED 111 shown in Formula 3 are equivalent, the relationship between the voltage Vdata to be applied to the data line Ld(i) and the voltage value Vcode that corresponds to the gradation value of the image data Pic is represented by Formula 5 below:
Therefore, if the voltage value Vcode that corresponds to the gradation value of the image data Pic to be supplied from the display signal generation circuit 12 is corrected according to Formula 5 above, the luminance that corresponds to the image data Pic may be acquired, and the display characteristic shown in Formula 1 may be acquired.
However, the transistor T3 is degraded over time due to the flow of drain current Id shown in
Note that the current-voltage characteristics VI—0 in the drawing denotes the current-voltage characteristics of the transistor T3 if the threshold voltage Vth is an initial value at the factory setting at the time of shipment and the β value is a standard value.
As shown in
Additionally, β (as shown in Formula 5) shows the variation in each pixel circuit 11(i, j) caused by factors inherent to the manufacturing process. For example, when β0 is set to the standard value of β (e.g., a design value or a typical value) and β=(β0+Δβ), the drain current-gate voltage (which is equivalent to the drain voltage) characteristics VI—0 of the transistor T3 are set to the drain current-gate voltage characteristics VI—2. Moreover, when β=(β0−Δβ), the current-voltage characteristics VI—0 of the transistor T3 are set to the current-voltage characteristics VI—3.
The variations of this threshold voltage Vth and the variations of β may affect the image quality (display characteristic) of the display device 1. Therefore, in order to improve the display image quality, the threshold voltage Vth and β is acquired, whereupon the image data Pic is corrected based on the acquired threshold voltage Vth and β.
In this embodiment, an auto-zero method is used to acquire the threshold voltage Vth for each pixel circuit 11(i, j). Then, the relation of the drain current Id and the drain voltage in the transistor T3 are acquired according to a current supply-voltage measurement method, and the β value is acquired based on the threshold voltage Vth acquired through the auto-zero method.
The following describes the auto-zero method:
As shown in
When the transistor T3 is set to the high-impedance state, the current is not flowed from the transistor T3 to the external source. However, the transistor T3 retains the “on” state due to the electrical charge accumulated in the capacitor C1, and the drain current Id continues to flow between the drain and the source in the transistor T3 based on the electrical charge accumulated in the capacitor C1. Consequently, when the transistor T3 is set to the high-impedance state, the electrical charge corresponding to the initial voltage Vprimary that is previously accumulated in the capacitor C1 is gradually discharged. As shown in
The auto-zero method is used to measure the drain voltage Vds (gate voltage Vgs) as the threshold voltage Vth at the point after the high-impedance state is set and relaxation time tm to be set to the time when the drain current Id is not flowing has elapsed, as shown in
In this case, if time t is defined as the elapsed time after the high-impedance state is set, a potential difference Vds(t) for the drain voltage Vds is represented by Formula 6 below:
Note that Cp in Formula 6 denotes the capacity value in the capacitor C1. In Formula 6, if t=∞, the drain voltage Vds(∞) becomes the threshold voltage Vth. Namely, the drain voltage Vds(t) becomes asymptotic with respect to the threshold voltage Vth over time. However, in theory, even if the over-time t is set to “infinite,” the drain voltage Vds(t) does not coincide with the threshold voltage Vth. Nevertheless, as shown in
The characteristics-acquiring switching circuit 17 is used to output the voltages Vd(1) through Vd(m) of data lines Ld(1) through Ld(m) for each line to the control 13. When the threshold voltage Vth is measured using the auto-zero method, the voltages Vd(1) through Vd(m) to be output from the characteristics-acquiring switching circuit 17 become the threshold voltages Vth in each transistor T3 for the jth-line pixel circuits 11(1, j) through 11(m, j).
The following describes the current supply-voltage measurement method.
Moreover, β is represented by the following Formula 7. If the threshold voltage Vth value is already known, the β value can be acquired from Formula 7 below:
Note that the β value does not normally change over time. Thus, for example, at the time of shipment from the factory prior to actual use or when the power of the display device 1 is initially turned on after shipment of the product, and once the β value is acquired, it is not necessary to acquire the β value again. However, the β value measurement may be performed again using an arbitrary timing upon the actual use as necessary.
On the other hand, since the threshold voltage Vth changes over time, it is necessary to measure the threshold voltage Vth at startup during the actual use of the display device 1 or each time the image is displayed, or at periodic intervals.
The controller 13 is used to correct the image data Pic using the threshold voltage Vth and the β value acquired from the above, and, as shown in
The A/D converter circuit 131 is used to convert the analog voltages Vd(1) through Vd(m) output from the characteristics-acquiring switching circuit 17 into digital voltages Vd(1) through Vd(m).
When the auto-zero method is used, the A/D converter circuit 131 acquires the voltages Vd(1) through Vd(m) output from the characteristics-acquiring switching circuit 17 as the threshold voltage Vth of each transistor T3 in the selected jth-line pixel circuits 11(i, j) through 11(m, j), and converts them into digital values.
When the current supply-voltage measurement method is used, the A/D converter circuit 131 acquires the voltages Vd(1) through Vd(m) output from the characteristics-acquiring switching circuit 17 as each voltage Vsink of the selected jth-line, and converts the voltages Vd(1) through Vd(m) into digital values.
The A/D converter circuit 131 supplies the threshold voltage Vth and the voltage Vsink, which have been converted into digital values, to the correction processing circuit 133. The correction processing circuit 133 stores the supplied threshold voltage Vth and the voltage Vsink into the correction data storage circuit 132. Note that the A/D converter circuit 131 in the controller 13 is arranged with the same number of the line count (m) in the OLED panel 11.
The correction data storage circuit 132 stores the image data Pic of each pixel 11(i, j) once the image data Pic is supplied from the display signal generation circuit 12, and stores the data related to correction of the voltage-current characteristics-related data of the transistor T3 in each pixel circuit 11(i, j) and the image data Pic.
The correction data storage circuit 132 includes a storage area used to store the image data Pic values, a storage area used to store the threshold voltage Vth values, a storage area used to store the β values and a storage area used to store the voltage Vsink values according to each pixel circuit 11(i, j). Additionally, the correction data storage circuit 132 stores the current values of the current Isink as the data related to the voltage-current characteristics of the transistor T3 for each pixel circuit 11(i, j).
The correction processing circuit 133 is used to perform a correction processing with the image data Pic. The correction processing circuit 133 reads the threshold voltages Vth and the voltages Vsink from the correction data storage circuit 132 for each line, and reads the current values in the current Isink.
Then, the correction processing circuit 133 computes the result according to Formula 7 using the threshold voltage Vth, the voltage Vsink and the current Isink. As a result, the β value for each pixel circuit 11(i, j) is acquired as data related to the voltage-current characteristics of the transistor T3. The correction processing circuit 133 stores the β value acquired for each pixel circuit 11(i, j) into the storage area corresponding to the correction data storage circuit 132.
The correction processing circuit 133 reads the image data Pic, the threshold voltage Vth of the transistor T3 in each pixel circuit 11(i, j) and the β value from the correction data storage circuit 132 for each line, and corrects the image data Pic.
The controller 13 outputs the image data Pic, which is corrected by the correction processing circuit 133 to the data driver 16 for each line as the correction gradation signals Sdata(1) through Sdata(m), which in turn correspond to the selected j-line pixel circuits 11(1, j) through 11(m, j).
Additionally, when the video signal Image is supplied from the external source, the controller 13 generates clock signals CLK1 and CLK2 that are synchronized to the synchronous signal Sync, as supplied from the display signal generation circuit 12, and various control signals such as the start signals Sp1 and Sp2 used to start up an operation.
Subsequently, the controller 13 supplies those generated control signals to the select driver 14, the power-supply driver 15 and the data driver 16.
As shown in
The select driver 14 synchronizes the start signal Sp1, which is synchronized to a vertical synchronous signal supplied as a vertical control signal from the controller 13. According to the clock signal CLK1, which is to be supplied from the controller 13 as the vertical control signal, the select driver 14 selects each line in the OLED panel 11 by sending the high-level select signal Vselect(j) to the pixel circuits 11(1, 1) through 11(m, 1) for the first line, . . . , pixel circuits 11(1, n) through 11(m, n) for the nth line, one by one.
The power-supply driver 15 is used to output the voltage VL or VH voltage signals Vsource(1) through Vsource(n) to the voltage lines Lv(1) through Lv(n) one by one, and is connected to the drain of the transistor T3 in each pixel circuit 11(i, j) via the voltage lines Lv(j) (j=1 to n).
The power-supply driver 15 receives the start signal Sp2 from the controller 13 and starts up an operation according to the clock signal CLK2 supplied from the controller 13.
The power-supply driver 15 then outputs the voltage VL or VH voltage signals Vsource(1) through Vsource(n). The voltage VL is used to set the OLED 111 in each pixel circuit 11(i, j) to the non-emitting state during the write operation and the like. In this embodiment, the cathode voltage Vcath in the OLED 111 is set to 0 V and the voltage VL is set to 0 V or a potential lower than 0 V.
The voltage VH is used to set the OLED 111 in each pixel circuit 11(i, j) to the emitting state. In this embodiment, the voltage VH is set, for example, to +15 V.
The data driver 16 outputs the voltage signal Sv(i), which contains the analog gradation voltage Vdata(i) to the data line Ld(i), and writes the gradation voltage Vdata(i) in the capacitor C1 that is connected between the gate and source in the transistor T3 for each pixel circuit 11(i, j).
As shown in
The shift register/data register circuit 161 is used to write the digital correction gradation signals Sdata(1) through Sdata(m) supplied from the controller 13 corresponding to the data lines Ld(1) through Ld(m) by shifting one by one. Subsequently, the shift register/data register circuit 161 supplies the provided correction gradation signals Sdata(1) through Sdata(m) to the data latch circuit 162.
The data latch circuit 162 is used to retain the correction gradation signals Sdata(1) through Sdata(m) supplied from the shift register/data register circuit 161, and then supplies the correction gradation signals Sdata(1) through Sdata(m) to the D/A converter circuit 163.
The D/A converter circuit 163 generates the voltage signals Sv(1) through Sv(m) that have the gradation voltages Vdata(1) through Vdata(m) which are converted from the digital correction gradation signals Sdata(1) to Sdata(m) to analog values. In this case, the gradation voltages Vdata(1) through Vdata(m) have negative polarity.
The D/A converter circuit 163 supplies the generated voltage signals Sv(1) through Sv(m) to the characteristics-acquiring switching circuit 17.
When the D/A converter circuit 163 is used to acquire the threshold voltage Vth for each pixel circuit 11(i, j) through the use of the auto-zero method, the D/A converter circuit 163 outputs the voltage signals of the initial voltage Vprimary (instead of the voltage signals Sv(1) through Sv(m)) to the characteristics-acquiring switching circuit 17. For instance, the voltage signals of the initial voltage Vprimary are set in the D/A converter circuit 163 in advance. Alternatively, by setting the correction gradation signals Sdata(1) through Sdata(m) to be supplied from the controller 13 to the shift register/data register circuit 161 to signals corresponding to the initial voltage Vprimary, the voltage signals of the initial voltage Vprimary may output from the D/A converter circuit 163. In any case, the D/A converter circuit 163 functions as the voltage-applied circuit in this invention.
The characteristics-acquiring switching circuit 17 is used to output the voltage signals Sv(1) through Sv(m) supplied from the data driver 16, signals of the initial voltage Vprimary or the current Isink onto the data lines Ld(1) through Ld(m). As shown in
The current sources 171(1) through 171(m) are used to supply the current Isink for measurement. The current sources 171(1) through 171(m) supply the current Isink from the data lines Ld(1) through Ld(m) to the side of the data lines Ld(1) through Ld(m) via transistor T3 for each line in the drawing-in direction. The current values of the current Isink are either set to each current source 171(1) through 171(m) in advance or are set by the controller 13. Each current downstream terminal of the current sources 171(1) through 171(m) is set to the potential Vss.
The transistors T11(1) through T11(m), T12(1) through T12(m) and T13(1) through T13(m) are TFTs (Thin-Film Transistors) which are configured by the n-channel type FET.
The transistors T11(1) through T11(m) are turned on and off according to the control signal Cg1 to be supplied from the controller 13, and are used to connect or disconnect between the data driver 16 and the OEL panel 11. The source in the transistors T11(1) through T11(m) is connected to the D/A converter circuit 163 in the data driver 16.
The transistors T11(1) through T11(m) are turned on after a high-level control signal Cg1 (hereinafter referred to as the control signal Cg1(High)) is supplied from the controller 13 to the gate. When the transistors T11(1) through T11(m) are turned on, and the transistors T11(1) through T11(m) connect the D/A converter circuit 163 and the data lines Ld(1) through Ld(m).
The transistors T11(1) through T11(m) are turned off after a low-level control signal Cg1 (hereinafter referred to as the control signal Cg1(Low)) is supplied from the controller 13 to the gate. When the transistors T11(1) through T11(m) are turned off, the transistors T11(1) through T11(m) disconnect between the D/A converter circuit 163 and the data lines Ld(1) through Ld(m).
The transistors T12(1) through T12(m) are used to connect or disconnect between the current sources 171(1) through 171(m) and the data lines Ld(1) through Ld(m).
The drains in the transistors T12(1) through T12(m) are connected to the data lines Ld(1) through Ld(m) respectively, and the source is connected to the current upstream terminals of the current sources 171(1) through 171(m). Each gate is connected to the controller 13, and the control signal Cg2 is supplied from the controller 13.
The transistors T12(1) through T12(m) are turned on after a high-level control signal Cg2 (hereinafter referred to as the control signal Cg2(High)) is supplied from the controller 13 to the gate. When the transistors T12(1) through T12(m) are turned on, the transistors T12(1) through T12(m) connect between the current source 171(1) and the data line Ld(1), . . . , the current source 171(m) and the data line Ld(m), respectively.
The transistors T12(1) through T12(m) are turned off after a low-level control signal Cg2 (hereinafter referred to as the control signal Cg2(Low)) is supplied from the controller 13 to the gate. When the transistors T12(1) through T12(m) are turned off, the transistors T12(1) through T12(m) disconnect between the current source 171(1) and the data line Ld(1), . . . , the current source 171(m) and the data line Ld(m), respectively.
The transistors T13(1) through T13(m) are used to connect or disconnect between the current downstream terminals of the current sources 171(1) through 171(m) and the A/D converter circuit 131 in the controller 13.
The drains in the transistors T13(1) through T13(m) are connected to the current downstream terminals of the current sources 171(1) through 171(m) and the data lines Ld(1) through Ld(m), respectively, and the sources are connected to the A/D converter circuit 131 in the controller 13. The gates are connected to the controller 13, whereupon the control signal Cg3 is supplied from the controller 13. The m number of A/D converter circuits 131 in the controller 13 is installed corresponding to the transistors T13(1) through T13(m), and the converters are connected to the sources in the transistors T13(1) through T13(m).
The transistors T13(1) through T13(m) are turned on after a high-level control signal Cg3 (hereinafter referred to as the control signal Cg3(High)) is supplied. When the transistors T13(1) through T13(m) are turned on, the current downstream terminal of the current sources 171(1) through 171(m) and the data lines Ld(1) through Ld(m) are connected to the A/D converter circuit 131 in the controller 13. Consequently, the voltages Vd(1) through Vd(m) of the data lines Ld(1) through Ld(m) are applied to the A/D converter circuit 131 in the controller 13.
The transistors T13(1) through T13(m) are turned off after a low-level control signal Cg3 (hereinafter referred to as the control signal Cg3(Low)) is supplied. When the transistors T13(1) through T13(m) are turned off, the connections between the current downstream terminals of the current sources 171(1) through 171(m) and the A/D converter circuit 131 in the controller 13 are cut off.
The following describes the display device operation according to this embodiment. Note that the transistors T11, T12 and T13 are indicated as switches in
The display device 1 is used to acquire the threshold voltage Vth in each transistor T3 in each pixel circuit 11(1, 1) through 11(m, 1), . . . , 11(1, n) through 11(m, n), and the β values at the time of factory shipment before the actual operation.
The following describes the operation to acquire the threshold voltage Vth. The controller 13 acquires the threshold voltage Vth of each transistor T3 in each pixel circuit 11(1, 1) through 11(m, 1), . . . , 11(1, n) through 11(m, n) using the auto-zero method.
Thus, the controller 13 supplies the start signals Sp1 and Sp2, the clock signals CLK1 and CLK2 to the select driver 14, the power-supply driver 15 and the data driver 16.
The select driver 14, the power-supply driver 15 and the data driver 16 start the operation after the start signals Sp1 and Sp2 are supplied from the controller 13, and operate according to the clock signals CLK1 and CLK2.
After the select driver 14 starts the operation, the select driver 14 outputs the high-level signals Vselect(1), Vselect(2), . . . Vselect(n) to the select lines Ls(1), Ls(2), . . . Ls(n), one by one.
As shown in
The period being output from the high-level signal Vselect(1) to the select line Ls(1) by the select driver 14 becomes the period of first-line selection.
The power-supply driver 15 applies the voltage signal Vsource(1) of the voltage VL to the voltage line Lv(j).
At this time, the voltage of the voltage line Lv(1) is set to 0 V even if each transistor T3 in the pixel circuits 11(1, 1) through 11(m, 1) is turned on; however, the current does not flow into the OLED 111 because the cathode voltage in the OLED 111 is 0 V.
As shown in
The transistors T11(1) through T11(m) in the characteristics-acquiring switching circuit 17 are turned on after the control signal Cg1(High) is supplied to the gates. Consequently, the D/A converter circuit 163 and the data lines Ld(1) through Ld(m) are connected.
The transistors T12(1) through T12(m) are turned off after the control signal Cg2(Low) is supplied to the gates, whereupon the transistors T12(1) through T12(m) disconnect between the current sources 171(1) through 171(m) and the data lines Ld(1) through Ld(m), respectively.
The transistors T13(1) through T13(m) are turned off after the control signal Cg3(Low) is supplied to the gates. Consequently, the transistors T13(1) through T13(m) disconnect between the current downstream terminals of the current sources 171(1) through 171(m) and the A/D converter circuit 131 in the controller 13.
The D/A converter circuit 163 outputs the voltage signal of the initial voltage Vprimary to the characteristics-acquiring switching circuit 17. As a result, the initial voltage Vprimary is applied to the data line Ld(1).
As shown in
The capacitor C1 in the pixel circuit 11(1, 1) is charged using this initial voltage Vprimary. Similarly, each capacitor C1 in pixel circuits 11(2, 1) through 11(m, 1) is charged using this initial voltage Vprimary.
When the current is at time t11 after the capacitor C1 is charged with the initial voltage Vprimary, the controller 13 supplies the control signal Cg1(Low) to the characteristics-acquiring switching circuit 17, as shown in
The transistors T11(1) through T11(m) are turned off after the control signal Cg1(Low) is supplied to the gates. When the transistor T11(1) is turned off, the drain voltage Vds in the transistor T3 is naturally relaxed through the capacitor C1 and gradually degraded.
When time t12 arrives (once the relaxation time t is elapsed from time t11), the drain voltage Vds is degraded to the threshold voltage Vth and the drain current Id hardly flows into the transistor T3. As shown in
As shown in
The transistors T13(1) through T13(m) in the characteristics-acquiring switching circuit 17 are turned on after the control signal Cg3(High) is supplied to the gates. Consequently, the data lines Ld(1) through Ld(m) are connected to the A/D converter circuit 131 in the controller 13.
The A/D converter circuit 131 is used to measure the voltages Vd(1) through Vd(m) of the data lines Ld(1) through Ld(m) in parallel, and to acquire the voltages Vd(1) through Vd(m) as the threshold voltage Vth of the transistor T3 in the pixel circuits 11(1, 1) through 11(m, 1).
The A/D converter circuit 131 stores the threshold voltage Vth in the transistor T3 for the pixel circuits 11(1, 1) through 11(m, 1) into the storage areas corresponding to the pixel circuits 11(1, 1) through 11(m, 1) in the correction data storage circuit 132.
Similarly, the A/D converter circuit 131 acquires the threshold voltage Vth in the transistor T3 for each pixel circuit 11(i, j) during each selection period used to select the second line, . . . , nth line pixel circuit 11(i, j) by the select driver 14. Also, the acquired threshold voltage Vth is stored in each storage area in the correction data storage circuit 132.
The following describes an operation used to acquire the β value: The display device 1 acquires the voltage Vsink in each pixel circuit 11(i, j) according to the current supply-voltage measurement method, and acquires the β value based on the acquired voltage Vsink.
As shown in
When the high-level select signal Vselect(1) is output to the select line Ls(1), the transistors T1 and T2 in the pixel circuits 11(1, 1) through 11(m, 1) are turned on. As a result, the transistor T3 is also turned on.
At that time, the voltage of the voltage line Lv(1) is set to 0 V even if each transistor T3 in the pixel circuits 11(1, 1) through 11(m, 1) is turned on, and the current does not flow into the OLED 111 because the cathode voltage in the OLED 111 is 0 V.
Subsequently, as shown in
The transistors T12(1) through T12(m) are turned on after the control signal Cg2(High) is supplied to the gates. As a result, the current sources 171(1) through 171(m) are connected to the data lines Ld(1) through Ld(m), respectively.
As shown in
When the current Isink flows in the drawing-in direction, the voltages Vd(1) through Vd(m) of the data lines Ld(1) through Ld(m) are degraded as shown in
The controller 13 outputs the control signal Cg3(High) to the characteristics-acquiring switching circuit 17 at time t21, whereupon the voltages Vd(1) through Vd(m) become a constant voltage, as shown in
As shown in
The A/D converter circuit 131 measures the voltages Vd(1) through Vd(m) of the data lines Ld(1) through Ld(m), and acquires the measured voltages Vd(1) through Vd(m) as the voltages Vsink(1) through Vsink(m). The A/D converter circuit 131 then stores the acquired voltages Vsink in the storage areas that correspond to each pixel circuit 11(1, 1) through 11(m, 1) in the correction data storage circuit 132.
The select driver 14 lowers the select signal Vselect(1) to the low-level state at time t22 after acquiring the voltages Vsink(1) through Vsink(m) as shown in
After time t22 is elapsed, the select driver 14 similarly selects the second-line pixel circuits 11(1, 2) through 11(m, 2), . . . , nth-line pixel circuits 11(1, n) through 11(m, n).
The A/D converter circuit 131 measures the voltage of the data lines Ld(1) through Ld(m) for each selection period, and the A/D converter circuit 131 then stores the measured voltages Vd(1) through Vd(m) into each storage area in the correction data storage circuit 132 as the voltages Vsink(1) through Vsink(m).
Subsequently, the correction processing circuit 133 in the controller 13 reads the threshold voltage Vth and the voltage Vsink for each line from the correction data storage circuit 132, and computes the β values for each pixel circuit 11(i, j) according to Formula 7.
The correction processing circuit 133 stores the β value for each pixel circuit 11(i, j) acquired by means of the computation in the correction data storage circuit 132.
The threshold voltage Vth and the β values are acquired from the above description. After the acquired threshold voltage Vth and the β values are stored in the correction data storage circuit 132, the video signal Image is supplied from the external source. The following describes an operation in which the OLED 111 in each pixel circuit 11(i, j) is in a light emitting operation.
When the video signal Image is supplied from the external source, the display signal generation circuit 12 acquires the image data Pic from the supplied video signal Image and the synchronous signal Sync, and supplies the image data Pic and the synchronous signal Sync to the controller 13. The controller 13 stores the supplied image data Pic into the correction data storage circuit 132.
Subsequently, the controller 13 executes the processing to write the voltage signals Sv(1) through Sv(m) to the capacitor C1 in each pixel circuit 11(i, j).
The controller 13 outputs the control signals Cg2(Low) and Cg3(Low) to the characteristics-acquiring switching circuit 17, and then outputs the start signals Sp1 and Sp2 to the select driver 14, the power-supply driver 15 and the data driver 16.
The select driver 14, the power-supply driver 15 and the data driver 16 start the operation after the start signals Sp1 and Sp2 are supplied from the controller 13, and operate according to the clock signals CLK1 and CLK2.
After the select driver 14 starts the operation, and when the select driver 14 outputs the high-level signal Vselect(1) to the select line Ls(1) at time t31 as shown in
At this time, the current does not flow into the OLED 111 even if the power-supply driver 15 outputs the signal Vsource(1) of voltage VL=0 V to the voltage line Lv(1) because the cathode voltage Vcath is 0 V.
The controller 13 outputs the control signal Cg1(High) to the characteristics-acquiring switching circuit 17. The transistors T11(1) through T11(m) are turned on after the control signal Cg1(High) is supplied to the gates. As a result, the D/A converter circuit 163 and the data lines Ld(1) through Ld(m) are connected.
The correction processing circuit 133 in the controller 13 reads the image data Pic from the correction data storage circuit 132, the threshold voltage Vth in the transistor T3 in each pixel circuit 11(i, j) and the β value for each line, and then corrects the voltage value Vcode corresponding to the gradation values of the image data Pic for each line according to Formula 5, whereupon the correction processing circuit 133 acquires the correction gradation signals Sdata(1) through Sdata(m).
The controller 13 outputs the correction gradation signals Sdata(1) through Sdata(m) acquired by the correction processing circuit 133 to the data driver 16.
The shift register/data register circuit 161 in the data driver 16 reads the digital correction gradation signals Sdata(1) through Sdata(m) supplied from the controller 13 by shifting one by one, and supplies the digital correction gradation signals Sdata(1) through Sdata(m) to the data latch circuit 162.
The data latch circuit 162 retains the correction gradation signals Sdata(1) through Sdata(m) supplied from the shift register/data register circuit 161, and supplies the correction gradation signals Sdata(1) through Sdata(m) to the D/A converter circuit 163. The D/A converter circuit 163 generates the voltage signals Sv(1) through Sv(m) that have the negative polarity gradation voltages Vdata(1) through Vdata(m) which are converted from the digital correction gradation signals Sdata(1) through Sdata(m) retained by the data latch circuit 162 into analog values.
The D/A converter circuit 163 supplies the generated voltage signals Sv(1) through Sv(m) to the characteristics-acquiring switching circuit 17. Since the D/A converter circuit 163 and the data lines Ld(1) through Ld(m) are connected via the transistors T11(1) through T11(m) respectively, the voltage signals Sv(1) through Sv(m) are output to the data lines Ld(1) through Ld(m), respectively.
When the negative polarity voltage signals Sv(1) through Sv(m) are output to the data lines Ld(1) through Ld(m), the current flows from the power-supply driver 15 to the D/A converter circuit 163 via the pixel circuits 11(1, 1) through 11(m, 1) and the transistors T11(1) through T11(m).
As a result, each capacitor C1 in the pixel circuits 11(1, 1) through 11(m, 1) is charged with the gradation voltages Vdata(1) through Vdata(m) of the voltage signals Sv(1) through Sv(m).
The select driver 14 lowers the signal Vselect(1) to the low-level state at time t41. When the signal Vselect(1) is set to the low-level state, the transistors T1 and T2 in the pixel circuits 11(1, 1) through 11(m, 1) are turned off.
Each capacitor C1 in the pixel circuits 11(1, 1) through 11(m, 1) retains the voltage of the charged voltage signals Sv(1) through Sv(m), respectively.
As for the second line pixel circuits 11(1, 2) through 11(m, 2), . . . , nth line pixel circuits 11(1, n) through 11(m, n), the controller 13 executes the write processing similar to the one used for the first line. Each capacitor C1 retains the voltages of the charged voltage signals Sv(1) through Sv(m).
Once the write processing is complete, the controller 13 controls the light emitting operation. As shown in
When the signal level of the select lines Ls(1) through Ls(n) becomes the low-level state, the transistors T1 and T2 in all pixel circuits 11(i, j) are turned off, and the transistor T3 enters to the flowing state.
The power-supply driver 15 outputs the signals Vsource(1) through Vsource(n) of the voltage VH (=+15 V) to the voltage lines Lv(1) through Lv(n).
When the voltage of the voltage lines Lv(1) through Lv(n) is set to the voltage VH, as in setting the voltage retained by each capacitor C1 to the gate voltage Vgs, the transistor T3 in each pixel circuit 11(i, j) supplies the drain current Id (which corresponds to the gate voltage Vgs) to the OLED 111.
When this drain current Id flows, each OLED 111 emits with the luminance corresponding to the current values.
As described above, according to this embodiment, the threshold voltage Vth of the transistor T3 in each pixel circuit 11(i, j) is acquired using the auto-zero method. Furthermore, the current Isink is supplied using the current supply-voltage measurement method in order to acquire the voltage Vsink and the β value.
Therefore, the threshold voltage Vth and the β value of the transistor T3 in each pixel circuit 11(i, j) can be acquired without complicated calculation. Because the image data Pc is corrected based on the β value in addition to the threshold voltage Vth, the over-time change of the transistor T3 as well as any variations in manufacturing processes can be corrected in order to control the degradation of image quality.
Furthermore, the controller 13 can be used to measure the threshold voltage Vth in the transistor T3 for each pixel circuit 11(i, j) simply by installing the A/D converter circuit 131, and also to measure the voltage Vsink, which simplifies the circuits and makes computation processing easier.
Note that this invention is not limited to the application described above, but also allows various other applications.
In this embodiment, for example, the display device 1 is used to describe the current supply-voltage measurement method for acquiring the voltage-current characteristics of the transistor T3 in each pixel circuit 11(i, j). However, the voltage-current characteristics of the transistor T3 in each pixel circuit 11(i, j) may also be acquired using the voltage-applied current measurement method.
In this case, as shown in
While the high-level select signal Vselect(1) is output to the select line Ls(1), as shown in
Note that the voltage preset according to the voltage values may be applied to each data line Ld(1) through Ld(m) from the D/A converter circuit 163 instead of providing the voltage sources to the characteristics-acquiring switching circuit 17.
In the above embodiment, the characteristics-acquiring switching circuit 17 is described as a configuration installed separately from the data driver 16. However, the data driver 16 may have the characteristics-acquiring switching circuit 17 built-in.
In the above embodiment, the controller 13 includes two or more A/D converter circuits 131. However, the data driver 16 may include two or more A/D converter circuits 131, and each A/D converter circuit 131 may be connected to the source in the transistor T13.
In the above embodiment, the same number of A/D converter circuits 131 as the line number of the OEL panel 11 is installed in order to perform the measurement for the voltage Vd in parallel. However, for example, a smaller number of A/D converter circuits 131 than the line number of the OEL panel 11 may be installed, in which case the connection between each data line and each A/D converter circuit 131 is switched one by one to perform the measurement for the voltage Vd. Furthermore, it is possible to install only one A/D converter circuit 131, in which case the connection may be switched one by one for every data line in order to perform the measurement for the voltage Vd. Thus, the time required for the voltage Vd measurement for all data lines is increased in comparison to a case in which two or more A/D converter circuits are installed. Nevertheless, the circuit scale can be reduced.
In the above embodiment, there are three transistors used in as a configuration of the pixel circuit 11(i, j). However, the pixel circuit 11(i, j) is not limited to this configuration. For instance, a pixel circuit may have a configuration of two transistors or more than three transistors.
Moreover, this invention is described for a case that is applicable to the display device 1 including the OEL panel 11, but it is not limited to such an application.
For example, this invention may be applied to an exposure device which includes multiple pixels having the light emitting elements by means of the OLED 111 and including the light emitting element array arranged in one direction, and which is used to irradiate and expose the light emitted from the light emitting element array to the photoreceptor drum according to the image data. In this case, the degradation of exposure conditions caused by degradation over time, or due to variations in characteristics, can be controlled.
Having described and illustrated the principles of this application by reference to one or more preferred embodiments, it should be apparent that the preferred embodiment(s) may be modified in arrangement and detail without departing from the principles disclosed herein and that it is intended that the application be construed as including all such modifications and variations insofar as they come within the spirit and scope of the subject matter disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-087471 | Mar 2009 | JP | national |
