This application claims priority to Taiwan Application Serial Number 111100471, filed on Jan. 5, 2022, which is herein incorporated by reference in its entirety.
The present disclosure relates to an electronic device. More particularly, the present disclosure relates to a pixel driving device.
In conventional pixel driving devices, threshold voltages of driving transistors are different, resulting in current differences, which in turn lead to brightness differences and uneven display images of pixel driving devices.
In addition, a driving current required for micro light emitting devices (μ LED) in conventional pixel driving devices to emit light is relatively large. When a driving current flows through a path between two power supply voltages, a voltage difference is too large to generate a driving current difference, which in turn lead to differences in brightness and increased power consumption of a pixel driving device.
Furthermore, based on a structure of conventional pixel driving device, if an optical sensor is added to a pixel driving device, a pixel driving device will be too complicated and difficult to implement.
For the foregoing reason, there is a need to provide some other circuits to solve the problems of the prior art.
One aspect of the present disclosure provides a pixel driving device. The pixel driving device includes a driving transistor, a pixel driving circuit, an optical sensor circuit, and a reset and reading circuit. A first end of the driving transistor is connected to a first node. A control end of the driving transistor is connected to a second node. The driving transistor is configured to control a light emitting device. The pixel driving circuit is connected to the driving transistor, the first node, and the second node, and is configured to receive a first sweep signal, a second sweep signal, and a driving signal. The pixel driving circuit is configured to reset the first node and the second node according to the first sweep signal. The pixel driving circuit is configured to compensate the second node according to the second sweep signal. The pixel driving circuit is configured to control the driving transistor so as to drive the light emitting device according to the driving signal. The optical sensor circuit includes a third node. The optical sensor circuit is configured to receive the driving signal to reset the third node to a voltage level of the driving signal. The optical sensor circuit is configured to perform a sensing process to generate a light sensing signal. The reset and reading circuit is connected to the pixel driving circuit, the optical sensor circuit, and the control end of the driving transistor. The reset and reading circuit is configured to receive a reset and reading signal so as to reset the pixel driving circuit and read out the light sensing signal of the optical sensor circuit at the same time.
Another aspect of the present disclosure provides a pixel driving device. The pixel driving device includes a driving transistor, a pixel driving circuit, and an optical sensor circuit. A first end of the driving transistor is connected to a first node. A control end of the driving transistor is connected to a second node. The driving transistor is configured to control a light emitting device. The pixel driving circuit is configured to receive a first sweep signal, a second sweep signal, a driving signal, and a reset and reading signal. The pixel driving circuit is configured to reset the first node and the second node according to the first sweep signal. The pixel driving circuit is configured to compensate the second node according to the second sweep signal. The pixel driving circuit is configured to control the driving transistor so as to drive the light emitting device according to the driving signal. The pixel driving circuit is configured to turn off the driving transistor according to the reset and reading signal. The optical sensor circuit is connected to the pixel driving circuit. The optical sensor circuit is configured to receive the driving signal and the reset and reading signal. The optical sensor circuit is configured to perform a sensing process so as to a light sensing signal. The optical sensor circuit is configured to output the light sensing signal to a readout line of the pixel driving device according to the reset and reading signal.
These and other aspects of the present disclosure will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications therein may be effected without departing from the spirit and scope of the novel concepts of the disclosure.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the present disclosure as claimed.
The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Furthermore, it should be understood that the terms, “comprising”, “including”, “having”, “containing”, “involving” and the like, used herein are open-ended, that is, including but not limited to.
The terms used in this specification and claims, unless otherwise stated, generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner skilled in the art regarding the description of the disclosure.
In some embodiments, please start form a top end and a right end of each of an element shown in the figure as a first end. A first end of the driving transistor DT1 is connected to a first node N1. A control end driving transistor DT1 is connected to a second node N2. The driving transistor DT1 is configured to control a light emitting device LED. The pixel driving circuit 110 is connected to driving transistor DT1, the first node N1, the second node N2, and is configured to receive first sweep signal S1, a second sweep signal S2, and a driving signal EM.
Then, the pixel driving circuit 110 is configured to reset the first node N1 and the second node N2 according to the first sweep signal S1. The pixel driving circuit 110 is configured to compensate the second node N2 according to the second sweep signal S2. The pixel driving circuit 110 is configured to control the driving transistor DT1 so as to drive the light emitting device LED according to the driving signal EM.
Furthermore, the optical sensor circuit 120 includes a third node N3. The optical sensor circuit 120 is configured to receive the driving signal EM to reset the third node N3 to a voltage level of the driving signal EM.
The reset and reading circuit 130 is connected to the pixel driving circuit 110, the optical sensor circuit 120, and the control end of the driving transistor DT1. Then, the reset and reading circuit 130 is configured to receive a reset and reading signal RR so as to reset the pixel driving circuit 110 and read out the light sensing signal of the optical sensor circuit 120 at the same time.
In some embodiments, the pixel driving circuit 110 includes a reset circuit 111, a compensation circuit 112, and a driving circuit 113. The reset circuit 111 is configured to receive the first sweep signal S1. The reset circuit 111 is configured to reset the first node N1 and the second node N2 according to the first sweep signal S1.
Furthermore, the compensation circuit 112 is connected to the reset circuit 111. The compensation circuit 112 is configured to receive the second sweep signal S2. The compensation circuit 112 is configured to compensate the second node N2 so as to control the driving transistor DT1 to compensate the first node N1 according to the second sweep signal S2.
Then, the driving circuit 113 is connected to the reset circuit 111 and the compensation circuit 112. The driving circuit 113 is configured to receive the EM. The driving circuit 113 is configured to control the driving transistor DT1 so as to drive the light emitting device LED according to the driving signal EM.
In some embodiments, the driving transistor DT1 includes a first end, a second end, and a control end (e.g. a gate terminal of the driving transistor DT1). The first end of the driving transistor DT1 is connected to the first node N1, the second end of the driving transistor DT1 is configured to receive a power supply voltage VSS. The control end of the driving transistor DT1 is connected to the second node N2.
In some embodiments, in order to facilitate the understanding of an operation of the pixel driving device 100 shown in
In some embodiments, the optical sensor circuit 120 is configured to reset the third node N3 of the optical sensor circuit 120 according to the second sweep signal S2 in the second stage I2. The optical sensor circuit 120 is configured to perform a sensing process so as to generate the light sensing signal in the third stage I3.
In some embodiments, the reset and reading circuit 130 is configured to reset the pixel driving circuit 110 and read out the light sensing signal sensed by the optical sensor circuit 120 in the third stage I3 according to the reset and reading signal RR in a fourth stage I4.
In some embodiments, please refer to
In addition, please refer to
Additionally, the second transistor T2 includes a first end, a second end, and a control end (e.g. a gate terminal of the second transistor T2). The first end of the second transistor T2 is configured to receive a first low reference voltage source VREFH. The second end of the second transistor T2 is connected to the second end of the first capacitor C1. The control end of the second transistor T2 is configured to receive the first sweep signal S1 in the first stage I1. The second transistor T2 is configured to reset the second end of the first capacitor C1 in response to the first sweep signal S1.
Furthermore, the third transistor T3 includes a first end, a second end, and a control end (e.g. a gate terminal of the third transistor T3). The first end of the third transistor T3 is configured to receive the first high reference voltage source VREFH. The second end of the third transistor T3 is connected to the first node N1. The control end of the third transistor T3 is configured to receive the first sweep signal S1 in the first stage I1. The third transistor T3 is configured to reset the first node N1 in response to the first sweep signal S1.
In some embodiments, please refer to
In addition, please refer to
Additionally, the fifth transistor T5 includes a first end, a second end, and a control end (e.g. a gate terminal of the fifth transistor T5). The first end of the fifth transistor T5 is configured to receive a first reference voltage source VREF. The second end of the fifth transistor T5 is connected to the second node N2. The control end of the fifth transistor T5 is configured to receive the second sweep signal S2 in the second stage I2 The fifth transistor T5 is configured to compensate the second node N2 in response to the second sweep signal S2 in the second stage I2.
In some embodiments, please refer to
In some embodiments, please refer to
Then, the first reset transistor T7 includes a first end, a second end, and a control end (e.g. a gate terminal of the first reset transistor T7). The first end of the first reset transistor T7 is connected to the second node N2 of the driving circuit 113 of the pixel driving circuit 110. The second end of the first reset transistor T7 is configured to receive the first high reference voltage source VREFH. The control end of the first reset transistor T7 is configured to receive the reset and reading signal RR in the fourth stage I4. The first reset transistor T7 is configured to reset the second node N2 of the driving circuit 113 of the pixel driving circuit 110 in response to the reset and reading signal RR.
Furthermore, please refer to
In some embodiments, please refer to
Then, please refer to
Furthermore, the second reset transistor T9 includes a first end, a second end, and a control end (e.g. a gate terminal of the second reset transistor T9). The first end of the second reset transistor T9 is configured to receive the driving signal EM. The second end of the second reset transistor T9 is connected to the third node N3. The control end of the second reset transistor T9 is configured to receive the second sweep signal S2 in the second stage I2. The second reset transistor T9 is configured to reset the third node N3 to a voltage level VGH of the driving signal EM in response to the second sweep signal S2.
In some embodiments, the aforementioned driving transistor DT1, and transistors T1 to T9 includes P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS).
In some embodiments, the first sweep signal S1 writes the voltage level of the first high reference voltage source VREFH to the second node N2 through the first transistor T1 of the reset circuit 111. The control end of the driving transistor DT1 is configured to receive the voltage level of the second node N2. The driving transistor DT1 is turned off in response to the voltage level. The first sweep signal S1 writes the voltage level of a first low reference voltage source VREFL to the second end of the first capacitor C1 (La the fourth node N4) through the second transistor T2. The first sweep signal S1 writes the voltage level of the first high reference voltage source VREFH to the first end of the first capacitor C1 through the third transistor T3.
At this time, a voltage level of the first node N1 is the voltage level of first high reference voltage source VREFH. A voltage level of the second node N2 is the voltage level of the first high reference voltage source VREFH. A voltage level of the fourth node N4 is the voltage level of the first low reference voltage source VREFL.
In some embodiments, the second sweep signal S2 writes the voltage level of the data voltage source VDATA to the fourth node N4 through the fourth transistor T4 of the compensation circuit 112. The second sweep signal S2 writes the voltage level of the first reference voltage source VREF to the second node N2 through the fifth transistor T5. Since the voltage level of the second node N2 is discharged to the voltage level of the first reference voltage source VREF, the driving transistor DT1 is configure to compensate the first node N1 in response the voltage level of the second node N2.
At the same time, the second sweep signal S2 resets the third node N3 to the voltage level VGH of the driving signal EM through the second reset transistor T9 of the optical sensor circuit 120.
At this time, a voltage level of the first node N1 is the voltage level of the first reference voltage source VREF plus a threshold voltage VTH_DT1 of the driving transistor DT1. A voltage level of the second node N2 is the voltage level of reference voltage source VREF. A voltage level of the third node N3 is the voltage level VGH of the driving signal EM. A voltage level of the fourth node N4 is the voltage level of the data voltage source VDATA.
In some embodiments, the driving signal EM connects the second node N2 and the fourth node N4 through the sixth transistor T6 and indirectly connects the first node N1 and the second node N2.
In some embodiments, the driving transistor DT1 is turned on according to a voltage difference between the first end and the control end of the driving transistor DT1. The first end of the driving transistor DT1 is equivalent to the first node N1. The control end of the driving transistor DT1 is equivalent to the second node N2. After the sixth transistor T6 is turned on, the driving transistor DT1 is turned on, so that a voltage level of the second node N2 becomes (VREF+|VTH_DT1|−VSS). The first end of the first capacitor C1 responds to a change of the voltage level of the second node N2, and the second end of the first capacitor C1 senses the first end of the first capacitor C1 to change the fourth node N4 to (VDATA+VSS−VREF−|VTH_DT1|).
In addition, a driving current Id is output according to the voltage difference between the first end and the control end of the driving transistor DT1. The voltage difference between the first end and the control end of the driving transistor DT1 is equivalent to a voltage difference between the fourth node N4 and the second node N2. A formula of the above driving current Id is listed below:
In the formula 1, Id is the driving current, VSG is the voltage difference between the first end and the control end of the driving transistor DT1, and Vth is a threshold voltage. In the third stage I3, the voltage level of the control end of the driving transistor DT1 is (VDATA+VSS−VREF−)|VTH_DT1|), and the voltage level of the second end of the driving transistor DT1 is VSS. Substitute the voltage level of the control end and the second end of the driving transistor DT1 into the formula 1, a following formula can be obtained:
In aforementioned formula 2, the same voltage levels cancel each other out, and the formula 2 is rewritten as below:
At the same time, please refer to
It is further explained that, in the third stage I3, a voltage level of the third node N3 is determined by the intensity of the photocurrent Ip1. Therefore, the voltage level of the third node N3 has various situations. The voltage level of the third node N3 shown in
In some embodiments, the reset and reading signal RR writes the voltage level of the first high reference voltage source VREFH to the second node N2 through the first reset transistor T7, and the driving transistor DT1 is turned off in response to the voltage level of the second node N2. The reset and reading signal RR reads out the light sensing signal sensed by the optical sensor SRO of the optical sensor circuit 120 in the third stage I3 through the read transistor T8, and outputs the light sensing signal to the readout line O.
In some embodiments, the optical sensor circuit 120A is further configured to receive the second sweep signal S2. The optical sensor circuit 120A includes the third node N3, a second capacitor C2, and a light sensing transistor T10.
Then, the second capacitor C2 includes a first end and a second end. The first end of the second capacitor C2 is connected to the third node N3. The second end of the second capacitor C2 is configured to receive the first reference voltage source VREF.
Furthermore, please refer to
In some embodiments, please refer to
In some embodiments, please refer to
In some embodiments, the optical sensor circuit 120B includes the third node N3, a capacitor C3, and a light sensing diode PIN.
Then, the capacitor C3 includes a first end and a second end. The first end of the capacitor C3 is connected to the third node N3. The second end of the capacitor C3 is configured to receive the first reference voltage source VREF.
Furthermore, the light sensing diode PIN includes an anode terminal and a cathode terminal. The anode terminal of the light sensing diode PIN is configured to receive the driving signal EM. The cathode terminal of the light sensing diode PIN is connected to the third node N3. The light sensing diode PIN is configured to perform a sensing process a light L3 to generate the light sensing signal. While generating the light sensing signal, the light sensing diode PIN will generate a photocurrent Ip3. The light L3 includes at least one of a specific spectrum and a visible spectrum.
In some embodiments, the first end of the driving transistor DT1 is connected to the first node N1. The control end of the driving transistor DT1 is connected to the second node N2. The driving transistor DT1 is configured to control the light emitting device LED.
Then, the pixel driving circuit 210 is configured to receive the first sweep signal S1, the second sweep signal S2, the driving signal EM, and the reset and reading signal RR. The pixel driving circuit 210 is configured to reset the first node N1 and the second node N2 according to the first sweep signal S1. The pixel driving circuit 210 is configured to compensate the second node N2 according to the second sweep signal S2. The pixel driving circuit 210 is configured to control the driving transistor DT1 so as to drive the light emitting device LED according to the driving signal EM. The pixel driving circuit 210 is configured to turn off the driving transistor DT1 according to the reset and reading signal RR.
Furthermore, the optical sensor circuit 220 is connected to the pixel driving circuit 210. The optical sensor circuit 220 is configured to receive the driving signal EM and the reset and reading signal RR. The optical sensor circuit 220 is configured to perform a sensing process so as to generate the light sensing signal. The optical sensor circuit 220 is configured to output the light sensing signal to the readout line O of the pixel driving device 200 according to the reset and reading signal RR.
It should be note that, please refer to
In some embodiments, the pixel driving circuit 210 includes a reset circuit 211, a compensation circuit 212, and a driving circuit 213. The transistor T7 in
It is further explained that, the embodiment of
Then, please refer to
Furthermore, please refer to
In some embodiments, the optical sensor circuit 220 and the pixel driving circuit 210 are connected to a signal source of the reset and reading signal RR.
In some embodiments, please refer to
In some embodiments, a direction of the signal transmitted by the data line (e.g. a location of the data voltage source VDATA) and a direction of the signal transmitted by the readout line O are the same direction.
Based on the above embodiments, the present disclosure provides a pixel driving device to reduce a voltage difference between two power supply voltages so as to reduce power consumption, and an optical sensor is added so that a pixel driving device can sense and display at the same time.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of the present disclosure provided they fall within the scope of the following claims.
Number | Date | Country | Kind |
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111100471 | Jan 2022 | TW | national |
Number | Name | Date | Kind |
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20190035326 | Wang et al. | Jan 2019 | A1 |
20210173544 | Yang | Jun 2021 | A1 |
20210407379 | Yang et al. | Dec 2021 | A1 |
Number | Date | Country |
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108154844 | Jun 2018 | CN |