Patent Application
20050219173
Data is often loaded from top to bottom on many pulse-modulated micro-displays using continuous rastering. However, this often involves high average data rates and may involve decoupling pixel activation from the data loading.
In the following detailed description of the present embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments that may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice disclosed subject matter, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.
Projector 100 also includes a controller 140 for controlling the operation of micro-displays 120. For one embodiment, controller 140 controls the modulation of micro-displays 120. For another embodiment, controller 140 is adapted to perform methods in accordance with embodiments of the present disclosure in response to computer-readable instructions. These computer-readable instructions are stored on a computer-usable media 150 of controller 140 and may be in the form of software, firmware, or hardware. In a hardware solution, the instructions are hard coded as part of a processor, e.g., an application-specific integrated circuit (ASIC) chip, a field programmable gate array (FPGA), etc. In a software or firmware solution, the instructions are stored for retrieval by controller 140. Some additional examples of computer-usable media include static or dynamic random access memory (SRAM or DRAM), read-only memory (ROM), electrically-erasable programmable ROM (EEPROM or flash memory), magnetic media and optical media, whether permanent or removable.
Controller 140 receives digital source data, for example, from an image source 160, such as a computer, DVD player, a set-top box connected to a direct television satellite link, or a cable television provider, etc. For some embodiments, controller 140 formats the digital data in a multiple bit format, such as an eight bit per color format, e.g., eight bits for each of the colors red, green, and blue. Each of the micro-displays 120 displays one bit of data on each of its pixels. That is, when the level of a bit is a logic HIGH, for example, the pixel is ON or active, and when the level of a bit is a logic LOW, the pixel is OFF or inactive.
Following are definitions of terms used in conjunction with describing FIGS. 2-4: An array segment is an arbitrary group of pixel rows, e.g., 16 pixels tall by the array width, of a micro-display 120. Time slices are increments of time corresponding to the color depth of the source data. For example, displaying a single 8-bit color source on a micro-display 120 would require 28−1=255 time slices that fit within a source frame time (in the case of video). 8-bit color requires 28=256 digital codes to represent, but only requires 255 time slices to display because the color black (code 0) requires zero time slices of display time. The source frame time is defined as the time it takes to display all of the bits of source data. A time slice corresponds to the shortest time a color is displayed on a pixel. For one embodiment, this corresponds to the binary-weighted time the least significant bit for that color, i.e., the binary bit 0 (or the zeroth binary bit), is displayed. For a source frame time of (1/60) seconds and for three colors displayed on a singe micro-display, this is [(1/60) seconds/frame]/[(3 colors/time slice)×(255 time slices/frame)]=21.79 micro-seconds. In general, the binary-weighted display time for the Nth bit, for this example, is tN=(21.79 micro seconds)×2N. Sub-slices are divisions of time slices. The duration of a sub-slice enables the algorithm described herein produce short bit display times. For one embodiment, there are an even integer number of sub-slices per time slice for producing a linear display output. For another embodiment, there two sub-slices per time slice, as shown in
During time-slice 0, sub-slice 0, each pixel of segment 0 is set to on/off for x0 data. Bit zero for each pixel will only be ON if the 0-255 color description (e.g., 8-bit/color representation) is an odd value (logic HIGH), for one embodiment. During time-slice 0, sub-slice 1 nothing is loaded. The display time for the x0 data expires at the end of time slice 0, and the pixels of segment 0 can be reloaded with on/off data corresponding to another bit level and/or color at time-slice 1, sub-slice 0, such as y5 data, as shown in
Note that the total duration a bit is displayed on a pixel corresponds to the color intensity of the bit being displayed. Therefore, the spatial order in which segments are loaded does not matter. However,
Note further that each segment is reloaded exactly on time-slice 2(bit#) after the previous data load on that segment, for one embodiment. For example, each segment of
Note that for one embodiment, first pixel data, e.g., x0 data, intended for a portion of a pixel array, e.g., segment 0, and having a first bit level, e.g., bit level 0, is loaded at a first time, e.g., at sub-slice 0 of time-slice 0, and is immediately displayed for a first time duration, e.g., one time slice, as shown in
The information represented in
For one embodiment, the number of allocated sub slices may be increased by multiples of two. That is, (2×m) sub-slices may be configured, where m is greater than or equal to 1, instead of only two sub-slices provided the arrangement only allows one full segment to be loaded per sub-slice. For another embodiment, the segment size may be resized arbitrarily to shorten or lengthen the time required to load a segment. For other embodiments, more than one physical data bus may be used to load data into the microdisplay array, and a number of simultaneous segment loads equal to the number of data busses can occur.
For another embodiment, the display time for the lowest bit level data can be arbitrarily assigned to be multiple time slices long, and the display times for higher bit levels of data can be scaled accordingly. That is, the display time for the least significant binary bit may be represented by more than one time slice. The number of time slices per binary weighted display times of other bits scale respectively. For example, if the least significant bit, or bit 0, is displayed for two time slices, bit 1 would be displayed for 4 time slices, bit 2 for 8 time slices, and so on.
Although specific embodiments have been illustrated and described herein it is manifestly intended that the scope of the claimed subject matter be limited only by the following claims and equivalents thereof.
This application is a Continuation-in-Part of U.S. application Ser. No. 10/734,685, filed Dec. 12, 2003, which application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10734685 | Dec 2003 | US |
| Child | 11129995 | May 2005 | US |
