Patent Application
20250104630
This application claims priority to Korean Patent Application No. 10-2023-0126543, filed on Sep. 21, 2023, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.
Embodiments of the invention relate to a display device, and more particularly to a pixel and a display device including the pixel.
Driving transistors of pixels of a display device, such as an organic light emitting diode (OLED) display device, may have different threshold voltages due to a process variation, a degradation, etc. Because of this threshold voltage variation, the pixels of the display device may not emit light with uniform luminance. To prevent or reduce the luminance non-uniformity, a pixel for performing a compensation operation that compensates for a threshold voltage of a driving transistor has been developed. For example, to perform the compensation operation in a diode connection method, the pixel may diode-connect a driving transistor, and may transfer a data voltage to a gate node of the driving transistor through the diode-connected driving transistor. Thus, in the pixel, the data voltage in which a threshold voltage of the driving transistor is compensated may be applied to the gate node.
In the pixel performing the compensation operation in the diode connection method, the gate node may be initialized to an initialization voltage lower than the data voltage before the data voltage is applied to the gate node. The pixel may receive an initialization signal to provide the initialization voltage to the gate node.
Some embodiments provide a pixel of a display device that performs a compensation operation without using an initialization signal.
Some embodiments provide a display device that performs a compensation operation without using an initialization signal.
According to embodiments, a pixel of a display device includes a capacitor connected between a line, which transfers a first power supply voltage, and a first node, a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node, a second transistor including a gate which receives a scan signal, a first terminal connected to a data line, and a second terminal connected to a second node, a third transistor including a gate which receives the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node, a fourth transistor including a gate connected to the second node, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the first node, and a light emitting element including an anode connected to the third node, and a cathode connected to a line which transfers a second power supply voltage.
In embodiments, the fourth transistor may be turned on in response to a reference voltage transferred to the second node through the data line and the second transistor.
In embodiments, the initialization voltage may be higher than the reference voltage.
In embodiments, the fourth transistor may be turned off in response to a data voltage transferred to the second node through the data line and the second transistor.
In embodiments, the initialization voltage may be lower than the data voltage.
In embodiments, the pixel may further include a fifth transistor connected between the line, which transfers the first power supply voltage, and the second node, where the fifth transistor may receive an emission signal, and a sixth transistor connected between the third node and the anode of the light emitting element, where the sixth transistor may receive the emission signal.
In embodiments, the fifth transistor may include a gate which receives the emission signal, a first terminal connected to the line which transfers the first power supply voltage, and a second terminal connected to the second node, and the sixth transistor may include a gate which receives the emission signal, a first terminal connected to the third node, and a second terminal connected to the anode of the light emitting element.
In embodiments, the first through sixth transistors may be P-type metal oxide semiconductor (PMOS) transistors.
In embodiments, a frame period for the pixel may include an initialization period in which the first node and the third node are initialized, a data writing and compensation period in which a data voltage is provided through the data line, and an emission period in which the light emitting element emits light.
In embodiments, in the initialization period, the scan signal may have a first level, the emission signal may have a second level, a reference voltage may be provided through the data line, the second transistor may transfer the reference voltage of the data line to the second node in response to the scan signal having the first level, the fourth transistor may transfer the initialization voltage to the first node in response to the reference voltage of the second node, the third transistor may transfer the initialization voltage of the first node to the third node in response to the scan signal having the first level, and the first node and the third node may be initialized based on the initialization voltage.
In embodiments, in the data writing and compensation period, the scan signal may have a first level, the emission signal may have a second level, a data voltage may be provided through the data line, the second transistor may transfer the data voltage of the data line to the second node in response to the scan signal having the first level, the third transistor may diode-connect the first transistor in response to the scan signal having the first level, and a voltage obtained by subtracting a threshold voltage of the first transistor from the data voltage may be applied to the first node through the diode-connected first transistor.
In embodiments, in the emission period, the scan signal may have a second level, the emission signal may have a first level, the fifth transistor and the sixth transistor may be turned on in response to the emission signal having the first level, the first transistor may generate a driving current based on a voltage of the first node, and the light emitting element may emit light based on the driving current.
In embodiments, the pixel may further include a seventh transistor configured to transfer an anode initialization voltage to the anode of the light emitting element in response to the scan signal.
In embodiments, the seventh transistor may include a gate which receives the scan signal, a first terminal connected to a line which transfers the anode initialization voltage, and a second terminal connected to the anode of the light emitting element.
In embodiments, the anode initialization voltage may be equal to the initialization voltage.
In embodiments, the anode initialization voltage may be different from the initialization voltage.
According to embodiments, a pixel of a display device includes a capacitor connected between a line, which transfers a first power supply voltage, and a first node, a first transistor including a gate connected to the first node, a first terminal connected to a second node, and a second terminal connected to a third node, a second transistor including a gate which receives a scan signal, a first terminal connected to a data line, and a second terminal connected to the second node, a third transistor including a gate which receives the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node, a fourth transistor including a gate connected to the second node, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the first node, a fifth transistor including a gate which receives an emission signal, a first terminal connected to the line which transfers the first power supply voltage, and a second terminal connected to the second node, a sixth transistor including a gate which receives the emission signal, a first terminal connected to the third node, and a second terminal, and a light emitting element including an anode connected to the second terminal of the sixth transistor, and a cathode connected to a line which transfers a second power supply voltage.
In embodiments, the pixel may further include a seventh transistor including includes a gate which receives the scan signal, a first terminal connected to a line which transfers an anode initialization voltage, and a second terminal connected to the anode of the light emitting element.
According to embodiments, a display device includes a display panel including a plurality of pixels, a data driver connected to each of the plurality of pixels through a data line, and a scan driver which provides a scan signal to each of the plurality of pixels. Each of the plurality of pixels includes a capacitor connected between a line, which transfers a first power supply voltage, and a first node, a first transistor including a gate connected to the first node, a first terminal connected to the second node, and a second terminal connected to a third node, a second transistor including a gate which receives the scan signal, a first terminal connected to the data line, and a second terminal connected to the second node, a third transistor including a gate which receives the scan signal, a first terminal connected to the third node, and a second terminal connected to the first node, a fourth transistor including a gate connected to the second node, a first terminal connected to a line which transfers an initialization voltage, and a second terminal connected to the first node, and a light emitting element including an anode connected to the third node, and a cathode connected to a line which transfers a second power supply voltage.
In embodiments, while the scan signal is applied and a reference voltage is provided to the data line, the fourth transistor may be turned on in response to the reference voltage transferred to the second node through the data line and the second transistor. While the scan signal is applied and a data voltage is provided to the data line, the fourth transistor may be turned off in response to the data voltage transferred to the second node through the data line and the second transistor.
As described above, in a pixel of a display device according to embodiments, a gate of a fourth transistor may be connected to a second node. In such embodiments, the fourth transistor may be turned on in response to a reference voltage applied to the second node through a data line and a second transistor, and may be turned off in response to a data voltage applied to the second node through the data line and the second transistor. Accordingly, the pixel according to embodiments may be implemented without using a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor, and the number of signal lines of the display device may be reduced.
Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. Thus, reference to “an” element in a claim followed by reference to “the” element is inclusive of one element and a plurality of the elements. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within +30%, 20%, 10% or 5% of the stated value.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.
Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings.
Referring to
In an embodiment, the capacitor CST may be connected between a line that transfers a first power supply voltage ELVDD (e.g., a high power supply voltage) and a first node N1. The first node N1 may be a gate node connected to a gate (e.g., a gate terminal) of the first transistor T1. In embodiments, the capacitor CST may be referred to as a storage capacitor for storing a data voltage. In an embodiment, the capacitor CST may include a first electrode connected to the line that transfers the first power supply voltage ELVDD, and a second electrode connected to the first node N1.
The first transistor T1 may generate a driving current based on a voltage of the first node N1. In embodiments, the first transistor T1 may be referred to as a driving transistor for driving the light emitting element EL. In an embodiment, the first transistor T1 may include a gate connected to the first node N1, a first terminal (e.g., a source) connected to a second node N2, and a second terminal (e.g., a drain) connected to a third node N3.
The second transistor T2 may connect a data line DL to the second node N2 in response to a scan signal GW. The second node N2 may be a source node connected to the source of the first transistor T1. In embodiments, the second transistor T2 may be referred to as a scan transistor or a switching transistor that transfers a voltage of the data line DL to the second node N2. In an embodiment, the second transistor T2 may include a gate that receives the scan signal GW, a first terminal connected to the data line DL, and a second terminal connected to the second node N2.
The third transistor T3 may connect the first node N1 and the third node N3 to each other in response to the scan signal GW. The third node N3 may be a drain node connected to the drain of the first transistor T1. In an embodiment, the gate node and the drain node are connected to each other via the third transistor T3, and thus the first transistor T1 may be diode-connected or connected in a diode form. In embodiments, the third transistor T3 may be referred to as a compensation transistor for diode-connecting the first transistor T1, i.e., connection the first transistor T1 in a diode form. In an embodiment, the third transistor T3 may include a gate that receives the scan signal GW, a first terminal connected to the third node N3, and a second terminal connected to the first node N1.
The fourth transistor T4 may transfer an initialization voltage VINT to the first node N1 in response to a voltage of the second node N2. In embodiments, the fourth transistor T4 may be referred to as an initialization transistor for providing the initialization voltage VINT to the first node N1, or the gate node. In an embodiment, the fourth transistor T4 may include a gate connected to the second node N2, a first terminal connected to a line that transfers the initialization voltage VINT, and a second terminal connected to the first node N1.
The fifth transistor T5 may be connected between the line that transfers the first power supply voltage ELVDD and the second node N2, and the sixth transistor T6 may be connected between the third node N3 and an anode of the light emitting element EL. The fifth transistor T5 and the sixth transistor T6 may receive a same emission signal EM as each other. In response to the emission signal EM, the fifth transistor T5 may connect the line that transfers the first power supply voltage ELVDD and the second node N2 to each other, and the sixth transistor T6 may connect the third node N3 and the anode of the light emitting element EL to each other. In embodiments, the fifth transistor T5 and the sixth transistor T6 may be referred to as emission transistors for forming a path of the driving current from the line that transfers the first power supply voltage ELVDD to a line that transfers a second power supply voltage ELVSS (e.g., a low power supply voltage). In an embodiment, the fifth transistor T5 may include a gate that receives the emission signal EM, a first terminal connected to the line that transfers the first power supply voltage ELVDD, and a second terminal connected to the second node N2, and the sixth transistor T6 may include a gate that receives the emission signal EM, a first terminal connected to the third node N3, and a second terminal connected to the anode of the light emitting element EL.
The light emitting element EL may emit light in response to the driving current generated by the first transistor T1. In embodiments, the light emitting element EL may be an organic light emitting diode (OLED), but is not limited thereto. In another embodiment, for example, the light emitting element EL may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro-light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In an embodiment, the light emitting element EL may include the anode connected to the third node N3 through the sixth transistor T6, and a cathode connected to the line that transfers the second power supply voltage ELVSS.
In some embodiments, as illustrated in
As described above, in the pixel 100 of the display device according to embodiments, the gate of the fourth transistor T4 may be connected to the second node N2. Thus, the fourth transistor T4 may not receive a separate signal (e.g., an initialization signal), and may be turned on or off in response to the voltage of the second node N2. In some embodiments, the fourth transistor T4 may be turned on in response to a reference voltage applied to the second node N2 through the data line DL and the second transistor T2, and may be turned off in response to the data voltage applied to the second node N2 through the data line DL and the second transistor T2. Accordingly, the pixel 100 according to embodiments may be implemented without using the separate signal (e.g., the initialization signal) for turning on or off the fourth transistor T4, and the number of signal lines of the display device including the pixel 100 may be reduced.
Hereinafter, an operation of the pixel 100 according to embodiments will be described with reference to
Referring to
In the initialization period INIP, the scan signal GW may have a first level, the emission signal EM may have a second level, and the reference voltage VREF may be provided through the data line DL. In some embodiments, the first level may be an active level for turning on each transistor, and the second level may be an inactive level for turning off each transistor. In an embodiment, for example, as illustrated in
In the initialization period INIP, the fourth transistor T4 that is turned on in response to the reference voltage VREF at the second node N2 may transfer the initialization voltage VINT to the first node N1. Since the initialization voltage VINT applied to the first node N1 is higher than the reference voltage VREF applied to the second node N2, the first transistor T1 may be turned off. In addition, the third transistor T3 may be turned on in response to the scan signal GW having the first level, and may transfer the initialization voltage VINT at the first node N1 to the third node N3. Accordingly, the first node N1 and the third node N3 may be initialized based on the initialization voltage VINT. Since the first node N1 (e.g., a gate node) is initialized to the initialization voltage VINT, a compensation operation in a diode connection method may be normally performed in the data writing and compensation period DWCP. Further, since the third node N3 (e.g., a drain node) is initialized to the initialization voltage VINT, residual charges remaining at the drain node may be discharged or removed.
In the data writing and compensation period DWCP, the scan signal GW may have the first level, the emission signal EM may have the second level, and the data voltage VDAT may be provided through the data line DL. In an embodiment, as illustrated in
In the data writing and compensation period DWCP, the third transistor T3 may be turned on in response to the scan signal GW having the first level, and may diode-connect the first transistor T1. Since the data voltage VDAT of the second node N2 is applied to the first node N1 through the diode-connected first transistor T1, a voltage (VDAT-VTH) obtained by subtracting a threshold voltage (VTH) of the first transistor T1 from the data voltage VDAT may be applied to the first node N1. This operation may be referred to as a compensation operation in a diode connection method. Further, the storage capacitor CST may store the voltage VDAT-VTH at the first node N1.
In the emission period EMP, the scan signal GW may have the second level, and the emission signal EM may have the first level. In an embodiment, as illustrated in
As described above, in the pixel 100 of the display device according to embodiments, since the fourth transistor T4 is be turned on and off based on the reference voltage VREF and the data voltage VDAT provided through the data line DL, the display device including the pixel 100 may be implemented without using a separate signal (e.g., an initialization signal). That is, the pixel 100 may be driven using only two signals GW and EM, and the number of signal lines of the display device including the pixel 100 may be reduced.
Referring to
The seventh transistor T7 may transfer an anode initialization voltage AVINT to an anode of the light emitting element EL in response to a scan signal GW. In some embodiments, in an initialization period INIP and a data writing and compensation period DWCP illustrated in
In some embodiments, the anode initialization voltage AVINT may be substantially the same as an initialization voltage VINT, and the line that transfers the anode initialization voltage AVINT and a line that transfers the initialization voltage VINT may be the same line. In other embodiments, the anode initialization voltage AVINT may be different from the initialization voltage VINT, and the line that transfers the anode initialization voltage AVINT may be different from the line that transfers the initialization voltage VINT.
Referring to
The display panel 610 may include the plurality of pixels PX. According to embodiments, each pixel PX of the display panel 610 may be a pixel 100 of
The data driver 620 may generate the reference voltage VREF and the data voltages VDAT based on output image data ODAT and a data control signal DCTRL received from the controller 650, and may provide the reference voltage VREF and the data voltages VDAT to the plurality of pixels PX. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some embodiments, the data driver 620 may alternately provide the reference voltage VREF and the data voltage (VDAT) to each data line. Further, in each horizontal time, the data driver 620 may sequentially output the reference voltage VREF and the data voltage VDAT to each data line. In an embodiment, for example, as illustrated in
The scan driver 630 may provide the scan signals GW1, GW2, GW3, . . . to the plurality of pixels PX based on a scan control signal SCTRL received from the controller 650. The scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In an embodiment, as illustrated in
The emission driver 640 may provide the emission signals EM1, EM2, EM3, . . . to the plurality of pixels PX based on an emission control signal EMCTRL received from the controller 650. The emission control signal EMCTRL may include, but is not limited to, an emission start signal and an emission clock signal. In an embodiment, as illustrated in
The controller 650 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a master clock signal. The controller 650 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal SCTRL and the emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 650 may control the data driver 620 by providing the output image data ODAT and the data control signal DCTRL to the data driver 620, may control the scan driver 630 by providing the scan control signal SCTRL to the scan driver 630, and may control the emission driver 640 by providing the emission control signal EMCTRL to the emission driver 640.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in some embodiments, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (PCI) bus.
The memory device 1120 may store data for operations of the electronic device 1100. In an embodiment, for example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.
The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100. The display device 1160 may be coupled to other components through the buses or other communication links.
In the display device 1160, a gate of a fourth transistor of each pixel may be connected to a second node. Further, the fourth transistor may be turned on in response to a reference voltage applied to the second node through a data line and a second transistor, and may be turned off in response to a data voltage applied to the second node through the data line and the second transistor. Accordingly, the display device 1160 may be implemented without using a separate signal (e.g., an initialization signal) for turning on or off the fourth transistor, and the number of signal lines of the display device 1160 may be reduced.
Embodiments of the inventions may be applied to any display device 1160 and any electronic device 1100 including the display device 1160, for example, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV) (e.g., a digital TV, a three-dimensional (3D) TV, etc.), a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.
The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.
While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0126543 | Sep 2023 | KR | national |
