Patent Grant
11955081
This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0110004, filed on Sep. 5, 2019 in the Korean Intellectual Property Office (KIPO), the entire content of which is incorporated herein by reference.
Aspects of example embodiments of the present inventive concept relate to a display device, and more particularly, to a pixel of an organic light emitting diode display device, and the organic light emitting diode display device.
Reduction of power consumption may be desirable in an organic light emitting diode (OLED) display device that is employed in a portable device, such as a smartphone, a tablet computer, and the like. Recently, in order to reduce the power consumption of the OLED display device, a low frequency driving technique, which decreases a driving frequency when displaying a still image, has been developed. For example, when performing low frequency driving, the OLED display device may not drive a display panel at one or more frames, and the display panel may display an image based on stored data signals, thereby reducing the power consumption.
However, while the display panel displays an image based on the stored data signals, the stored data signals may be distorted by leakage currents of transistors included in pixels of the display panel, and thus, an image quality of the OLED display device may be degraded.
The above information disclosed in this Background section is for enhancement of understanding of the background of the inventive concept, and therefore, it may contain information that does not constitute prior art.
One or more example embodiments of the present inventive concept are directed to a pixel of an organic light emitting diode display device that is capable of preventing or reducing an image quality degradation at low frequency driving.
One or more example embodiments of the present inventive concept are directed to an organic light emitting diode display device capable of preventing or reducing an image quality degradation at low frequency driving.
According to one or more example embodiments of the present inventive concept, a pixel of an organic light emitting diode display device, includes: a storage capacitor including a first electrode connected to a line of a first power supply voltage, and a second electrode connected to a gate node; a first transistor including a gate electrode connected to the gate node; a second transistor configured to transfer a data signal to a source of the first transistor in response to a scan signal; a third transistor configured to diode-connect the first transistor in response to the scan signal, the third transistor including first and second sub-transistors serially connected between the gate node and a drain of the first transistor; a fourth transistor configured to transfer an initialization voltage to the gate node in response to an initialization signal, the fourth transistor including third and fourth sub-transistors serially connected between the gate node and a line of the initialization voltage; and an organic light emitting diode comprising an anode, and a cathode connected to a line of a second power supply voltage. At least one of the second sub-transistor and the fourth sub-transistor includes a bottom electrode.
In an example embodiment, the fourth transistor may include: a first gate electrode of the third sub-transistor configured to receive the initialization signal; a first source of the third sub-transistor connected to the gate node; a second gate electrode of the fourth sub-transistor configured to receive the initialization signal; a second drain of the fourth sub-transistor connected to the line of the initialization voltage; a node of the fourth transistor configured as a first drain of the third sub-transistor and a second source of the fourth sub-transistor; and the bottom electrode located under the second gate electrode of the fourth sub-transistor.
In an example embodiment, the bottom electrode of the fourth transistor may be configured to receive a bottom electrode voltage during a masking period in which a display panel of the organic light emitting diode display device is not driven.
In an example embodiment, the bottom electrode voltage may have a positive voltage level during the masking period.
In an example embodiment, an off-current of the fourth sub-transistor may be increased according to the bottom electrode voltage having the positive voltage level, and the off-current of the fourth sub-transistor may flow from the node of the fourth transistor to the line of the initialization voltage during the masking period.
In an example embodiment, the bottom electrode voltage may have a negative voltage level during the masking period.
In an example embodiment, the fourth sub-transistor may be configured to turned on according to the bottom electrode voltage having the negative voltage level, and an on-current of the fourth sub-transistor may flow from the node of the fourth transistor to the line of the initialization voltage.
In an example embodiment, the third transistor may include: a first gate electrode of the first sub-transistor configured to receive the scan signal; a first source of the first sub-transistor connected to the gate node; a second gate electrode of the second sub-transistor configured to receive the scan signal; a second drain of the second sub-transistor connected to the drain of the first transistor; a node of the third transistor configured as a first drain of the first sub-transistor and a second source of the second sub-transistor; and the bottom electrode located under the second gate electrode of the second sub-transistor.
In an example embodiment, the bottom electrode of the third transistor may be configured to receive a bottom electrode voltage during a masking period in which a display panel of the organic light emitting diode display device is not driven.
In an example embodiment, the bottom electrode voltage may have a positive voltage level during the masking period.
In an example embodiment, an off-current of the second sub-transistor may be increased according to the bottom electrode voltage having the positive voltage level, and the off-current of the second sub-transistor may flow from the node of the third transistor to the drain of the first transistor during the masking period.
In an example embodiment, the bottom electrode voltage may have a negative voltage level during the masking period.
In an example embodiment, the second sub-transistor may be configured to turned on according to the bottom electrode voltage having the negative voltage level, and an on-current of the second sub-transistor may flow from the node of the third transistor to the drain of the first transistor.
In an example embodiment, each of the second sub-transistor and the fourth sub-transistor may include the bottom electrode.
In an example embodiment, the pixel may further include: a fifth transistor including a gate electrode configured to receive an emission signal, a source connected to the line of the first power supply voltage, and a drain connected to the source of the first transistor; a sixth transistor including a gate electrode configured to receive the emission signal, a source connected to the drain of the first transistor, and a drain connected to the anode of the organic light emitting diode; and a seventh transistor including a gate electrode configured to receive the initialization signal, a source connected to the anode of the organic light emitting diode, and a drain connected to the line of the initialization voltage.
According to one or more example embodiments of the present inventive concept, an organic light emitting diode (OLED) display device includes: a display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a scan driver configured to provide scan signals and initialization signals to the plurality of pixels; a power supply configured to provide a first power supply voltage, a second power supply voltage, and an initialization voltage to the plurality of pixels; and a controller configured to control the data driver, the scan driver, and the power supply. Each of the plurality of pixels includes: a storage capacitor including a first electrode connected to a line of the first power supply voltage, and a second electrode connected to a gate node; a first transistor including a gate electrode connected to the gate node; a second transistor configured to transfer a corresponding one of the data signals to a source of the first transistor in response to a corresponding one of the scan signals; a third transistor configured to diode-connect the first transistor in response to the corresponding one of the scan signals, the third transistor including first and second sub-transistors that are serially connected between the gate node and a drain of the first transistor; a fourth transistor configured to transfer the initialization voltage to the gate node in response to a corresponding one of the initialization signals, the fourth transistor including third and fourth sub-transistors that are serially connected between the gate node and a line of the initialization voltage; and an organic light emitting diode including an anode, and a cathode connected to a line of the second power supply voltage. At least one of the second sub-transistor and the fourth sub-transistor includes a bottom electrode.
In an example embodiment, the controller may include: a still image detector configured to receive input image data at an input frame frequency, and to determine whether the input image data represents a still image, and when the input image data represents the still image, the controller may be configured to set at least one frame period as a masking period to drive the display panel at a driving frequency lower than the input frame frequency.
In an example embodiment, the data driver may be configured to not provide the data signals to the plurality of pixels during the masking period, the scan driver may be configured to not provide the scan signals to the plurality of pixels during the masking period, and the power supply may be configured to provide a bottom electrode voltage to the bottom electrode of each of the plurality of pixels during the masking period.
In an example embodiment, the controller may include: a still image detector configured to receive input image data at an input frame frequency, to divide the input image data into a plurality of partial image data, and to determine whether each of the plurality of partial image data represents a still image. When at least one partial image data of the plurality of partial image data represents the still image, the controller may be configured to set a portion of a frame period corresponding to a portion of the display panel as a masking period to drive the portion of the display panel corresponding to the at least one partial image data at a driving frequency lower than the input frame frequency. The power supply may be configured to provide a bottom electrode voltage to the bottom electrode of each of the plurality of pixels during the masking period.
In an example embodiment, the display panel may include a plurality of regions, and the power supply may be configured to provide different bottom electrode voltages to the plurality of regions during a masking period.
According to one or more example embodiments of the present inventive concept, a third transistor (e.g., a threshold voltage compensating transistor) of a pixel may include first and second sub-transistors that are serially connected between a gate node and a drain of a first transistor of the pixel, a fourth transistor (e.g., a gate initializing transistor) of the pixel may include third and fourth sub-transistors that are serially connected between the gate node and a line of an initialization voltage, and at least one from among the second sub-transistor and the fourth sub-transistor may include a bottom electrode. In some example embodiments, the bottom electrode may receive a bottom electrode voltage that is a positive voltage or a negative voltage during a masking period in which a display panel is not driven. Accordingly, a voltage distortion of the gate node at low frequency driving may be compensated, and an image quality of the organic light emitting diode display device may be improved.
The above and other aspects and features of the present inventive concept will become more apparent to those skilled in the art from the following detailed description of the example embodiments with reference to the accompanying drawings.
Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. The present inventive concept, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the inventive concept to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the inventive concept may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof may not be repeated.
In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the inventive concept.
It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the inventive concept.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Also, the term “exemplary” is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
Referring to
The storage capacitor CST may store a data signal DS transferred through the second transistor T2 and the first transistor T1, which may be diode-connected (e.g., by the third transistor T3) as described below. In some example embodiments, the storage capacitor CST may have a first electrode connected to a line of a first power supply voltage ELVDD, and a second electrode connected to a gate node NG.
The first transistor T1 may generate a driving current according to (e.g., based on) the data signal DS stored in the storage capacitor CST (e.g., or a voltage of the gate node NG). The first transistor T1 may be referred to as a driving transistor. In some example embodiments, the first transistor T1 may have a gate electrode connected to the second electrode of the storage capacitor CST (e.g., at the gate node NG), a source connected to the line of the first power supply voltage ELVDD, and a drain connected to a source of the sixth transistor T6.
The second transistor T2 may transfer the data signal DS to the source of the first transistor T1 in response to a scan signal SS. The second transistor T2 may be referred to as a switching transistor or a scan transistor. In some example embodiments, the second transistor T2 may have a gate electrode for receiving the scan signal SS, a source for receiving the data signal DS, and a drain connected to the source of the first transistor T1.
The third transistor T3 may diode-connect the first transistor T1 in response to the scan signal SS. The third transistor T3 may be referred to as a threshold voltage compensating transistor. In some example embodiments, the third transistor T3 may have a gate electrode for receiving the scan signal SS, a drain (e.g., a second drain of a second sub-transistor T3-2) connected to the drain of the first transistor T1, and a source (e.g., a first source of a first sub-transistor T3-1) connected to the gate electrode of the first transistor T1 (e.g., at the gate node NG). While the scan signal SS is applied, the data signal DS transferred by the second transistor T2 may be stored in the storage capacitor CST through the first transistor T1 that is diode-connected by the third transistor T3. Accordingly, the storage capacitor CST may store the data signal DS where a threshold voltage of the first transistor T1 is compensated.
The fourth transistor T4 may transfer an initialization voltage VINIT to the gate node NG in response to an initialization signal SI. The fourth transistor T4 may be referred to as a gate initializing transistor. In some example embodiments, the fourth transistor T4 may include a gate electrode for receiving the initialization signal SI, a source (e.g., a first source of a third sub-transistor T4-1) connected to the gate node NG, and a drain (e.g., a second drain of a fourth sub-transistor T4-2) connected to a line of the initialization voltage VINIT. While the initialization signal SI is applied, the fourth transistor T4 may initialize the gate node NG (e.g., the storage capacitor CST and the gate electrode of the first transistor T1) by using the initialization voltage VINIT.
The fifth transistor T5 may connect the line of the first power supply voltage ELVDD to the source of the first transistor T1 in response to an emission signal SEM. The fifth transistor T5 may be referred to as a first emission transistor. In some example embodiments, the fifth transistor T5 may include a gate electrode for receiving the emission signal SEM, a source connected to the line of the first power supply voltage ELVDD, and a drain connected to the source of the first transistor T1.
The sixth transistor T6 may connect the drain of the first transistor T1 to an anode of the organic light emitting diode EL in response to the emission signal SEM. The sixth transistor T6 may be referred to as a second emission transistor. In some example embodiments, the sixth transistor T6 may include a gate electrode for receiving the emission signal SEM, a source connected to the drain of the first transistor T1, and a drain connected to the anode of the organic light emitting diode EL. While the emission signal SEM is applied, the fifth and sixth transistors T5 and T6 may be turned on, and a path of the driving current from the line of the first power supply voltage ELVDD to a line of a second power supply voltage ELVSS may be formed.
The seventh transistor T7 may transfer the initialization voltage VINIT to the anode of the organic light emitting diode EL in response to the initialization signal SI. The seventh transistor T7 may be referred to as a diode initializing transistor. In some example embodiments, the seventh transistor T7 may include a gate electrode for receiving the initialization signal SI, a source connected to the anode of the organic light emitting diode EL, and a drain connected to the line of the initialization voltage VINIT. While the initialization signal SI is applied, the seventh transistor T7 may initialize the organic light emitting diode EL by using the initialization voltage VINIT.
The organic light emitting diode EL may emit light according to (e.g., based on) the driving current generated by the first transistor T1. In some example embodiments, the organic light emitting diode EL may have the anode connected to the drain of the sixth transistor T6, and a cathode connected to the line of the second power supply voltage ELVSS. While the emission signal SEM is applied, the driving current generated by the first transistor T1 may be provided to the organic light emitting diode EL, and the organic light emitting diode EL may emit light according to (e.g., based on) the driving current.
To reduce power consumption, the organic light emitting diode display device including the pixel 100 may perform low frequency driving, for example, when a still image is displayed. When the low frequency driving is performed, each pixel 100 may not receive the initialization signal SI, the scan signal SS, and the data signal DS during at least a portion of a plurality of frame periods, and may emit light according to (e.g., based on) the data signal DS that is stored in the storage capacitor CST during a previous frame period. In this case, the data signal DS stored in the storage capacitor CST (e.g., or a voltage of the gate node NG) may be distorted by a leakage current of the transistors T1 through T7 of the pixel 100 (e.g., by a leakage current of the third and fourth transistors T3 and T4), and thus, an image quality of the organic light emitting diode display device may be degraded.
In some example embodiments, to reduce the leakage current of the third and fourth transistors T3 and T4, each of the third and fourth transistors T3 and T4 may have a dual transistor structure. For example, as illustrated in
However, even if the third transistor T3 includes the first and second sub-transistors T3-1 and T3-2, a parasitic capacitor may be formed between a node NT3 of the third transistor T3 and a line (e.g., a line of the scan signal SS) of the pixel 100, and thus, a leakage current of the first sub-transistor T3-1 from the node NT3 of the third transistor T3 to the gate node NG may occur. Further, even if the fourth transistor T4 includes the third and fourth sub-transistors T4-1 and T4-2, a parasitic capacitor may be formed between a node NT4 of the fourth transistor T4 and a line (e.g., a line of the initialization signal SI) of the pixel 100, and thus, a leakage current of the third sub-transistor T4-1 from the node NT4 of the fourth transistor T4 to the gate node NG may occur. Accordingly, the voltage of the gate node NG may be increased, and the driving current of the first transistor T1 may be reduced, and thus, luminance of the organic light emitting diode EL may be reduced.
According to one or more example embodiments, to compensate for the voltage distortion of the gate node NG by the leakage currents of the first sub-transistor T3-1 and the third sub-transistor T4-1, the fourth sub-transistor T4-2 of the pixel 100 may include a bottom electrode 120. In some example embodiments, the bottom electrode 120 may be referred to as a bottom metal layer (BML).
In some example embodiments, as illustrated in
For example, as illustrated in
Further, for example, as illustrated in
In the pixel 100 of the organic light emitting diode display device according to one or more example embodiments, when the low frequency driving is performed, for example, during a masking period in which a display panel is not driven, the bottom electrode 120 of the fourth sub-transistor T4-2 may receive the bottom electrode voltage VBML through the bottom electrode voltage line LVBML. The bottom electrode 120 of the fourth sub-transistor T4-2 may provide an off-current IOFF or an on-current ION from the node NT4 of the fourth transistor T4 to the line LVINIT of the initialization voltage VINIT according to (e.g., based on) the bottom electrode voltage VBML. Accordingly, the leakage current from the node NT4 of the fourth transistor T4 to the gate node NG may be prevented or reduced, and the voltage distortion of the gate node NG may be compensated.
Referring to
In more detail, during the first frame period FP1, the pixel 100 may receive the emission signal SEM having an off level (e.g., a high level), and may sequentially receive the initialization signal SI and the scan signal SS (e.g., having an on level, such as a low level) while the emission signal SEM has the off level. While the initialization signal SI is received, the fourth and seventh transistors T4 and T7 may be turned on, the fourth transistor T4 may initialize the gate node NG by using the initialization voltage VINIT, and the seventh transistor T7 may initialize the organic light emitting diode EL by using the initialization voltage VINIT. A voltage V_NG of the gate node NG may become the same or substantially the same as the initialization voltage VINIT transferred through the fourth transistor T4. While the scan signal SS is received, a data voltage VD may be applied to the pixel 100 as the data signal DS, and the second and third transistors T2 and T3 may be turned on. The second transistor T2 may transfer the data voltage VD to the source of the first transistor T1, and the third transistor T3 may diode-connect the first transistor T1. In this case, the data voltage VD may be transferred to the gate node NG through the diode-connected first transistor T1. Because the data voltage VD is transferred through the diode-connected first transistor T1, the voltage V_NG of the gate node NG may become a voltage VD-VTH corresponding to a difference between the data voltage VD and the threshold voltage VTH of the first transistor T1 (e.g., a voltage resulting from the threshold voltage VTH of the first transistor T1 subtracted from the data voltage VD).
When the emission signal SEM is changed from the off level (e.g., the high level) to an on level (e.g., a low level), the fifth and sixth transistors T5 and T6 may be turned on, the first transistor T1 may generate a driving current according to (e.g., based on) the voltage V_NG of the gate node NG (e.g., the voltage VD-VTH corresponding to the difference between the data voltage VD and the threshold voltage VTH of the first transistor T1), and the organic light emitting diode EL may emit light according to (e.g., based on) the driving current. Further, when the emission signal SEM is changed from the off level to the on level, the scan signal SS and the initialization signal SI are applied with an off level (e.g., a high level) to turn off the third and fourth transistor T3 and T4. While the third and fourth transistors T3 and T4 are turned off in response to the scan signal SS and the initialization signal SI having the off level, leakage currents of the third and fourth transistors T3 and T4 may flow to the gate node NG, and the voltage V_NG of the gate node NG may be increased. Thus, the driving current may be reduced according to (e.g., based on) the increased voltage V_NG of the gate node NG.
Further, in a case where a bottom electrode voltage VBML is not applied to a bottom electrode 120, during the masking period MP in which a display panel is not driven, for example, during the second and third frame periods FP2 and FP3, the voltage V_NG of the gate node NG may be further increased as illustrated as a dashed line 210 of
However, in the pixel 100 according to one or more example embodiments, the bottom electrode 120 of the fourth sub-transistor T4-2 of the fourth transistor T4 may receive the bottom electrode voltage VBML during the masking period MP in which the display panel of the organic light emitting diode display device is not driven. Further, in some example embodiments, the bottom electrode voltage VBML may have a positive voltage level during the masking period MP. For example, the bottom electrode voltage VBML may be in a range from about 5V to about 8V, but the present inventive concept is not limited thereto. The bottom electrode voltage VBML may serve as a body voltage of the fourth sub-transistor T4-2, and thus, an off-current IOFF of the fourth sub-transistor T4-2 may be increased according to (e.g., based on) the bottom electrode voltage VBML having the positive voltage level. Accordingly, during the masking period MP (e.g., during the second and third frame periods FP2 and FP3), the off-current IOFF of the fourth sub-transistor T4-2 may flow from the node NT4 of the fourth transistor T4 to the line of the initialization voltage VINIT, and a voltage of the node NT4 of the fourth transistor T4 may be decreased. Accordingly, the voltage V_NG of the gate node NG may also be decreased as illustrated as a solid line 220 of
Referring to
In some example embodiments, as illustrated in
Referring to
In the pixel 200 of the organic light emitting diode display device according to one or more example embodiments, to compensate a voltage distortion of the gate node NG by leakage currents of the first sub-transistor T3-1 and the third sub-transistor T4-1, the second sub-transistor T3-2 may include the bottom electrode 240.
In some example embodiments, similar to the fourth transistor T4 illustrated in
Further, for example, as illustrated in
In the pixel 200 of the organic light emitting diode display device according to example embodiments, when low frequency driving is performed, for example, during a masking period in which a display panel is not driven, the bottom electrode 220 of the second sub-transistor T3-2 may receive the bottom electrode voltage VBML through the bottom electrode voltage line LVBML. The bottom electrode 220 may provide an off-current IOFF or an on-current ION from the node NT3 of the third transistor T3 to the drain of the first transistor T1 according to (e.g., based on) the bottom electrode voltage VBML.
In some example embodiments, the bottom electrode voltage VBML may have a positive voltage level during the masking period. For example, the bottom electrode voltage VBML may be in a range from about 5V to about 8V, but the present inventive concept is not limited thereto. The bottom electrode voltage VBML may serve as a body voltage of the second sub-transistor T3-2, and thus, an off-current IOFF of the second sub-transistor T3-2 may be increased according to (e.g., based on) the bottom electrode voltage VBML having the positive voltage level. Accordingly, during the masking period, the off-current IOFF of the second sub-transistor T3-2 may flow from the node NT3 of the third transistor T3 to the drain of the first transistor T1, a voltage of the node NT3 of the third transistor T3 may be decreased, and thus, a voltage of the gate node NG also may be decreased. Therefore, during the masking period, a distortion of the voltage of the gate node NG may be compensated, a luminance degradation of the pixel 200 may be compensated, and thus, an image quality of the organic light emitting diode display device may be improved.
In other example embodiments, the bottom electrode voltage VBML may have a negative voltage level during the masking period. For example, the bottom electrode voltage VBML may be in a range from about −5V to about −8V, but the present inventive concept is not limited thereto. The bottom electrode voltage VBML may serve as a body voltage of the second sub-transistor T3-2, and thus, the second sub-transistor T3-2 may be turned on according to (e.g., based on) the bottom electrode voltage VBML having the negative voltage level. Accordingly, during the masking period, an on-current ION of the second sub-transistor T3-2 may flow from the node NT3 of the third transistor T3 to the drain of the first transistor T1, the voltage of the node NT3 of the third transistor T3 may be decreased, and thus, the voltage V_NG of the gate node NG may also be decreased. Therefore, during the masking period, the distortion of the voltage V_NG of the gate node NG may be compensated, the luminance degradation of the pixel 200 may be compensated, and thus, the image quality of the organic light emitting diode display device may be improved.
Referring to
In the pixel 300 of the organic light emitting diode display device according to one or more example embodiments, to compensate a voltage distortion of the gate node NG by leakage currents of the first sub-transistor T3-1 and the third sub-transistor T4-1, the second sub-transistor T3-2 may include the bottom electrode 340, and the fourth sub-transistor T4-2 may include the bottom electrode 320.
When low frequency driving is performed, for example, during a masking period in which a display panel is not driven, the bottom electrode 340 of the second sub-transistor T3-2 and the bottom electrode 320 of the fourth sub-transistor T4-2 may receive a bottom electrode voltage VBML, and may compensate a voltage distortion of the gate node NG according to (e.g., based on) the bottom electrode voltage VBML. In some example embodiments, the bottom electrode voltage VBML may have a positive voltage level during the masking period. In this case, off-currents IOFF of the second sub-transistor T3-2 and the fourth sub-transistor T4-2 may be increased, and thus, the voltage distortion of the gate node NG may be compensated during the masking period. In other example embodiments, the bottom electrode voltage VBML may have a negative voltage level during the masking period. In this case, on-currents ION of the second sub-transistor T3-2 and the fourth sub-transistor T4-2 may be generated, and thus, the voltage distortion of the gate node NG may be compensated during the masking period.
Referring to
The display panel 410 may include a plurality of data signal lines, a plurality of scan signal lines, a plurality of initialization signal lines, a plurality of emission signal lines, and the plurality of pixels PX connected to the signal lines. According to one or more example embodiments, each pixel PX may be the same or substantially the same as the pixel 100 of
The data driver 420 may generate the data signals DS according to (e.g., based on) a data control signal DCTRL and output image data ODAT received from the controller 460, and may provide the data signals DS to the plurality of pixels PX through the plurality of data signal lines. In some example embodiments, the data control signal DCTRL may include an output data enable signal ODE, a horizontal start signal, and a load signal, but the present inventive concept is not limited thereto. The data driver 420 may receive the output image data ODAT at an output frame frequency OFF from the controller 460. In some example embodiments, the data driver 420 may receive the output image data ODAT at the output frame frequency OFF that is the same or substantially the same as an input frame frequency IFF when a moving image is displayed, and may receive the output image data ODAT at the output frame frequency OFF that is lower than the input frame frequency IFF when a still image is displayed. Further, the data driver 420 may receive the output data enable signal ODE in synchronization with the output image data ODAT. In some example embodiments, the data driver 420 and the controller 460 may be implemented with a signal integrated circuit, and the signal integrated circuit may be referred to as a timing controller embedded data driver (TED). In other example embodiments, the data driver 420 and the controller 460 may be implemented with separate integrated circuits.
The scan driver 430 may generate the scan signals SS and the initialization signals SI according to (e.g., based on) a scan control signal SCTRL received from the controller 460, and may provide the scan signals SS and the initialization signals SI to the plurality of pixels PX through the plurality of scan signal lines and the plurality of initialization signal lines. In some example embodiments, the scan control signal SCTRL may include a scan start signal and a scan clock signal, but the present inventive concept is not limited thereto. In some example embodiments, the scan driver 430 may be integrated with or may be formed at (e.g., in or on) a peripheral portion of the display panel 410. In other example embodiments, the scan driver 430 may be implemented with one or more integrated circuits.
The emission driver 440 may generate the emission signals SEM according to (e.g., based on) an emission control signal EMCTRL received from the controller 460, and may provide the emission signals SEM to the plurality of pixels PX through the plurality of emission signal lines. In some example embodiments, the emission signals SEM may be sequentially provided to the plurality of pixels PX on a pixel row basis. In other example embodiments, the emission signals SEM may be a global signal that is concurrently (e.g., simultaneously or substantially simultaneously) provided to the plurality of pixels PX. In some example embodiments, the emission driver 440 may be integrated with or formed at (e.g., in or on) the peripheral portion of the display panel 410. In other example embodiments, the emission driver 440 may be implemented with one or more integrated circuits.
The power supply unit 450 may generate the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage VINIT, and may provide the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage VINIT to the plurality of pixels PX. Further, the power supply unit 450 may generate a bottom electrode voltage VBML during a masking period in which the display panel 410 is not driven according to (e.g., based on) a power control signal PCTRL, and may provide the bottom electrode voltage VBML to the plurality of pixels PX during the masking period. In some example embodiments, the bottom electrode voltage VBML may be a positive voltage, for example, in a range from about 5V to about 8V, but the present inventive concept is not limited thereto. In other example embodiments, the bottom electrode voltage VBML may be a negative voltage, for example, in a range from about −5V to about −8V, but the present inventive concept is not limited thereto. In some example embodiments, the power supply unit 450 may be implemented in the form of an integrated circuit, and the integrated circuit may be referred to as a power management integrated circuit (PMIC). In other example embodiments, the power supply unit 450 may be included in the controller 460 or in the data driver 420.
The controller (e.g., a timing controller (TCON)) 460 may receive input image data IDAT and a control signal CTRL from an external host (e.g., an application processor (AP), a graphic processing unit (GPU), a graphic card, and/or the like). In some example embodiments, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal IDE, a master clock signal, and/or the like, but the present inventive concept is not limited thereto. The controller 460 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal SCTRL, the emission control signal EMCTRL, and the power control signal PCTRL according to (e.g., based on) the input image data IDAT and the control signal CTRL. The controller 460 may control an operation of the data driver 420 by providing the output image data ODAT and the data control signal DCTRL to the data driver 420, an operation of the scan driver 430 by providing the scan control signal SCTRL to the scan driver 430, an operation of the emission driver 440 by providing the emission control signal EMCTRL to the emission driver 440, and an operation of the power supply unit 450 by providing the power control signal PCTRL to the power supply unit 450.
The organic light emitting diode display device 400 according to one or more example embodiments may detect whether the input image data IDAT represents a still image, and may set at least one frame period as the masking period when the input image data IDAT represents the still image. In this case, the organic light emitting diode display device 400 may perform low frequency driving to drive the display panel 410 at a driving frequency that is lower than the input frame frequency IFF by not driving the display panel 410 during the masking period. In some example embodiments, to perform the low frequency driving, the controller 460 of the organic light emitting diode display device 400 may include a still image detector 470.
The still image detector 470 may receive the input image data IDAT at the input frame frequency IFF, and may determine whether the input image data IDAT represents the still image. In some example embodiments, the still image detector 470 may determine whether the input image data IDAT represents the still image by comparing the input image data IDAT for a previous frame period with the input image data IDAT for a current frame period. For example, the still image detector 470 may store a representative value (e.g., an average value, a checksum, and/or the like) of the input image data IDAT for the previous frame period, may calculate a representative value of the input image data IDAT for the current frame period, and may compare the stored representative value (e.g., for the previous frame) with the calculated representative value (e.g., for the current frame) to determine whether the input image data IDAT represents the still image.
In a case where the input image data IDAT represents the still image, to drive the display panel 410 at the driving frequency or at the output frame frequency OFF that is lower than the input frame frequency IFF, the controller 460 may set at least one frame period as the masking period, and may not drive the display panel 410 during the masking period. For example, the controller 460 may control the data driver 420 to not provide the data signals DS to the plurality of pixels PX during the masking period, and may control the scan driver 430 to not provide the scan signals SS to the plurality of pixels PX during the masking period. In some example embodiments, during the masking period, the emission driver 400 may provide the emission signals SEM to the plurality of pixels PX at the input frame frequency IFF, such that the display panel 410 may periodically emit light. Further, in some example embodiments, the power supply unit 450 may provide the bottom electrode voltage VBML to the bottom electrode of each pixel PX. Accordingly, a voltage distortion of the gate node of each pixel PX may be compensated.
For example, as illustrated in
In a case where the still image detector 470 determines that the input image data IDAT represents the still image, the controller 460 may determine the driving frequency of the display panel 410, or the output frame frequency OFF, to be lower than the input frame frequency IFF. In some example embodiments, the controller 460 may determine a flicker value (e.g., a value representing a level of a flicker perceived by a user) corresponding to a gray level (e.g., a grayscale level) or luminance of the input image data IDAT, and may determine the driving frequency of the display panel 410 according to (e.g., based on) the flicker value. For example, as illustrated in
During the masking period MP, the controller 460 may control the data driver 420 to not provide the data signals DS to the plurality of pixels PX. For example, during the third frame period FP3, the controller 460 may provide the data driver 420 with the frame data FDAT as the output image data ODAT, and the output data enable signal ODE synchronized with the output image data ODAT. However, during the masking period MP, or during the fourth and fifth frame periods FP4 and FP5, the controller 460 may not provide the output image data ODAT and the output data enable signal ODE to the data driver 420. In other words, the controller 460 may provide the data driver 420 with one frame of data FDAT during the three frame periods FP3, FP4, and FP5, and thus, the data driver 420 may drive the display panel 410 at the driving frequency, or the output frame frequency OFF, of about 20 Hz, which is one third of the input frame frequency IFF of about 60 Hz.
Further, during the masking period MP, or during the fourth and fifth frame periods FP4 and FP5, the controller 460 may control the power supply unit 450 to provide the bottom electrode voltage VBML to the bottom electrode of each pixel PX. In some example embodiments, the bottom electrode voltage VBML may be a positive voltage, for example, in a range from about 5V to about 8V, but the present inventive concept is not limited thereto. In other example embodiments, the bottom electrode voltage VBML may be a negative voltage, for example, in a range from about −5V to about −8V, but the present inventive concept is not limited thereto. Accordingly, a voltage distortion of the gate node of each pixel PX during the masking period MP may be compensated, and thus, the image quality of the organic light emitting diode display device 400 may be improved.
As described above, the organic light emitting diode display device 400 according to one or more example embodiments may perform the low frequency driving by detecting the still image, and may set at least one frame period as the masking period MP when performing the low frequency driving. Further, the organic light emitting diode display device 400 may provide the bottom electrode voltage VBML to the bottom electrode of each pixel PX during the masking period MP. Accordingly, the voltage distortion of the gate node of each pixel PX during the masking period MP may be compensated, and thus, the image quality of the organic light emitting diode display device 400 may be improved.
Referring to
In some example embodiments, the still image detector 470 may receive the input image data IDAT at the input frame frequency IFF, may divide the input image data IDAT into a plurality of partial image data, and may determine whether each of the plurality of partial image data represents a still image. For example, each partial image data may correspond to N consecutive scan signal lines, where N is an integer greater than 0. In some example embodiments, the still image detector 470 may detect a boundary between a moving image and a still image, and may divide the input image data IDAT into first partial image data for the moving image and second partial image data for the still image. For example, as illustrated in
In a case where at least one partial image data of the plurality of partial image data represents the still image, to drive a portion of the display panel 410a corresponding to the at least one partial image data at a driving frequency lower than the input frame frequency IFF, the controller 460 may set a portion of a frame period corresponding to the portion of the display panel 410a as a masking period.
For example, as illustrated in
Referring to
As illustrated in
Referring to
The processor 1110 may perform various computing functions and/or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), and/or the like. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, and/or the like. Further, in some example embodiments, the processor 1110 may be further coupled to an extended bus, such as a peripheral component interconnection (PCI) bus and/or the like.
The memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device, such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and/or the like, and/or at least one volatile memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, and/or the like.
The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, and/or the like. The I/O device 1140 may be an input device, such as a keyboard, a keypad, a mouse, a touch screen, and/or the like, and an output device, such as a printer, a speaker, and/or the like. The power supply 1150 may supply power for operations of the electronic device 1100. The organic light emitting diode display device 1160 may be coupled to other components through the buses or other communication links.
In each pixel of the organic light emitting diode display device 1160, a third transistor (e.g., a threshold voltage compensating transistor) may include first and second sub-transistors that are serially connected between a gate node and a drain of a first transistor, a fourth transistor (e.g., a gate initializing transistor) may include third and fourth sub-transistors that are serially connected between the gate node and a line of an initialization voltage, and at least one of the second sub-transistor and the fourth sub-transistor may include a bottom electrode. In some example embodiments, the bottom electrode may receive a bottom electrode voltage that is a positive voltage or a negative voltage during a masking period in which a display panel is not driven. Accordingly, a voltage distortion of the gate node at low frequency driving may be compensated, and an image quality of the organic light emitting diode display device 1160 may be improved.
One or more of the example embodiments of the inventive concept may be applied to any suitable organic light emitting diode display device 1160, and/or any suitable electronic device 1100 including the organic light emitting diode display device 1160. For example, one or more of the example embodiments of the inventive concept may be applied to a mobile phone, a smart phone, a wearable electronic device, a tablet computer, a television (TV), a digital TV, a 3D TV, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, and/or the like.
The foregoing is illustrative of example embodiments, and is not to be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that various modifications are possible in the example embodiments without departing from the spirit and scope of the present inventive concept. Accordingly, all such modifications are intended to be included within the spirit and scope of the present inventive concept, as defined in the claims and their equivalents. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed herein, and that various modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the appended claims, and their equivalents.
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