This application claims the priority benefit of Taiwan application serial no. 99139416, filed on Nov. 16, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The invention relates to a pixel structure. More particularly, the invention relates to a pixel structure and a dual gate pixel structure of a flat panel display (FPD).
2. Description of Related Art
In the highly competitive FPD industry, manufactures are not only dedicated to research and development of FPDs with superior performance but also making great efforts to reduce production costs, so as to increase profits and supply affordable FPDs to the consumer market.
Thin film transistor liquid crystal displays (TFT LCDs), one of the most popular FPDs, are taken for example. There are various methods for reducing production costs of the TFT LCDs. One of the methods is to reduce the number of photo masks required in a fabrication process of a pixel structure, so as to reduce human power and manufacturing time and further lower down the production costs.
In general, the number of photo masks required in the fabrication process of the pixel structure can be reduced by simplifying the conventional five-mask process to be the four-mask process.
The photoresist layer 110 coated onto the second metal layer 108 is then patterned by using a half tone photo mask or a gray tone photo mask, i.e., the second photo mask 200, as shown in
The metal layer is often coated with non-uniform photoresist. For instance, the right portion of the photoresist layer 110 shown in
When a second wet etching process is performed with use of the photoresist layer 110 as a mask, the exposed second metal layer 108 is etched, and the underlying semiconductor layer 106 is partially exposed, as shown in
A passivation layer 112 is formed on the substrate 100 after the remaining photoresist layer 110 is removed, as indicated in
The invention is directed to a pixel structure that can preclude the abnormal pixel display.
The invention is directed to a dual gate pixel structure that can preclude the abnormal pixel display as well.
The invention provides a pixel structure that includes a substrate, a first metal layer, a gate insulator, a semiconductor layer, a second metal layer, a passivation layer, a hole, and a pixel electrode. The first metal layer is configured on the substrate. Besides, the first metal layer includes a scan line, a gate electrically connected to the scan line, and a common electrode. The common electrode is separated from the scan line and has a predetermined opening. The predetermined opening is located on an edge of the common electrode. The gate insulator is configured on the substrate and covers the first metal layer. The semiconductor layer is configured on the gate insulator. The second metal layer is configured on the semiconductor layer, and the semiconductor layer underlies the entire second metal layer. Besides, the second metal layer includes a data line, a source, a drain, and a storage electrode. The scan line and the data line are intersected. The source is electrically connected to the data line. The storage electrode is located above the predetermined opening. The passivation layer is configured on the substrate and covers the second metal layer. Besides, the passivation layer has an opening that exposes the drain. The hole located in the predetermined opening goes through the passivation layer and exposes the second metal layer. The pixel electrode is configured on the passivation layer and fills the hole. The pixel electrode is electrically connected to the drain via the opening and electrically connected to the second metal layer via the hole.
The invention further provides a dual gate pixel structure that includes a substrate, a first metal layer, a gate insulator, a semiconductor layer, a second metal layer, a passivation layer, a hole, and a pixel electrode. The first metal layer is configured on the substrate. Besides, the first metal layer includes two scan lines, two gates electrically connected to the scan lines, and a common electrode. The common electrode is separated from the scan lines and has two predetermined openings. The predetermined openings are located on an edge of the common electrode. The gate insulator is configured on the substrate and covers the first metal layer. The semiconductor layer is configured on the gate insulator. The second metal layer is configured on the semiconductor layer, and the semiconductor layer underlies the entire second metal layer. Besides, the second metal layer includes a data line, two sources, two drains, and two storage electrodes. The scan lines and the data line are intersected. The sources are electrically connected to the data line, respectively. The storage electrodes are located above the predetermined openings. The passivation layer is configured on the substrate and covers the second metal layer. Besides, the passivation layer has two openings that expose the drains. The holes located in the predetermined openings go through the passivation layer and expose the second metal layer. The pixel electrodes are configured on the passivation layer and fill the holes. The pixel electrodes are electrically connected to the drains via the openings and electrically connected to the second metal layer via the holes.
According to an embodiment of the invention, the hole that goes through the passivation layer and is located in the predetermined opening does not go through the second metal layer, the semiconductor layer, and the gate insulator.
According to an embodiment of the invention, the hole that goes through the passivation layer and is located in the predetermined opening further goes through the second metal layer, the semiconductor layer, and the gate insulator and exposes a side wall of the second metal layer, a side wall of the semiconductor layer, a side wall of the gate insulator, and a surface of the substrate.
According to an embodiment of the invention, the common electrode is located at the peripheries of the pixel electrode and is partially overlapped with the pixel electrode.
According to an embodiment of the invention, the overlapping portion of the common electrode and the pixel electrode is where a storage capacitor is formed.
According to an embodiment of the invention, an overlapping portion of the common electrode and the storage electrode is where a storage capacitor is formed.
According to an embodiment of the invention, the common electrode has at least one bending portion, and the predetermined opening and the bending portion at least have a distance therebetween.
According to an embodiment of the invention, the predetermined opening and an edge of the storage electrode at least have a distance therebetween.
According to an embodiment of the invention, the hole is substantially smaller than the predetermined opening.
In the pixel structure and the dual gate pixel structure of the invention, the predetermined opening of the common electrode can prevent a portion of the second metal layer, a portion of the semiconductor layer, and a portion of the gate insulator that are located below the hole from being etched because of the uneven photoresist coating. Further, the issue of the short circuit between the common electrode and the pixel electrode can be resolved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below.
The accompanying drawings constituting a part of this specification are incorporated herein to provide a further understanding of the invention. Here, the drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
A method of forming the pixel structure in this embodiment is exemplarily described below. As indicated in
Note that the common electrode CL of this embodiment has at least one bending portion and a predetermined opening O. The predetermined opening O is located on the edge of the common electrode CL, and therefore the predetermined opening O and the bending portion have a proper distance therebetween. In this embodiment, the substrate 300 is made of glass, quartz, an organic polymer, an opaque/reflective material (e.g., a conductive material, a wafer, ceramics, or any other appropriate material), or any other appropriate material, for instance. The first metal layer 302 is made of an alloy, metal, or any other appropriate material, for instance.
A gate insulator 304, a semiconductor layer 306, and a second metal layer 308 are sequentially formed on the entire substrate 300 to cover the scan line SL and the common electrode CL. In this embodiment, the gate insulator 304 is made of an inorganic dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer containing at least two of the aforesaid materials), an organic dielectric material, or a combination thereof, for instance. The semiconductor layer 306 of this embodiment is made of an amorphous silicon layer or any other appropriate semiconductor material, for instance. The second metal layer 308 of this embodiment is made of an alloy, metal, or any other appropriate material, for instance.
After the gate insulator 304, the semiconductor layer 306, and the second metal layer 308 are formed, the second metal layer 308 is coated with a photoresist layer 310. The photoresist layer 310 of this embodiment can be made of a positive photoresist material or a negative photoresist material, which is not limited in this invention. However, the photoresist layer 310 coated onto the second metal layer 308 often has the uneven thickness. For instance, a portion of the photoresist layer 310 that is located above the predetermined opening O has a relatively thin thickness, as indicated in
The photoresist layer 310 is then patterned with use of the second photo mask 400 (e.g., a half tone photo mask), as indicated in
Upon completion of said processes, an O2 ashing process is performed to clean superficial organic remains. During the O2 ashing process, a portion of the photoresist layer 310 located above the scan line SL is removed to expose a portion of the second metal layer 308. Meanwhile, the portion of the photoresist layer 310 that is located above the predetermined opening O and has the relatively thin thickness is removed, and a portion of the underlying second metal layer 308 is exposed, as indicated in
After the photoresist layer 310 is patterned, a second wet etching process is performed to etch the exposed portion of the second metal layer 308 located above the scan line SL, such that the source S and the drain D are formed, and that a portion of the semiconductor layer 306 is exposed, as indicated in
After the photoresist layer 310 is patterned, a second dry etching process is performed. Here, the exposed portion of the semiconductor layer 306 located above the scan line SL is partially removed, as indicated in
Here, all the processes performed with use of the second photo mask aim at patterning the second metal layer 308 and the semiconductor layer 306. In this embodiment, the patterned second metal layer 308 includes a data line DL, the source S, the drain D, and a storage electrode CE, as indicated in
Note that the pixel structure of this embodiment is formed with use of four photo masks. Namely, after the gate insulator 304, the semiconductor layer 306, and the second metal layer 308 are sequentially formed on the entire substrate 300, the gate insulator 304, the semiconductor layer 306, and the second metal layer 308 are patterned by using the same photo mask. Accordingly, after said processes are completed, the semiconductor layer 306 underlies the data line DL, the source S, the drain D, and the storage electrode CE in this embodiment. Here, the storage electrode CE of this embodiment is located above the predetermined opening O and partially overlapped with the common electrode CL. Hence, the overlapping portion of the common electrode CL and the storage electrode CE can be where a storage capacitor is formed. Besides, in this embodiment, an edge CE-a of the storage electrode CE and an edge O-a of the predetermined opening O at least have a distance d therebetween, and the edge CE-a of the storage electrode CE and an edge CL-a of the common electrode CL at least have a distance d′ therebetween. The distance d and the distance d′ are both greater than zero in this embodiment and preferably greater than the maximum error tolerance (e.g., 3 um) in an alignment process. Thus, the overlapping portion of the common electrode CL and the storage electrode CE is not varied because of the errors in the alignment process, and the storage capacitance generated thereby is not changed. As such, no relevant electrical issue caused by the changed storage capacitance is raised.
After all the processes performed with use of the second photo mask are completed, the remaining photoresist layer 310 is removed, and a passivation layer 312 is formed on the substrate 300 to cover the second metal layer 308, as shown in
When the opening W and the hole H are formed, note that a portion of the semiconductor layer 306 and a portion of the gate insulator 304 that correspond to the hole H are completely removed, such that the hole H which goes through the passivation layer 312 and is located in the predetermined opening O further goes through the second metal layer 308, the semiconductor layer 306, and the gate insulator 304 and exposes a side wall of the second metal layer 308, a side wall of the semiconductor layer 306, a side wall of the gate insulator 304, and a surface of the substrate 300, as indicated in
A pixel electrode PE is then formed on the substrate 300 with use of the third photo mask. The pixel electrode PE is electrically connected to the drain D via the opening W and electrically connected to the storage capacitor CE of the second metal layer 308 and the exposed substrate 300 via the hole H. Here, the conventional issue of short circuit between the pixel electrode PE and the first metal layer 302 is not raised.
The common electrode CL of this embodiment has the predetermined opening O located below the hole H, and the predetermined opening O is substantially greater in size than the hole H. In case of the uneven photoresist coating, the pixel electrode PE can merely be in contact with the storage electrode CE of the second metal layer 308 and the substrate 300 via the hole H but not in contact with the common electrode CL. Hence, the issue of short circuit is not raised. In other words, the abnormal pixel display caused by the uneven photoresist coating as disclosed in the related art can be prevented in the invention as described above, and the display quality and electrical performance of the pixel structure can be improved according to this embodiment.
It should be mentioned that the hole H going through the passivation layer 312 and located in the predetermined opening O does not go through the second metal layer 308, the semiconductor layer 306, and the gate insulator 304, given the photoresist layer 312 is evenly coated onto the second metal layer 308 and has the uniform thickness. Namely, the hole H exposes the second metal layer 308 but does not go through the second metal layer 308, nor does the hole H expose or go through the semiconductor layer 306 and the gate insulator 304.
Based on the above, another pixel structure that includes the substrate 300, the first metal layer 302, the gate insulator 304, the semiconductor layer 306, the second metal layer 308, the passivation layer 312, the hole H, and the pixel electrode PE can also be provided in this embodiment. The first metal layer 302 is configured on the substrate 300 and includes the scan line SL, the gate electrically connected to the scan line SL, and the common electrode CL. The common electrode CL is separated from the scan line SL and has a predetermined opening O that is located on the edge of the common electrode CL, as shown in
In the pixel structure of this embodiment, the second metal layer 308 is configured on the semiconductor layer 306, and the semiconductor layer 306 underlies the entire second metal layer 308. Here, the second metal layer 308 includes the data line DL, the source S, the drain D, and the storage electrode CE. The scan line SL and the data line DL are intersected. The source S is electrically connected to the data line DL. The storage electrode CE is located above the predetermined opening O. The passivation layer 312 is configured on the substrate 300 and covers the second metal layer 308. Besides, the passivation layer 312 has an opening W that exposes the drain D. In this embodiment, the hole H is located in the predetermined opening O, goes through the passivation layer 312, and exposes the second metal layer 308. The pixel electrode PE is configured on the passivation:layer 312 and fills the hole H. Here, the pixel electrode PE is electrically connected to the drain D via the opening W and electrically connected to the second metal layer 308 via the hole H.
In this embodiment, the common electrode CL of the pixel structure has the predetermined opening O located below the hole H, and the predetermined opening O is substantially greater in size than the hole H. In case of the uneven photoresist coating as described in the related art, the pixel electrode PE can merely be in contact with the storage electrode CE of the second metal layer 308 and the substrate 300 via the hole H. As such, the electrical performance of the pixel structure can be improved, and the pixel structure applied to a display device can have satisfactory display quality.
The predetermined opening of the common electrode CL as described in the first embodiment is applicable to the dual gate pixel structure of the second embodiment, such that the issue of short circuit between the pixel electrode and the common electrode in the dual gate pixel structure of this embodiment can be prevented as well.
The method of forming the dual gate pixel structure and the material of each layer in this embodiment are similar to those described in the first embodiment, and thus no further description is provided herein. The difference between the dual gate pixel structure of this embodiment and the pixel structure of the first embodiment is elaborated hereinafter.
With reference to
Since the pixels located at the right and the left sides of the data line DL share the same data line DL in the dual gate pixel structure of this embodiment, the number of the data line DL in the pixel structure can be reduced, the number of the integrated circuits required by the display panel of the dual gate pixel structure can be decreased, and the manufacturing costs can be lowered down.
However, the storage capacitances at the right and the left sides of the data line DL in the dual gate pixel structure of this embodiment may differ from each other because the first metal layer 302 (the common electrode CL) and the second metal layer 308 (the storage electrode CE) are misaligned. As such, the display panel having said pixel structure is likely to have unfavorable display quality.
To resolve said issue, the edges CE-a of the storage electrodes CE at the right and the left sides of the data line DL and the edges O-a of the corresponding predetermined openings O have at least a distance d therebetween in the dual gate pixel structure of this embodiment. The edges CE-a of the storage electrodes CE at the right and the left sides of the data line DL and the edges CL-a of the corresponding common electrodes CL have at least a distance d′ therebetween. The distance d and the distance d′ are both greater than zero in this embodiment and preferably greater than the maximum error tolerance (e.g., 3 um) in an alignment process. Thereby, the storage capacitances of the pixels at the right and the left sides of the data line DL are not apt to be affected by the misalignment of the first metal layer 302 and the second metal layer 308. As such, the issues (e.g., non-uniform luminance, cross talk, and so on) of unfavorable display quality caused by the inconsistent storage capacitances at the right and the left sides of the data line DL can be resolved.
In light of the foregoing, the predetermined opening of the common electrode can prevent a portion of the second metal layer, a portion of the semiconductor layer, and a portion of the gate insulator that are located below the hole from being etched because of the uneven photoresist coating according to this invention. Further, the issue of the short circuit between the common electrode and the pixel electrode can be resolved.
Moreover, as long as the predetermined opening is properly located, the unfavorable display quality resulting from the misalignment of the first metal layer and the second metal layer can be improved.
Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.
Number | Date | Country | Kind |
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99139416 | Nov 2010 | TW | national |