BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a stripe-shaped pixel structure according to the prior art.
FIG. 2 is a schematic diagram of a shadow mask utilized to fabricate the stripe-shaped pixel structure of FIG. 1.
FIG. 3 is a schematic diagram of another pixel structure according to the prior art.
FIG. 4 is a schematic diagram of a shadow mask utilized to fabricate another pixel structure of FIG. 3.
FIG. 5 is a schematic diagram of a pixel structure according to a preferred embodiment of the present invention.
FIG. 6 is a schematic diagram of a display pixel unit of the pixel structure of FIG. 5.
FIG. 7 is a flow chart of a method of fabricating a pixel structure according to the present invention.
FIGS. 8 to 10 are schematic diagrams of shadow masks utilized to fabricate the pixel structure shown in FIG. 5 according to the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 5, which is a schematic diagram of a pixel structure for use in an electroluminescent panel according to a preferred embodiment of the present invention. As shown in FIG. 5, the pixel structure 50 comprises a substrate 52, a plurality of first subpixel units 54 disposed on the substrate 52, a plurality of second subpixel units 56 disposed on the substrate 52, and a plurality of third subpixel units 58 disposed on the substrate 52. In the preferred embodiment, the first subpixel units 54, the second subpixel units 56, and the third subpixel units 58 are red, green, and blue subpixel units, respectively, and therefore each first subpixel unit 54 comprises three first subpixels (red subpixels) R arranged in a delta formation, each second subpixel unit 56 comprises three second subpixels (green subpixels) G arranged in a delta formation, and each third subpixel unit 58 comprises three third subpixels (blue subpixels) B arranged in a delta formation.
In the pixel structure 50 of the preferred embodiment, the first subpixel unit 54, the second subpixel unit 56 and the third subpixel unit 58 are arranged in an alternating formation. As shown in FIG. 5, according to a direction of a row of subpixel units, the subpixel units disposed in each row are arranged in a repeating sequence of one first subpixel unit 54 followed by one second subpixel unit 56 followed by one third subpixel unit 58. In adjacent rows, the first subpixel unit 54, the second subpixel unit 56, and the third subpixel unit of a row are disposed in a mismatched arrangement relative to the first subpixel unit 54, the second subpixel unit 56 and the third subpixel unit 58 of an adjacent row. Further, any two adjacent subpixel units are upside-down relative to each other, such as an obverse triangle and a reverse triangle.
FIG. 5 shows an arrangement of the subpixel units of the pixel structure 50, but the pixel structure 50 forms a display frame by combining display pixel units when displaying an image. Please refer to FIG. 6, which is a schematic diagram of the display pixel unit 60 of the pixel structure 50 shown in FIG. 5. As shown in FIG. 6, the pixel structure 50 comprises a plurality of display pixel units 60. Each display pixel unit 60 comprises a first subpixel R, a second subpixel G, and a third subpixel B. The first subpixel R, the second subpixel G, and the third subpixel B of each display pixel unit 60 respectively belong to one first subpixel unit 54, one second subpixel unit 56 and one third subpixel unit 58 that are adjacent to each other.
As can be seen in FIG. 6, a characteristic of a structure of the display pixel unit 60 of the preferred embodiment is that the first subpixel R of each display pixel unit 60 is next to the first subpixels R of two adjacent display pixel units 60, the second subpixel G of each display pixel unit 60 is next to the second subpixels G of two adjacent display pixel units 60, and the third subpixel B of each display pixel unit 60 is next to the third subpixels B of two adjacent display pixel units 60. Additionally, in each display pixel unit 60, the first subpixel R, the second subpixel G and the third subpixel B are arranged in a delta formation, such that each display pixel unit 60 forms a similar triangle structure. In addition, each display pixel unit 60 in a same row is oriented differently from an adjacent pixel unit in the same row. In other words, any two adjacent display pixel units 60 are upside-down (such as an obverse triangle and a reverse triangle) relative to each other.
As designed, in the aforementioned display pixel unit 60, the first subpixel R, the second subpixel G, and the third subpixel B of each display pixel unit 60 are arranged in a delta formation, and the arrangement centralizes a distribution of the subpixels. Therefore, light is mixed more effectively, whereby display quality is improved. Additionally, due to the arrangement of the first pixel unit 54, the second pixel unit 56, and the third pixel unit 58, the limitations on the shadow mask mentioned above are overcome, and precision of the pixel structure is increased. Please refer to FIG. 7, which is a flow chart of the present invention method of fabricating the pixel structure for use in an electroluminescent panel. As shown in FIG. 7, the method comprises:
Step 70: Providing a substrate;
Step 72: Providing a first shadow mask having a plurality of first openings patterned in an array of similar T shapes;
Step 74: Utilizing the first shadow mask to evaporate a plurality of first subpixel units corresponding to each first opening onto the substrate, where each first subpixel unit comprises three first subpixels arranged in a delta formation;
Step 76: Providing a second shadow mask having a plurality of second openings patterned in an array of similar T shapes;
Step 78: Utilizing the second shadow mask to evaporate a plurality of second subpixel units corresponding to each second opening onto the substrate, where each second subpixel unit comprises three second subpixels arranged in a delta formation, and no second subpixel unit overlaps any of the plurality of first subpixel units;
Step 80: Providing a third shadow mask having a plurality of third openings patterned in an array of similar T shapes; and
Step 82: Utilizing the third shadow mask to evaporate a plurality of third subpixel units corresponding to each third opening onto the substrate, where each third subpixel unit comprises three third subpixels arranged in a delta formation, and no third subpixel unit overlaps any of the plurality of first subpixel units or any of the plurality of second subpixel units;
By the aforementioned steps, the pixel structure can be formed on the substrate. The display pixel unit of the pixel structure comprises one first subpixel of each first subpixel unit, one second subpixel of one second subpixel unit adjacent to the first subpixel unit, and one third subpixel of one third subpixel unit adjacent to the first subpixel unit. Please refer to FIGS. 8-10, which are diagrams of the shadow mask used to fabricate the pixel structure shown in FIG. 5 according to the present invention. FIG. 8 is a schematic diagram of the first shadow mask, FIG. 9 is a schematic diagram of the second shadow mask, and FIG. 10 is a schematic diagram of the third shadow mask. As shown in FIGS. 8-10, the first shadow mask 90R comprises a plurality of first openings 92R patterned in an array of similar T shapes. Each first opening 92R in a same row is oriented differently from an adjacent first opening in the same row. The second shadow mask 90G comprises a plurality of second openings 92G patterned in an array of similar T shapes. Each second opening 92G in a same row oriented differently from an adjacent second opening in the same row. The third shadow mask 90B comprises a plurality of third openings 92B patterned in an array of similar T shapes. Each third opening 92B in a same row oriented differently from an adjacent third opening in the same row.
Arrangements of openings in the first shadow mask 90R, the second shadow mask 90G, and the third shadow mask 90B are similar, a difference being that the arrangement of openings in each shadow mask is offset from the arrangement of openings in each other shadow mask. The arrangement of openings in the shadow mask increases a distance between each opening, so that production of the shadow mask does not face the above mentioned process limitation arising due to the consideration of the structural strength of the shadow mask. As can be seen from FIGS. 8-10, for the first shadow mask 90R, the second shadow mask 90G, and the third shadow mask 90B, the distance separating each of the plurality of first openings 92R, the distance separating each of the plurality of second openings 92G, and the distance separating each of the plurality of third openings 92B are all far over the process limitation. By utilizing the first shadow mask 90R, the second shadow mask 90G, and the third shadow mask 90B in order in the evaporation deposition process, the pixel structure shown in FIG. 5 can be fabricated. In such a way, although the distance separating the first openings 92R, the distance separating the second openings 92G, and the distance separating the third openings 92B are respectively bigger than the distances separating subpixels of the prior art, when the shadow masks are combined, the pixel structure has smaller distances between subpixels, which effectively increases resolution.
By utilizing the pixel structure design and the method according to the present invention, the resolution of electroluminescent panel can be increased effectively. It is worthy of note that the pixel structure of the present invention can be applied to all kinds of full color display panels, such as OLED display panels or polymer light emitting diode (PLED) display panels. Therefore, depending on different display panel types, each subpixel can comprise an organic light emitting diode or a polymer light emitting diode to effectively increase resolution while still following the spirit of the pixel structure design of the present invention.
In summary, to improve a thin-film transistor display panel fabrication process, the pixel structure of the present invention and method of making the same can overcome the evaporation deposition process limitation to increase the precision of subpixel fabrication, exceeding 200 ppi in practice. Therefore, the evaporation deposition process is removed as a bottleneck for increasing resolution.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20080001536
