1. Field of the Invention
The invention relates generally to light detectors and more specifically to photodiodes.
2. Discussion of the Related Art
Photo-sensitive diodes are generally referred to as photodiodes. A photodiode can be used as a light detector. When used as a light detector, the sensitivity of the photodiode is approximately proportional to the lateral junction area thereof. For that reason, it is often desirable to have large lateral junction areas in a photodiodes used as light detectors.
In one aspect, an apparatus includes a light detector that includes a substrate with a planar surface and an array of photodiodes located along the planar surface. Each photodiode has a sequence of different semiconductor layers stacked vertically over the planar surface. The photodiodes are electrically connected in series.
In some embodiments of the apparatus, the photodiodes are arranged concentrically around a single region of the planar surface.
In some embodiments of the apparatus, each sequence includes a p-i-n vertical stack of semiconductor layers over the planar surface. Also, the p-i-n vertical stacks may be located between the metal connection layers and the substrate.
In some embodiments of the apparatus, each photodiode includes a back-to-back stack of two photodiodes over the planar surface. In such embodiments, each sequence may include an p-i-n vertical stack of semiconductor layers over the planar surface.
In some embodiments, the apparatus further includes an optical modulator connected to transmit a modulated optical carrier to the light detector and an antenna connected to receive an electrical driving signal from the light detector.
In another aspect, a method includes illuminating a planar array of photodiodes with a light beam. The photodiodes of the planar array are electrically connected in series. The method also includes producing an electrical signal from the planar array while the planar array is illuminated by the light beam. The electrical signal is indicative of an intensity of the light beam.
In some embodiments of the method, the illuminating includes passing light of the light beam through a surface of a planar substrate opposite to a surface of the planar substrate on which the planar array is located.
In some embodiments of the method, the illuminating includes illuminating a back-to-back stack of photodiodes located over the planar substrate. The photodiodes of the stack are connected in parallel to a light detection circuit.
In some embodiments, the method further includes optically modulating a data-carrying signal onto an optical carrier, wherein the modulated optical carrier produces the light beam. In such embodiments, the method further includes driving an antenna with the produced electrical signal.
In the Figures and text, similar reference numbers refer to features with substantially similar functions and/or substantially similar structures.
In some of the Figures, the relative dimensions of one or more features may be exaggerated to more clearly illustrate the elements therein.
Herein, various embodiments are described more fully by the Figures and the Detailed Description of Illustrative Embodiments. Nevertheless, the inventions may be embodied in various forms and are not limited to the specific embodiments that are described in the Figures and/or the Detailed Description of Illustrative Embodiments.
In the exemplary planar array 10, the photodiodes 121, . . . , 12N are concentric annuli, which are centered about a central region 17 of the substrate 16. The electrode 6 is, e.g., a metal electrode that directly electrically connects to one side of the inner-most photodiode 121. The electrode 8 is an annular metal electrode that directly electrically connects to one side of the outer-most photodiode 12N.
The concentric arrangement of the photodiodes 121, . . . , 12N in the planar array 10 may improve detection sensitivity when the planar array 10 is used to detect a light beam whose cross section approximately matches the area of the planar array 10. In such embodiments of the planar array 10, it may also be useful to approximately match the radial distribution of areas of the photodiodes 121, . . . , 12N to the radial intensity profile of the light beam whose intensity is to be detected or measured.
In other embodiments of a planar array, the photodiodes may have different relative positions and/or may also have different overall relative shapes.
Referring to
In the planar array 10, laterally adjacent photodiodes 121, . . . , 12N are directly electrically connected in series. In particular, the planar array 10 includes metal connection layers 28k, 28k+1, dielectric sidewalls 30k, 30k+1, inter-diode isolation regions 32k, 32k+1, and top and bottom p+-type and n+-type semiconductor layers to support the series electrical connections. The metal connection layer 28k+1 directly electrically connects the top p+-type semiconductor layer of the photodiode 12k+1 to the bottom n+-type semiconductor layer 34 of the adjacent photodiode 12k. The dielectric sidewalls 30k, 30k+1 electrically insulate other parts of the photodiodes 12k, 12k+1 from the metal connection layers 28k, 28k+1. The inter-diode isolation regions 32k, 32k+1 electrically insulate adjacent portions of bottom n+-type semiconductor layer 34 so that bottoms of the adjacent photodiodes 12k, 12k+1 are not electrically shorted together.
In this second planar array 10, the vertical stacking of p-i-n photodiodes into pairs 121, . . . , 12k+1 produces a higher effective light sensing area per unit surface area than an array of p-i-n photodiodes with the same lateral diameters, but not being vertically stacked. In particular, the back-to-back stacking results in a vertically stacked pair of semiconductor junctions in each photodiodes 121, . . . , 12N. This vertical stacking can substantially increase the effective sensing area for light perpendicularly incident onto the planar array 10 with respect to the sensing area of the planar array 10 of
In the planar arrays 10 of
In alternate embodiments the order of p-type and n-type semiconductor layers may be interchanged in the planar arrays 10 shown in
A series-connected planar array of photodiodes, e.g., as shown in
For example, a planar array of vertically oriented photodiodes provides a larger lateral junction area than the single photodiodes thereof. Since the light sensitivity of a photodiode is proportional to the lateral junction area, replacing a single vertical photodiode with a planar array of such photodiodes typically produces an increased sensitivity to light.
Also, a planar array of electrically “series-connected” photodiodes typically has a lower capacitance than a single large photodiode having a lateral junction area equal to that of the entire planar array provided that photodiodes of planar array have the same junction structure as the single large photodiode. In a series-connected planar array, the total capacitance is also lower, because the total capacitance of such an array is equal to the inverse of the sum of the inverses of the capacitances of the individual photodiodes therein. Even though the total resistance of such a planar array of photodiodes will be larger than the resistance of an individual photodiode therein, making an array of such individual photodiodes does not necessarily negatively impact the operating speed. In particular, the process of series connecting individual photodiodes can be done such that the total resistance scales up at a rate similar to the rate at which the total capacitance scales down. Since the parasitic time constant of a diode is the product of a diode's resistance and its capacitance, the parasitic time constant of such an array can remain fairly constant as more individual photodiodes are serially connected thereto. Indeed, as compared with a single photodiode of the same total lateral junction area and junction structure, such a planar array can have a much shorter minimum response time. Thus, such a planar array may allow the total lateral junction area to be increased without undesired reduction in the maximum operating speed of a photodiode light detector. For these reasons, a planar array of series-connected photodiodes can provide a high-sensitivity light detector that is adapted for high operating speeds.
In the wireless transmission system 40 of
In case of top-illumination of the planar array 10, the top surface of the planar array would be coated with an anti-reflective layer to efficiently couple light from the optical fiber into the planar array. In case of bottom illumination of the planar array 10, the bottom surface of the planar array would be coated with an anti-reflective layer known to a skilled person. In both cases, additional optical elements such as lenses and collimators may be used to enhance the coupling efficiency between optical fiber and planar array 10.
Devices and systems for wireless transmission, which may be easily modified to use the planar array 10 of
The method 70 includes forming a subcollector layer 92 on a semi-insulating planar InP substrate 16 as shown in the intermediate structure 82 of
The method 70 includes forming a lateral distribution of vertical multi-layer structures 94k, 94k+1 for the individual photodiodes on the crystalline InP subcollector layer 92 as shown in the intermediate structure 84 of
The series of conventional deposition and doping steps produces the layer structure of the vertical multi-layer structures 94k, 94k+1. An exemplary bottom-to-top layer structure for the multi-layer structures 94k, 94k+1 is as follows. The bottom layer 96 is about 200 nm of crystalline n-type InP with about 5×1016 n-type dopant atoms per cm3, e.g., Si or S atoms. The next higher layer 98 is a thin barrier layer of about 5 nm of crystalline n-type InP. In the thin barrier layer 98, the n-type dopant atom concentration is about 5×1017 per cm3. The next higher layer 100 is about 50 nm of (In1−xGax)(As1−yPy) semiconductor, which has an alloy composition that is bottom-to-top graded. The grading is such that x varies linearly in a bottom-to-top direction from about 0.18 to about 0.47, and y varies linearly in a bottom-to-top direction from about 0.64 to about 0.0. In this layer, the n-type dopant atom concentration varies linearly from a bottom value of about 5×1016 (i.e., n-type) to a top value of about 1015 (i.e., intrinsic-type). The next higher layer 102 is configured to absorb light at about a telecommunications wavelength, i.e., about 1.55 μm. This layer 102 has about 500 nm of crystalline p-type (In0.53Ga0.47)As. In the layer 102, p-type dopant atoms (e.g., zinc (Zn) and/or beryllium (Be) atoms) have a concentration that is graded from a bottom value of about 5×107 per cm3 to a top value of about 2×1018 per cm3. The layer 102 typically has a bandgap that is smaller than the bandgap of parts of the graded layer 100. In another embodiment, this layer may consist of (Ga0.5As0.5)Sb, enabling a “type-II” band alignment with the InP material of layer 98, hence obliterating the need for a graded layer 100. In both cases, the composition of layer 102 may be varied across the layer in addition to the doping concentration to produce an intrinsic electric field in the layer 102, thus accelerating photo-generated electrons toward the collection layer 98.
The next layer 104 is a barrier layer of about 200 nm of crystalline p+-type InP. This layer 104 has about 1019 p-type dopant atoms per cm3 ((e.g., Zn and/or Be atoms). The top layer 106 is an electrode layer of about 30 nm of p+-type (In0.53Ga0.47)As. This layer 106 also has about 1019 p-type dopant atoms per cm3.
In the above sequence of semiconductor layers, the linear alloy and/or dopant graded layers can also be approximated by stacks of thinner semiconductor layers of fixed alloys and dopant concentrations intermediate to the alloys and dopant concentrations of the final and initial semiconductor layers.
A conventional mask-controlled wet or dry etch patterns the multi-layer thereby producing the lateral relief pattern of the vertical multi-layer structures 94k, 94k+1. If a wet etch is employed, an etch chemistry that stops on the crystalline InP subcollector layer 92 or the InP substrate 16 can be selected. In the case of a dry etch, the etch depth may be controlled by timing or by using an in-situ interferometric or plasma-spectroscopic technique.
The method 70 involves forming a plurality of lateral isolation trenches 108 that cut through the subcollector layer 92 so that the bottoms of different ones of the vertical multi-layer structures 94k, 94k+1 are not shorted together, e.g., as shown in intermediate structure 86 of
The method 70 involves forming an electrically insulating sidewall 110 around each vertical multi-layer structure 94k, 94k+1 thereby producing the intermediate structure 88 of
The method 70 involves forming both electrical interconnects 112 that serially connect the photodiodes 94k, 94k+1 together and a pair of electrodes (not shown), e.g., the inner and outer metal electrodes 6, 8 of
One of skill in the art would readily be able to determine how to modify the method 70 in order to fabricate the planar array 10 of
The method 70 involves processing steps that are readily compatible with techniques for fabricating high-speed heterojunction bipolar transistors (HBTs). For example, U.S. Pat. No. 6,911,716 and U.S. patent application Ser. No. 10/624,038, which was filed on Jul. 21, 2003 by Young-Kai Chen et al, may describe some such techniques for fabricating HBTs. This patent and patent application are incorporated herein by reference in their entirety. In light of the above disclosure, one of skill in the art would be able to easily monolithically integrate high-power planar arrays of photodiodes as described herein and high-speed electronics circuitry on the same planar substrate.
The method 120 includes illuminating the planar array of photodiodes while the photodiodes are electrically connected in series (step 122). Preferably, the illuminating step involves illuminating a backside of a transparent substrate that supports the planar array where the backside is opposite the side of the substrate supporting metallization. Then, the metallization layers can be positioned to not interfere with the detection of the illuminating light beam by the photodiodes. The illuminating step may also involve illuminating a back-to-back stack of photodiodes over the planar substrate, e.g., as shown in
The method 120 includes producing an electrical signal from the output electrodes of the planar array while the planar array is illuminated by the light beam (step 124). The voltage or current associated with the produced electrical signal is indicative of an intensity of the light beam being detected by the planar array.
In some embodiments, the method 120 also includes optical modulating a data or analog signal carrying high frequency electrical signal onto an optical carrier, e.g., a modulated RF signal. The produced modulated optical carrier is used to illuminate the planar array of photodiodes at above step 112. In such embodiments, the method 120 may also involve driving an antenna with the electrical signal produced at above step 124. That is, these embodiments provide for operating a wireless transmission system, e.g., the wireless transmission system 40 of
The invention is intended to include other embodiments that would be obvious to one of skill in the art in light of the description, figures, and claims.
This application claims the benefit of U.S. provisional application No. 60/______, entitled “Planar Arrays of Photodiodes” and filed on Dec. 11, 2007 by Young-Kai Chen, Vincent Etienne Houtsma, Andreas Bertold Leven, and Nils Guenter Weimann, which is incorporated herein in its entirety.
Number | Date | Country | |
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61007138 | Dec 2007 | US |