Patent Application
20070285353
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:
In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
The address driver circuit 32 applies address-voltage pulses responsive to the display data to address electrodes Al through Am in synchronization with the clock signal. The Y-electrode drive circuit 33 drives Y electrodes Yl through Yn independently of each other. The X-electrode drive circuit 34 drives X electrodes Xl through Xn all together.
Waveforms for driving the address electrodes, Y electrodes, and X electrodes through the operations of the address driver circuit 32, the Y-electrode drive circuit 33, and the X-electrode drive circuit 34 are the same as those used in the related-art configuration as shown in
In the reset period, the reset/address-voltage generating circuit 43 of the Y-electrode drive circuit 33 generates a reset voltage, so that the scan driver circuit 41 applies the reset voltage to all the Y electrodes Yl through Yn. Further, a reset voltage generated by the reset/address-voltage generating circuit 46 of the X-electrode drive circuit 34 is applied to all the X electrodes Xl through Xn.
In the address period, the scan driver circuit 41 drives the Y electrodes Yl through Yn successively one by one based on the address voltage generated by the reset/address-voltage generating circuit 43, and, in conjunction therewith, the address driver circuit 32 applies address-voltage pulses for one horizontal line responsive to the display data to the address electrodes Al through Am. Cells to be displayed are selected in this manner, thereby controlling the display/non-display (selection/non-selection) of each display cell (pixel) 48.
In the sustain period, sustain voltage pulses generated by sustain pulse circuit 42 are applied to the Y electrodes Y1 through Yn via the scan driver circuit 41, and sustain voltage pulses generated by the sustain pulse circuit 45 are applied to the X electrodes Xl through Xn from the X-electrode drive circuit 34. The application of these sustain voltage pulses generates sustain discharge between an X electrode and a Y electrode at the cells selected as display cells. The address electrodes Al through Am, X electrodes Xl through Xn, and Y electrodes Yl through Yn are disposed between a front glass substrate and a rear glass substrate of the display panel 31. Further, partition walls are provided between the address electrodes Al through Am.
In the plasma display apparatus as described above, the number of light emissions of each display cell may be controlled to achieve the displaying of gray-scale tones. Electric discharge in the plasma display apparatus can assume only one of the two states, i.e., either the ON-state or the OFF-state, so that the number of light emissions is controlled to represent the level of brightness, i.e., gray-scale tones. To this end, one frame is divided into a plurality of sub-fields (e.g., 10 sub-fields). Each sub-field is constituted by a reset period, an address period, and a sustain period, and the length of the sustain period, i.e., the number of light emissions, is made to vary from sub-field to sub-field. For example, the ratio of the lengths of the sustain periods from the first sub-field to the tenth sub-field may be set to 1:2:4:8: . . . :512. One or more sub-fields are selected and subjected to discharge in response to the gray-scale level of a cell to be displayed, thereby displaying the cell at the desired gray-scale level.
The Y-electrode drive circuit 33 of
As in the configuration shown in
The scan IC 10 is implemented on the scan-drive-module substrate 50 (printed circuit board). Only one scan IC 10 is shown with respect to one scan-drive-module substrate 50 for the sake of convenience of illustration. In reality, however, a plurality of scan ICs 10 (see
The operations of the Y-electrode drive circuit 33 in the reset period, the address period, and the sustain period are the same as those described in connection with
When a plasma display panel is driven in the manner as described above, a serge voltage appears on the output signal line OUT due to a potential difference between the opposing electrodes of the display panel 31 and the like because the panel to be driven behaves as a capacitive load. The serge voltage appearing on the output signal line OUT ends up being superimposed on voltage VDH of the scan IC 10.
In order to suppress this serge voltage, the Y-electrode drive circuit 33 of
However, there is a possibility of the chip ceramic condenser 52 being destroyed to result in a short-circuit state if an excessively large serge voltage is applied. The chip resistor 53 connected in series with the chip ceramic condenser 52 between VDH and GND is thus designed to have such a resistance that the resistor is destroyed in response to an excessive electric current responsive to such an excessive voltage. Namely, provision is made such that the chip resistor 53 is destroyed to result in an open-path state before the chip ceramic condenser 52 is destroyed to result in a short-circuit state. With this provision, the scan IC 10 is prevented from becoming incapable of operation by avoiding short-circuiting between VDH and GND even if an excessively large serge voltage is applied.
There has been a conventional configuration in which a large film condenser is inserted between VDH and GND as previously described. No configuration, however, is known in which a ceramic condenser is inserted. This is because a ceramic condenser has a low tolerance level whereas a film condenser has a high, superior tolerance level. Under the conditions in which a high voltage such as 120 V in a stable state and reaching even 150 V due to a serge voltage is applied as between VDH and GND, it was conventionally an inevitable choice to use a film condenser that would be unlikely to be destroyed because of its high, superior tolerance level. The use of a ceramic condenser having a low tolerance level is fraught with a danger of destruction, which would result in a short-circuit state that incapacitates the operation of the scan IC 10.
In the present invention, a series connection of a ceramic condenser and a resistance is used to provide a configuration that provides an open-path state upon destruction, thereby making it viable to use a ceramic condenser.
A ceramic condenser as used in the present invention is inexpensive compared with a film condenser that was conventionally used, thereby helping to achieve cost reduction.
It should be noted that there is no chip-shape film condenser, and all film condensers are of the type that has connection nodes extending from a disc portion. Conventionally, a film condenser the size of a 2-cm-x-2-cm square, for example, is used for the serge-voltage suppressing purpose. The chip ceramic condenser 52 used in the present invention, on the other hand, is a ceramic condenser having a chip shape with a laminated structure, and may have a size of 2 mm by 1.25 mm, for example. The use of the chip ceramic condenser 52 thus helps to reduce the circuit size. Further, with chip shape, a stress applied to the condenser is small at the time of mounding on a substrate, thereby lowering the possibility of the component being damaged.
In this manner, the present invention uses the filter circuit 51 comprised of a series connection of the chip ceramic condenser 52 and the chip resistor 53 that is positioned in a close proximity of the scan IC 10 between VDH and GND to suppress a serge voltage, thereby making it possible to ensure the use of the scan IC 10 in a low-stress-level condition at a voltage sufficiently lower than the maximum tolerable voltage. This achieves a circuit configuration ensuring sufficient derating and high reliability with respect to the scan IC 10 by using a low-cost, small-size circuit.
In the operation of the related-art Y-electrode drive circuit shown in
In
One electrolyte condenser 26 as shown in
As previously described, a serge voltage appearing as superimposed on VDH of the scan IC 10 differs depending on the distance between the electrolyte condenser 26 and a scan IC 10, i.e., depending on the length of the above-described supply path. The serge voltage is relatively small in a scan IC 10 that is positioned at a short distance from the electrolyte condenser (voltage supply source) 26, i.e., in a scan IC 10 that has a short supply path. On the other hand, the serge voltage is relatively large in a scan IC 10 that is positioned at a long distance from the electrolyte condenser (voltage supply source) 26, i.e., in a scan IC 10 that has a long supply path.
In an example shown in
In this manner, the filter circuit 51 may be provided only with respect to some scan ICs 10 that are positioned at relatively long distances from the electrolyte condenser 26 among all the scan ICs 10. This can further reduce the cost and circuit size compared with a case in which the filter circuit 51 is provided in all the scan ICs 10. If a serge voltage is not ignorable in the scan ICs 10 (e.g., IC4, IC5, IC6, and IC7 in the example shown in
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
Although the embodiments described above have been directed to a configuration in which the filter circuit is provided in a scan IC of the Y-electrode drive circuit, the present invention is not limited to its application to a scan IC of the Y-electrode drive circuit. When a given IC is used in a condition where a high power supply voltage exceeding approximately 50 V is applied with a superimposed serge voltage, the filter circuit of the present invention can be utilized regardless of the type of the IC to suppress the serge voltage.
The present application is based on Japanese priority application No. 2006-159943 filed on Jun. 8, 2006, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-159943 | Jun 2006 | JP | national |
