This nonprovisional application claims priority under 35 U.S.C. §119(a) from Patent Application No. 10-2005-0028735 filed in Korea on Apr. 6, 2005 the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
Embodiments of the present invention relate to a plasma display apparatus that includes an arrangement of channels of data drive integrated circuits. Embodiments of the present invention may match data signals to respective regions when a total number of address electrodes on a plasma display panel that is driven in the state of being divided into two regions is different from a number of channels included in all data drive integrated circuits.
2. Background of Related Art
In a plasma display panel, a barrier rib formed between a front panel and a rear panel may form one unit cell. Each cell may be filled with a main discharge gas, such as neon (Ne), helium (He) or a mixed gas (Ne+He) of Ne and He, and an inert gas containing a small amount of xenon. When a discharge is generated using a high frequency voltage, the inert gas may generate vacuum ultraviolet rays and excite phosphors formed between the barrier ribs, thus displaying an image. Such plasma display panels may be thin and light-weight and, thus, are attracting attention as next-generation display devices.
Embodiments of the present invention may provide a plasma display apparatus and driving method thereof, wherein data signals can be effectively matched on an address-electrode-line basis without a complicated data processing process by improving the arrangement of use channels and non-use channels (or dummy channels) of data drive ICs.
In accordance with an embodiment of the present invention, a plasma display apparatus may be provided that includes a plasma display panel including first and second address electrode groups that correspond to first and second screen regions, respectively, and that match each other. First data drive ICs including channels connected to the first address electrode group are provided and second data drive ICs including channels connected to the second address electrode group are also provided. An nth channel of a first data drive IC from a first side of the first screen region is a dummy channel, an nth channel from a second side of the first screen region is the dummy channel, and an nth channel of a second data drive IC from a first side of the second screen region, which matches the first side of the first screen region, is also a dummy channel.
In accordance with an example embodiment of the present invention, a method is provided of driving a plasma display apparatus. This may include applying data to first data drive ICs and rearranging the data so that second region data that are applied from second data drive ICs to a second address electrode group match first region data that are applied from the first data drive ICs to a first address electrode group. The rearranged data may be applied to the second data drive ICs.
When a total number of address electrodes on a plasma display panel that is driven in the state of being divided into two regions is different from the number of channels included in all data drive ICs, data signals applied to the respective regions can be matched by improving the arrangement of use channels of the data drive ICs.
Other objects, advantages and salient features will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
Arrangements and embodiments of the present invention will be described in detail with reference to the following drawings, in which like numerals refer to like elements and wherein:
a to 8c illustrate a sequence of data signals so as to match data signals according to an example arrangement;
a to 10c are diagrams illustrating controlling a sequence of data signals so as to match the data signals in the arrangement of
a to 12c are diagrams illustrating controlling and driving a sequence of data signals in order to match data signals in the plasma display apparatus of
a to 18c are diagrams illustrating structure of the data drive IC A in which channels are divided into valid channels and dummy channels in the arrangement of
Arrangements and preferred embodiments of the present invention are described below in more detail with reference to the drawings.
As shown in
The front panel 100 includes pairs of scan electrodes 102 and sustain electrodes 103 that are used to produce a mutual discharge in each discharge cell and maintain the light emission of the discharge cell. That is, each of the scan electrodes 102 and each of the sustain electrodes 103 include a transparent electrode “a” made of a transparent ITO material and a bus electrode “b” made of a metallic material. The scan electrodes 102 and the sustain electrodes 103 are covered with at least one upper dielectric layer 104 that limits a discharge current and insulates the electrode pairs. A protection layer 105 on which magnesium oxide (MgO) is deposited to easily produce discharge conditions is formed on the entire surface of the upper dielectric layer 104.
Stripe type (or a well type) barrier ribs 112 for forming a plurality of discharge spaces (i.e., discharge cells) are arranged in parallel on the rear panel 110. Furthermore, address electrodes 113 that perform address discharges to generate vacuum ultraviolet rays are arranged parallel to the barrier ribs 112. R, G and B phosphors 114 that emit visible rays for image display upon address discharges are coated on the top surface of the rear panel 110. A lower dielectric layer 115 for protecting the address electrodes 113 is formed between the address electrodes 113 and the phosphors 114.
In such a plasma display panel, a plurality of discharge cells are formed in matrix form. The discharge cells are formed at points where the scan electrodes or the sustain electrodes cross the address electrodes. An electrode arrangement for forming a plurality of discharge cells in matrix form is described below with reference to
As illustrated in
Drive circuits are provided for applying predetermined drive signals to the electrodes of the plasma display panel 200. The drive circuits apply the drive signals to the electrodes of the plasma display panel 200, thus implementing an image. The structure in which the drive circuits are connected to the plasma display panel 200 may be referred to as a “plasma display apparatus.”
As the size of the plasma display panels increases, an address period may become excessively long and a sustain period may decrease all discharge cells are addressed using a single data drive unit. As a result, brightness implemented when the plasma display panel is driven may decrease because a total number of sustain pulses decreases.
A dual scan method may be used in which one plasma display panel is divided into two regions and the two regions are respectively addressed so as to prevent the address period from increasing excessively. An example of this method will be described with reference to
A connection structure of drive units in a dual scan method will be described with reference to
As shown in
Furthermore, a plurality of data drive integrated circuits (ICs) 406 for driving the address electrodes of the region A 401 and a plurality of data drive ICs 407 for driving the address electrodes of the region B 402 are connected to the plasma display panel 400.
In the structure, when data aligned by the first data alignment unit 404 are supplied to the data drive ICs 406, the data drive ICs 406 apply the aligned data to the address electrodes of the region A 401. Furthermore, data aligned by the second data alignment unit 405 are supplied to the address electrodes of the region B 402 through the data drive ICs 407. That is, one address electrode may be divided into two regions and the divided electrodes of the two regions may be respectively driven by different data drive ICs. An example of images implemented in the plasma display apparatus will be described with reference to
As shown in
An example of a method of matching data signals will be described below with reference to
Referring to
Accordingly, the supply directions of the data signals supplied from the second data alignment unit 605 may be set opposite to the supply direction of the data signals supplied from the first data alignment unit 604. This will be described with reference to
As shown in
In order to deal with unmatched data signals, a sequence of the data signals may be controlled in the second data alignment unit 705. This method will be described below with reference to
a to 8c illustrate controlling sequence of data signals so as to match data signals according to an example arrangement. Other arrangements are also possible.
a illustrates data supply paths before a sequence of data signals is controlled. That is, a plasma display panel 800 may be driven in a state of being divided into two regions 801 and 802. If data drive ICs for supplying data signals to the region 801 are set to a total of four data drive ICs A, B, C and D 806 and data drive ICs for supplying data signals to the region 802 are set to a total of four data drive ICs A, B, C and D 807, then the data supply directions of the first data alignment unit 804 and the second data alignment unit 805 may be opposite to each other. Consequently, the data signals supplied to the data drive ICs A, B, C and D 806 and the data signals supplied to the data drive ICs A, B, C and D 807 are opposite to each other.
As shown with respect to
As shown with respect to
As a result, data signals supplied from the first data alignment unit 804 and data signals supplied from the second data alignment unit 805 may be matched via a two-step data correction process (or hereafter called a data correction process).
However, this method of matching data signals through the two-step data correction process may be applied only to a case where a total number of electrode lines of a plasma display panel and a total number of channels included in all of the data drive ICs are the same. For instance, when a total number of discharge cells is 1920 in the lengthwise direction of the plasma display panel, address electrode lines may therefore be generally provided for red, green and blue colors. The total number of address electrode lines may therefore be 1920×3=5760. In an example where data drive ICs each having 192 channels are used, the total number of address electrode lines may be 192×30=5760 when a total of 30 data drive ICs are used. Accordingly, the method of
However, if one data drive IC has 256 channels and a total number of address electrode lines of one plasma display panel is 5760, data signals can be applied to the 5760 address electrode lines only when the number of data drive ICs is at least 23. This case will be described below with reference to
However, when the total number of data drive ICs each having the 256 channels is 23, the number of channels exceeds the number of address electrode lines by 128. In order to process the surplus channels, the number of which corresponds to a number by which the number of channels exceeds the total number of address electrode lines in any one data drive IC, non-use channels are provided as shown in
A method of controlling the sequence of data signals in order to match the data signals is described below with reference to
As shown in
In this arrangement, as in
As shown in
In
The arrangement sequence of the data of the data drive IC A 1007 is 1, 2, 3 and 4, which is the same as that of the data drive IC A 1006 in
However, in this method, a data processing process may be excessively complicated, and errors may be generated in the data processing process. Thus, there is a possibility that picture quality may degrade. Furthermore, there is a problem that reliability of a plasma display panel can be degraded due to errors generated in the process of electrically connecting the data drive ICs to the address electrode lines.
A plasma display apparatus according to example embodiments of the present invention will now be described.
The plasma display panel 1100 has a plurality of address electrodes formed therein. The plasma display panel 1100 is driven with its screen region divided into a first screen region and a second screen region (e.g., a region A 1101 and a region B 1102). Address electrodes corresponding to the first screen region are referred to as “a first address electrode group” and address electrodes corresponding to the second screen region are referred to as “a second address electrode group”.
The first data alignment unit 1104 applies aligned data signals to data drive ICs (A, B, C, . . . , D, E and F) connected to the address electrodes of the region A 1101 on the plasma display panel 1100 (i.e., the first address electrode group). Data drive ICs A connected to the address electrode group corresponding to the region A 1101 of the screen region of the plasma display panel 1100 may be referred to as “first data drive ICs” or “a first plurality of data drive ICs.”
The second data alignment unit 1105 applies aligned data signals to data drive ICs (A, B, C, . . . , D, E and F) connected to the address electrodes of the region B 1102 on the plasma display panel 1100 (i.e., the second address electrode group). Data drive ICs A connected to the address electrode group corresponding to the region B 1102 of the screen region of the plasma display panel 1100 may be referred to as “second data drive ICs” or “a second plurality of data drive ICs.”
The number of data drive ICs (i.e., the number of channels of the first data drive ICs and the number of channels of the second data drive ICs) are preferably the same.
Furthermore, the plurality of data drive ICs A, B, C, D, E and F including the plurality of channels are electrically connected to the address electrodes (i.e., the first address electrode group and the second address electrode group) in the two regions (i.e., the region A 1101 and the region B 1102) of the plasma display panel 1100. The plurality of channels in one or more of the plurality of data drive ICs are divided into dummy channels and valid channels.
“Dummy channels” refers to channels that are not connected to the first and second address electrode groups or to which data are not supplied. Furthermore, “valid channels” refers to channels other than the dummy channels.
If the nth channel of the first data drive IC, which is connected to the first address electrode group corresponding to the first screen region (i.e., the A region 1101) of the plasma display panel 1100, from one side of the first screen region (i.e., the A region 1101) is a dummy channel, an nth channel from the other side of the first screen region (i.e., the region A 1101) is also a dummy channel, and the nth channel of the second data drive IC from one side of the second screen region (i.e., the region B 1102) that matches the one side of the first screen region is also a dummy channel. For example, if a third channel from the left end in the first screen region (i.e., the region A 1101) of the plasma display panel 1100 is a dummy channel, a third channel from the right end of the region A 1101 is also a dummy channel. Further, a third channel from the left end of the second screen region (i.e., the region B 1102) of the plasma display panel 1100 is also a dummy channel.
If the plasma display panel 1100 has a symmetrical structure around a center thereof, a data drive IC having valid channels and dummy channels has a structure in which the dummy channels are symmetric to other data drive ICs horizontally and vertically around a center of the plasma display panel 1100. For example, in the
Consequently, a total number of dummy channels of the first data drive ICs in the first screen region (i.e., the region A 1101) of the plasma display panel 1100 is preferably the same as a total number of dummy channels of the second data drive ICs in the second screen region (i.e., the region B 1102).
As described above, the number of data drive ICs arranged in the first screen region and the second screen region (i.e., the region A 1101 and the region B 1102) of the plasma display panel 1100 may be at least four.
Also, the number of channels of an mth first data drive IC from one side of the first screen region (i.e., the region A 1101) of the screen region of the plasma display panel 1100 is the same as the number of channels of an mth first data drive IC from the other side of the first screen region and the number of channels of an mth second data drive IC from one side in the second screen region that matches the one side of the first screen region.
As an example, in
Also, one or more of the plurality of first data drive ICs and one or more of the plurality of second data drive ICs have one or more dummy channels, respectively.
Furthermore, the number of dummy channels of one of the first data drive ICs, which includes one or more dummy channels and is located at an mth location from one side of the first screen region, is the same as the number of dummy channels of another first data drive IC, which includes one or more dummy channels and is located at an mth location from the other side of the first screen region, and is the same as the number of dummy channels of one of the second data drive ICs, which includes one or more dummy channels and is located at an mth location from one side in the second screen region, which matches the one side of the first screen region.
For example, if 10 dummy channels are included in each of four of the first data drive ICs, which are arranged in the first screen region (i.e., the region A 1101) of the plasma display panel 1100, at both ends (two at each end) of the region A 1101, 10 dummy channels may be included in each of four of the second data drive ICs, which are arranged in the second screen region (i.e., the region B 1102) of the plasma display panel 1100 at both ends (two at each end) of the region B 1102.
The arrangement of dummy channels of one of the first data drive ICs, which includes one or more dummy channels and is located at an mth location from one side of the first screen region, may be the same as the arrangement of dummy channels of one of the first data drive ICs, which includes one or more dummy channels and is located at an mth location from the other side of the first screen region, and also may be the same as the arrangement of dummy channels of one of the second data drive ICs, which includes one or more dummy channels and is located at an mth location from one side in the second screen region that matches the side of the first screen region.
For example, if dummy channels are arranged in a predetermined pattern in four of the first data drive ICs, which are arranged in the first screen region (i.e., the region A 1101) of the plasma display panel 1100, at both ends (two at each end) of the region A 1101, then dummy channels are arranged in the same pattern as that of the dummy channels within four of the second data drive ICs, which are arranged in the second screen region (i.e., the region B 1102) of the plasma display panel 1100, at both ends (two at each end) of the region A 1101 in the four of the second data drive ICs at both ends (two at each end) of the region B 1102.
As described above, the arrangement of the dummy channels may be symmetrical within data drive ICs each having one or more dummy channels. For example, if two of the ten channels of the data drive IC at one side end are dummy channels in the case where one data drive IC has a total of ten channels, then two channels at the other side end of the data drive IC are also dummy channels. The arrangement of the dummy channels within one data drive IC may be horizontally symmetrical.
Most preferably, the arrangement of the dummy channels in the first screen region (i.e., the region A 1101) of the plasma display panel 1100 may be horizontally symmetrical. The arrangement of the dummy channels in the second screen region (i.e., the region B 1102) may also be horizontally symmetrical. The arrangement of the dummy channels in the first screen region (i.e., the region A 1101) and the arrangement of the dummy channels in the second screen region (i.e., the region B 1102) may be symmetrical around a border (or center area) that divides the first screen region (i.e., the region A 1101) and the second screen region (i.e., the region B 1102).
Furthermore, all dummy channels may be included in one of the first data drive ICs located at one side end of the first screen region (i.e., the region A 1101) and another data drive IC located at the other side end of the first screen region (i.e., the region A 1101). Further, all dummy channels may be included in one of the second data drive ICs located at one side end of the second screen region (i.e., the region B 1102) and another second data drive IC located at the other side end of the second screen region (i.e., the region B 1102).
As an example, in
The driving method of the plasma display apparatus according to an example embodiment of the present invention may include applying data to a plurality of first data drive ICs, rearranging the data so that second region data applied from a plurality of second data drive ICs to a second address electrode group match first region data applied from the first data drive ICs to a first address electrode group, and applying the rearranged data to the plurality of second data drive ICs.
The rearranging of the data will now be described in more detail. The rearranging of the data includes reversing the first region data to data respectively corresponding to the plurality of first data drive ICs, and reversing the first region data that were previously reversed to the data respectively corresponding to the plurality of first data drive ICs for every first data drive IC.
In the driving method of the plasma display apparatus according to an example embodiment of the present invention, reversing the data will be described with reference to
a to 12c are diagrams illustrating controlling and driving a sequence of data signals in order to match data signals in the plasma display apparatus of
a shows data supply paths before the sequence of data signals is controlled. That is, in the arrangement where one plasma display panel 1200 is driven in a state of being divided into two regions (i.e., a first screen region 1201 and a second screen region 1202), data drive ICs for supplying data signals to the region 1201 may be set to three data drive ICs A, B and C 1206, data drive ICs for supplying data signals to the region 1202 may be set to three data drive. ICs A, B and C 1207, and each of the data drive ICs has six channels. In such an arrangement, data supply directions of the first data alignment unit 1204 and the second data alignment unit 1205 are opposite to each other. In this arrangement, the data signals applied to the data drive ICs A, B, C 1206 and the data signals applied to the data drive ICs A, B and C 1207 are opposite to each other. At this time, the structure of use channels of the data drive IC A 1206 is symmetrical (i.e., the same as) to the structure of use channels of the data drive IC C 1206, the data drive IC A 1207 and the data drive IC C 1207. More specifically, in the data drive IC A 1206, a first channel and a sixth channel of a total of six channels are set as dummy channels, and a second channel to a fifth channel in a central portion thereof are set as valid channels. Furthermore, the data drive IC C 1206, the data drive IC A 1207 and the data drive IC C 1207 have a same arrangement as channels of the data drive IC A 1206.
In
For example, in order to match opposite data in
c shows an example of reversing the first region data, which were previously reversed to the data respectively corresponding to the plurality of first data drive ICs in
In
As a result, even when a total number of electrode lines of a plasma display panel and a total number of channels included in all of the data drive ICs are different from each other, data signals supplied from the first data alignment unit 1204 and data signals supplied from the second data alignment unit 1205 can be matched through a data correction process. This can simplify the data processing process as compared to previous and/or disadvantageous arrangements.
As described above, if the sequence of data is controlled, data supplied to the first data drive ICs and data supplied to the second data drive ICs can be applied in a same sequence from one side on the plasma display panel.
An example will now be described with reference to
In
Furthermore, the data drive IC A of the data drive ICs for applying the data signals to the region 1301 has a same arrangement of dummy channels as the first (i.e., the data drive IC A) of the data drive ICs, which supplies the data signals to the address electrodes corresponding to the second screen region (i.e., the region 1302) of the screen region of the plasma display panel 1300, from one side end of the region 1302, and also has a same arrangement of dummy channels as that of a first data drive IC (i.e., the data drive IC W) from the other side end of the region 1302.
That is,
In such an example, the detailed structure of the data drive IC A and the data drive IC W for supplying the data signals to the address electrodes corresponding to the region 1301, and the data drive IC A and the data drive IC W for supplying the data signals to the address electrodes corresponding to the region 1302 is described below with reference to
In
In
The example of
In such a case, the detailed structure of the data drive ICs A, B, C, D, E, F, G and H and the data drive ICs P, Q, R, S, T, U, V and W for supplying data signals to address electrodes corresponding to the region 1501, and the data drive ICs A, B, C, D, E, F, G and H and the data drive ICs P, Q, R, S, T, U, V and W for supplying data signals to address electrodes corresponding to the region 1502 will be described below with reference to
Referring to
In
Accordingly, the number of valid channels of all the channels of the data drive ICs for supplying the data signals to the address electrodes corresponding to the region 1701 is (256×23)−{(6×16)+(4×6)+(8×1)}=5760. As described above, in all the data drive ICs, channels may be divided into valid channels and dummy channels. This may allow for more stabilized driving as compared to the example of
The structures of the data drive ICs are described below in detail with reference to
Referring to
Referring to
Referring to
A plasma display apparatus has been described in detail according to an example embodiment of the present invention in which a dual scan method is applied and in which a plasma display panel serving as the display surface is scanned in a state of being divided into two regions. This method may be more effective when the size of the plasma display panel is relatively large.
While embodiments of the present invention have been described with respect to a plasma display panel, the present invention may also be applied to flat panel displays such as Liquid Crystal Displays (LCD), Organic Light Emitting Diodes (OLED) and Field Emission Displays (FED).
For example, in a LCD, a plurality of pixels for displaying an image may be formed in the LCD similar to in the plasma display panel. The LCD includes electrodes for supplying image data to these pixels and drive units. Further, as the size increases, the LCD may be disadvantageous in scanning all pixels through one scanning process in terms of noise generation in image data, scanning time, etc.
The dual scan method may therefore be applied to the LCD, where a display region is divided into two regions and the divided regions are separately scanned. As a result, dummy channels and valid channels are divided from each other in the above-described dual scan method. Therefore, embodiments are not limited to a plasma display panel, but can be applied to other flat panel displays such as LCDs.
Various features and embodiments will now be described. Each of these features and/or embodiments is merely exemplary as others are also within the scope of the present invention.
In accordance with an example embodiment of the present invention, a plasma display apparatus is provided that includes a plasma display panel including first and second address electrode groups that correspond to first and second screen regions, respectively, and that match each other. First data drive ICs including channels connected to the first address electrode group are provided. Second data drive ICs including channels connected to the second address electrode group are also provided. An nth channel of a first data drive IC from a first side of the first screen region is a dummy channel, an nth channel from a second side of the first screen region is a dummy channel, and an nth channel of a second data drive IC from a first side of the second screen region, which matches the first side of the first screen region, is also a dummy channel.
Dummy channels are channels that are not connected to the first and second address electrode groups or to which data is not supplied. Channels other than the dummy channel are valid channels to which data are supplied.
The number of first data drive ICs and the number of second data drive ICs may be identical to each other.
The number of channels of an mth first data drive IC from a first side of the first screen region may be identical to the number of channels of an mth first data drive IC from a second side of the first screen region and the number of channels of an mth second data drive IC from a first side of the second screen region, which matches the first side of the first screen region.
The first data drive ICs and the second data drive ICs may be plural in number.
The number of channels of the first data drive ICs and the number of channels of the second data drive ICs may be identical to each other.
One or more of the first data drive ICs and one or more of the second data drive ICs may each include one or more dummy channels.
The dummy channels may have an arrangement that is horizontally symmetrical within a data drive IC.
The number of dummy channels of an mth first data drive IC from a first side of the first screen region, which has one or more dummy channels, may be identical to the number of dummy channels of an mth first data drive IC from a second side of the first screen region, which has one or more dummy channels, and the number of dummy channels of an mth second data drive IC from a first side of the second screen region matching the first side of the first screen region, which has one or more dummy channels.
An arrangement of dummy channels of an mth first data drive IC from a first side of the first screen region, which has one or more dummy channels, may be identical to an arrangement of dummy channels of an mth first data drive IC from the second side of the first screen region, which has one or more dummy channels, and an arrangement of dummy channels of an mth second data drive IC from the first side of the second screen region matching the first side of the first screen region, which has one or more dummy channels.
Each of the first data drive ICs and each of the second data drive ICs may include one or more dummy channels.
All channels of at least one of the first data drive ICs and all channels of at least one of the second data drive ICs may be valid channels to which data are supplied.
One of the first data drive ICs located at a first side end in the first screen region and another first data drive IC located at a second side end of the first screen region may include all dummy channels. One of the second data drive ICs located at a first side end of the second screen region and another second data drive IC located at a second side end of the second screen region may include all dummy channels.
A total number of dummy channels of the first data drive ICs in the first screen region may be identical to a total number of dummy channels of the second data drive ICs in the second screen region.
An arrangement of the dummy channels in the first screen region may be horizontally symmetrical. An arrangement of the dummy channels in the second screen region may be horizontally symmetrical. An arrangement of the dummy channels in the first screen region and an arrangement of the dummy channels in the second screen region may be symmetrical to each other around a border between the first screen region and the second screen region.
Each of the first data drive ICs and the second data drive ICs may be four or more in number.
Embodiments of the present invention may provide a method of driving a plasma display apparatus. This may include applying data to the first data drive ICs and rearranging the data so that second region data that are applied from the second data drive ICs to the second address electrode group match first region data that are applied from the first data drive ICs to the first address electrode group. The rearranged data may be applied to the second data drive ICs.
Rearranging the data may include reversing the first region data to data corresponding to the first data drive ICs, respectively; and reversing the first region data that are reversed to the data corresponding to the first data drive ICs, for every first data drive IC.
The data applied to the first data drive ICs and the data applied to the second data drive ICs may be applied in an identical sequence from a first side of a plasma display panel.
The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
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