Information
-
Patent Grant
-
6538389
-
Patent Number
6,538,389
-
Date Filed
Monday, November 19, 200123 years ago
-
Date Issued
Tuesday, March 25, 200321 years ago
-
Inventors
-
Original Assignees
-
Examiners
Agents
-
CPC
-
US Classifications
Field of Search
US
- 315 1691
- 315 1692
- 315 1694
- 345 66
- 345 67
- 345 68
- 345 204
- 345 205
- 345 213
- 345 214
-
International Classifications
-
Abstract
A plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first drive circuit which applies an electric discharge voltage to the plurality of first electrodes, a second drive circuit which applies an electric discharge voltage to the plurality of second electrodes, and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes, and each of which has a conductive plate layer overlapping at least part of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines by eddy currents generated in the conductive plate layer in response to currents running through the wiring lines.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to plasma display apparatuses, and particularly relates to a plasma display apparatus that has an improved display quality.
2. Description of the Related Art
Plasma display panels have two glass plates on which electrodes are formed, and discharge-purpose gas fills the gap between the two glass plates that is in the order of 100 microns. Voltages higher than a discharge threshold voltage are applied between the electrodes to start gas discharge, and ultraviolet light generated from the discharge induces the light emission of photo florescent provided on the plate, thereby effecting screen displaying.
FIG. 1
is a diagram showing a schematic configuration of a plasma display apparatus.
A display panel
10
includes X electrodes
11
and Y electrodes
12
disposed in parallel, and further includes address electrodes
13
disposed in perpendicular thereto. The X electrodes
11
and the Y electrodes
12
are used to provide sustain discharge for display-purpose light emission. Voltage pulses are applied between the X electrodes
11
and the Y electrodes
12
, thereby carrying out sustain discharge. Further, the Y electrodes
12
serve as scan-purpose electrodes for writing display data. The address electrodes
13
are used to select display cells
15
that are to emit light. A voltage for writing discharge is applied between the Y electrodes
12
and the address electrodes
13
so as to select discharge cells. Shields
14
are provided between the address electrodes
13
for the purpose of separating the discharge cells
15
.
Discharge of a plasma display panel can only assume either one of the “on” state and the “off” state, so that the density, i.e., the gray scale, is represented by the number of repeated light emissions. To this end, a frame is divided into 10 sub-fields, for example. Each sub-field is comprised of a reset period, an address period, and a sustain discharge period. During the reset period, all cells are equally initialized regardless of lighting status in the previous sub-fields, e.g., are placed in the condition in which wall charge is erased. During the address period, selective discharge (addressing discharge) is performed to select the on/off states of cells in accordance with display data, thereby selectively generating wall charge that places cells in the “on” state. During the sustain discharge period, discharge is repeated in the cells where addressing discharge was performed to generate wall discharge, thereby emitting light. The length of the sustain discharge period, i.e., the number of repeated light emissions, differs from sub-field to sub-field. For example, ratios of the numbers of light emissions from the first sub-field to the tenth sub-field are set to 1:2:4:8: . . . :512, respectively. Sub-fields are then selected in accordance with the luminance level of a display cell to be subjected to gas discharge, thereby achieving a desired gray scale level.
FIG. 2
is a drawing showing another configuration of a display panel unit different from that of FIG.
1
.
In a display panel unit
10
A of
FIG. 2
, X electrodes
11
A and Y electrodes
12
A serving as display electrodes are provided in turn at equal intervals so as to cross address electrodes
13
A. All gaps between the electrodes are utilized as display lines (L
1
, L
2
, . . . ). This configuration is called an ALIS (alternate lightning of surfaces) method, and is disclosed in Japanese Patent No. 2801893. Since all the gaps between the electrodes are utilized as display lines, the number of electrodes is half as many as that of
FIG. 2
, which provides a basis for a cost reduction and a scale reduction.
Since all the gaps between electrodes serve as display lines in the ALIS method, it is impossible to light up all the display lines simultaneously. Lighting of odd-number lines (L
1
, L
3
, . . . ) and even-number lines (L
2
, L
4
, . . . ) are temporally separated to effect displaying. In the ALIS method, One frame is divided into two fields, each of which is comprised of a plurality of sub-fields. The first field is used for the displaying of odd-number lines, and the second field is used for the displaying of even-number lines.
FIG. 3
is a drawing showing a configuration of a related-art plasma display apparatus.
The plasma display apparatus of
FIG. 3
includes a plasma display panel
20
, a Y electrode drive circuit
21
, an X electrode drive circuit
22
, an address electrode drive circuit
23
, a discrimination decision circuit
24
, a memory
25
, a control circuit
26
, and a scanning circuit
27
.
A vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock signal Clock, and RGB signals each comprised of 8 bits and serving as data signals are supplied to the discrimination decision circuit
24
. The discrimination decision circuit
24
writes RGB data in the memory
25
as display data in response to the vertical synchronizing signal Vsync. The control circuit
26
controls the Y electrode drive circuit
21
, the X electrode drive circuit
22
, the address electrode drive circuit
23
, and the scanning circuit
27
, and displays the display data stored in the memory
25
on the plasma display panel
20
. In conjunction with this, the scanning circuit
27
scans the Y electrodes Y
1
through Yn, and the address electrode drive circuit
23
drives the address electrodes A
1
through An, thereby together effecting writing electric discharge for writing data in the plasma display panel
20
. In the display cells where data were written, further, sustain electric discharge is generated between the Y electrodes Y
1
through Yn and the X electrodes X
1
through Xn by the Y electrode drive circuit
21
and the X electrode drive circuit
22
.
In the related-art configuration shown in
FIG. 3
, lines y
1
through yn that extends from the Y electrode drive circuit
21
to the scanning circuit
27
to be connected to the Y electrodes Y
1
through Yn take different wiring paths between the Y electrode drive circuit
21
and the scanning circuit
27
, so that they have different wire lengths. In the example of
FIG. 3
, similarly, the X electrodes X
1
through Xn extending from the X electrode drive circuit
22
to the plasma display panel
20
take different wiring paths to have different wire lengths. The line y
1
and the Y electrode Y
1
connected thereto both having long wiring lengths have wiring resistance and wiring inductance larger than those of the line y
3
and the Y electrode Y
3
connected thereto both having relatively short wiring lengths. By the same token, the X electrode X
1
having a long wiring length has wiring resistance and wiring inductance larger than those of the X electrode X
3
having a relatively short wiring length. An effect of the wiring inductance is especially strong. Because of this, when an electric current runs through wiring lines and electrodes to generate electric discharge between the Y electrodes Y
1
through Yn and the X electrodes X
1
through Xn, a voltage drop occurs along the wiring lines and electrodes. The voltage drop generated in this manner differs from wiring line to wiring line and from electrode to electrode.
As a result of this voltage drop, when a sufficient margin cannot be secured for the discharge voltage of a plasma display panel with respect to the electrodes having a large voltage drop, a sufficient voltage required to light up an electric discharge may not be supplied. In such a case, a flicker of a screen or the like will appear, thereby degrading display quality.
Accordingly, the present invention is aimed at providing a plasma display panel in which a voltage drop produced in accordance with a wire length is reduced. Moreover, the present invention is aimed at providing a plasma display panel in which a variation in voltage drops produced according to wire lengths is reduced, thereby improving the quality of images.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a plasma display apparatus that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
In order to achieve the above objects according to the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first drive circuit which applies an electric discharge voltage to the plurality of first electrodes, a second drive circuit which applies an electric discharge voltage to the plurality of second electrodes, and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes, and each of which has a conductive plate layer overlapping at least part of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines by eddy currents generated in the conductive plate layer in response to currents running through the wiring lines.
Alternatively, the voltage fluctuation balancing units each include a reverse current line laid out along one of the wiring lines and having a current running therethrough in a direction opposite to a current running through the one of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines.
Alternatively, the voltage fluctuation balancing units each apply a voltage to at least one of the wiring lines where the applied voltage has an identical polarity to a voltage applied to the at least one of the wiring lines, thereby reducing a variation in voltage drops specific to the wiring lines.
The configurations as described above provide a plasma display panel apparatus in which a variation in voltage drops produced in accordance with wire lengths is reduced, thereby improving the quality of images.
According to another aspect of the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first drive circuit which applies an electric discharge voltage to odd-number electrodes of the plurality of first electrodes, and a second drive circuit which applies an electric discharge voltage to even-number electrodes of the plurality of first electrodes, wherein the first drive circuit and the second drive circuit have a mutually symmetrical input/output pin arrangement.
Such s symmetrical pin arrangement makes it possible to lay out wiring lines in a balanced arrangement, thereby efficiently reducing voltage drops caused by the wiring inductance and balancing the voltage drops.
According to another aspect of the present invention, a plasma display apparatus includes a plurality of first electrodes, a plurality of second electrodes which are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, a first integrated circuit which includes a high-side odd-number electrode drive circuit for supplying a high voltage to odd-number electrodes of the first electrodes and a low-side even-number electrode drive circuit for supplying a low voltage to even-number electrodes of the first electrodes, and a second integrated circuit which includes a low-side odd-number electrode drive circuit for supplying a low voltage to the odd-number electrodes of the first electrodes and a high-side even-number electrode drive circuit for supplying a high voltage to the even-number electrodes of the first electrodes.
In the invention described above, each electrode drive circuit is divided into an H-side circuitry and an L-side circuitry, and electrode drive circuits and wiring lines are arranged such that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This makes it possible to cut down the influence of wiring inductance.
According to another aspect of the present invention, a plasma display apparatus, which includes a plurality of first electrodes and a plurality of second electrodes that are arranged in substantially parallel to the plurality of first electrodes and generate electric discharge with the plurality of first electrodes at gaps therebetween, includes a plurality of blocks into which the plurality of first electrodes are divided, wherein each block is provided with an odd-number electrode drive circuit for driving odd-number electrodes of the first electrodes and an even-number electrode drive circuit for driving even-number electrodes of the first electrodes.
In the invention described above, each electrode drive circuit is divided into a plurality of circuitries, and electrode drive circuits and wiring lines are arranged such that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This makes it possible to cut down the influence of wiring inductance.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a diagram showing a schematic configuration of a plasma display apparatus;
FIG. 2
is a drawing showing another configuration of a display panel unit different from that of
FIG. 1
;
FIG. 3
is a drawing showing a configuration of a related-art plasma display apparatus;
FIG. 4
is a drawing showing a configuration of a plasma display apparatus according to the present invention;
FIGS. 5A and 5B
are drawings showing a configuration of a first embodiment of a voltage fluctuation balancing unit;
FIG. 6
is a drawing showing another example of the first embodiment of the voltage fluctuation balancing unit;
FIG. 7
is a drawing showing a configuration of a second embodiment of the voltage fluctuation balancing unit;
FIG. 8
is a drawing showing a configuration of a third embodiment of a voltage fluctuation balancing unit;
FIG. 9
is a drawing showing another example of a configuration of the plasma display apparatus according to the present invention;
FIG. 10
is a drawing showing a configuration of a fourth embodiment of the voltage fluctuation balancing unit;
FIG. 11
is a drawing showing a configuration of a fifth embodiment of the voltage fluctuation balancing unit;
FIG. 12
is a drawing showing a configuration of a sixth embodiment of the voltage fluctuation balancing unit;
FIG. 13
is a drawing showing a detailed configuration of the sixth embodiment of the voltage fluctuation balancing unit shown in
FIG. 12
;
FIG. 14
is a drawing showing a configuration of a seventh embodiment of the voltage fluctuation balancing unit;
FIG. 15
is a drawing showing a configuration of an eighth embodiment of the voltage fluctuation balancing unit; and
FIG. 16
is a circuit diagram showing a configuration of an odd-number X electrode drive circuit and an even-number X electrode drive circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 4
is a drawing showing a configuration of a plasma display apparatus according to the present invention. In
FIG. 4
, the same elements as those of
FIG. 3
are referred to by the same numerals.
The plasma display apparatus of
FIG. 4
includes the plasma display panel
20
, the Y electrode drive circuit
21
, the X electrode drive circuit
22
, the address electrode drive circuit
23
, the discrimination decision circuit
24
, the memory
25
, the control circuit
26
, the scanning circuit
27
, and voltage fluctuation balancing units
31
and
32
.
A vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock signal Clock, and RGB signals each comprised of 8 bits and serving as data signals are supplied to the discrimination decision circuit
24
. The discrimination decision circuit
24
writes RGB data in the memory
25
as display data in response to the vertical synchronizing signal Vsync. The control circuit
26
controls the Y electrode drive circuit
21
, the X electrode drive circuit
22
, the address electrode drive circuit
23
, and the scanning circuit
27
, and displays the display data stored in the memory
25
on the plasma display panel
20
. In conjunction with this, the scanning circuit
27
scans the Y electrodes Y
1
through Yn, and the address electrode drive circuit
23
drives the address electrodes A
1
through An, thereby together effecting writing electric discharge for writing data in the plasma display panel
20
. In the display cells where data were written, further, sustain electric discharge is generated between the Y electrodes Y
1
through Yn and the X electrodes X
1
through Xn by the Y electrode drive circuit
21
and the X electrode drive circuit
22
.
The voltage fluctuation balancing units
31
and
32
adjust wiring inductance and the like with respect to the Y electrodes Y
1
through Yn and the X electrodes X
1
through Xn, respectively, so that voltage drops along the wiring paths become substantially the same.
In the following, an embodiment of the voltage fluctuation balancing units
31
and
32
will be described.
FIGS. 5A and 5B
are drawings showing a configuration of a first embodiment of the voltage fluctuation balancing unit. The voltage fluctuation balancing unit
31
or
32
includes wiring lines S
1
through S
5
and conductive boards
35
. In the case of the voltage fluctuation balancing unit
31
for the Y electrodes Y
1
through Yn, the wiring lines S
1
through S
5
correspond to the wiring lines y
1
through yn, which are connected to the respective Y electrodes Y
1
through Yn through the scanning circuit
27
. In the case of the voltage fluctuation balancing unit
32
for the X electrodes X
1
through Xn, the wiring lines S
1
through S
5
correspond to the X electrodes X
1
through Xn. For the sake of simplicity of the figure, only 5 wiring lines are shown. In actuality, however, each one of the 5 wiring lines shown in the figure is comprised of a plurality of lines. In total, therefore, the voltage fluctuation balancing units
31
and
32
are provided with wiring lines as many as there are Y electrodes and X electrodes, respectively, in the plasma display panel
20
.
FIG. 5B
shows a layer structure of part of the voltage fluctuation balancing unit
31
or
32
.
As shown in
FIG. 5B
, the voltage fluctuation balancing unit
31
or
32
includes at least one wiring layer
36
and an eddy current layer
37
which are provided on a printed circuit board. Wiring lines (for example, S
1
and S
2
) are laid out in at least one wiring layer
36
, and the conductive board
35
is formed in the eddy current layer
37
. The conductive board
35
is made of conductive material such as copper. When a current runs through the wiring lines, an eddy current will be generated in such a direction as to cancel the magnetic field generated by the running current.
Such eddy currents are illustratively shown in
FIG. 5A
as arrows. In
FIG. 5A
, if the direction of the currents running through the wiring lines S
1
or S
5
is reversed (the direction of electric currents alternates during sustain discharge), the direction of the eddy currents illustratively shown is also reversed as a natural consequence.
When currents run through the wiring lines to generate eddy currents in such a direction as to cancel the magnetic field generated by the running currents, the wiring inductance of the wiring lines are reduced. An effect of this wiring inductance reduction increases as the lengths of the wiring lines increase. Therefore, wiring inductance is reduced greatly with respect to wiring lines having relatively long wire lengths, and is not reduced so much with respect to wiring lines having relatively short wire lengths. It is thus possible to reduce the wiring inductance by the larger extent the longer the wire length becomes. As a result, voltage drops caused by the wiring inductance of wiring lines can be adjusted to be substantially the same.
According to the voltage fluctuation balancing unit of the first embodiment as described above, it is possible to reduce the wiring inductance of each wiring line according to the wiring length thereof by utilizing an effect of the conductive board that generates an eddy current. This makes it possible to make the voltage drops by the wiring inductance substantially the same.
It should be noted that a wiring pattern of the wiring lines S
1
through S
5
does not have to extend roughly symmetrically from the center as shown in
FIG. 5A
, and may have any form.
FIG. 6
is a drawing showing another example of the first embodiment of the voltage fluctuation balancing unit. As shown in
FIG. 6
, the wiring pattern of the wiring lines S
1
through S
5
may extend to one side. As shown in these examples, the form of the wiring line pattern is not limited to any specific form.
FIG. 7
is a drawing showing a configuration of a second embodiment of the voltage fluctuation balancing unit.
The voltage fluctuation balancing unit
31
or
32
includes wiring lines S
1
and S
2
, a reverse current line
41
, and a reverse current supply unit
42
. In the case of the voltage fluctuation balancing unit
31
for the Y electrodes Y
1
through Yn, the wiring lines S
1
and S
2
correspond to the wiring lines y
1
through yn, which are connected to the respective Y electrodes Y
1
through Yn through the scanning circuit
27
. In the case of the voltage fluctuation balancing unit
32
for the X electrodes X
1
through Xn, the wiring lines S
1
and S
2
correspond to the X electrodes X
1
through Xn. For the sake of simplicity of the figure, only 2 wiring lines are shown. In actuality, however, each one of the 2 wiring lines shown in the figure is comprised of a plurality of lines. In total, therefore, the voltage fluctuation balancing units
31
and
32
are provided with wiring lines as many as there are Y electrodes and X electrodes, respectively, in the plasma display panel
20
.
The reverse current supply unit
42
supplies an electric current to the reverse current line
41
where the supplied current runs in a direction opposite to the current running through wiring line S
2
. If the direction of the current running through the wiring line S
2
is reversed (the direction of electric currents alternates during sustain discharge), the direction of the current that is supplied by the reverse current supply unit
42
to the reverse current line
41
is also reversed.
When the current runs through the wiring line S
2
, and the current is supplied to the reverse current line
41
to run in such a direction as to cancel the magnetic field generated by the former current, the wiring inductance of the wiring line S
2
is reduced. The wiring inductance is reduced with respect to the wiring line S
2
having a relatively long wire length compared to the wiring line S
1
. As a result, voltage drops caused by the wiring inductance of wiring lines can be adjusted to be substantially the same. As was described in connection with the first embodiment, the form of the wiring line pattern is not limited to any specific form in the present invention.
FIG. 8
is a drawing showing a configuration of a third embodiment of a voltage fluctuation balancing unit.
The voltage fluctuation balancing unit
31
or
32
includes wiring S
1
and S
2
and a voltage addition unit
51
. In the case of the voltage fluctuation balancing unit
31
for the Y electrodes Y
1
through Yn, the wiring lines SI and S
2
correspond to the wiring lines y
1
through yn, which are connected to the respective Y electrodes Y
1
through Yn through the scanning circuit
27
. In the case of the voltage fluctuation balancing unit
32
for the X electrodes X
1
through Xn, the wiring lines S
1
and S
2
correspond to the X electrodes X
1
through Xn. For the sake of simplicity of the figure, only 2 wiring lines are shown. In actuality, however, each one of the 2 wiring lines shown in the figure is comprised of a plurality of lines.
The voltage addition unit
51
applies an additional voltage having the same polarity as the voltage applied to the wiring line S
2
. In detail, the voltage addition unit
51
is comprised of a voltage supply sources that supplies a pulse voltage as does the Y electrode drive circuit
21
or the X electrode drive circuit
22
, and supplies the additional voltage in synchronization with the operation of the Y electrode drive circuit
21
or the X electrode drive circuit
22
so as to add this additional voltage. Along the wiring line S
2
having a relatively long wire length compared to the wiring line S
1
, the additional voltage is added to compensate for the voltage drop caused by the wiring inductance, thereby making the voltage drops of wiring lines substantially the same. In the present invention, the form of the wiring line pattern is not limited to any specific form in the present invention.
FIG. 9
is a drawing showing another example of a configuration of the plasma display apparatus according to the present invention. In
FIG. 9
, the same elements as those of
FIG. 4
are referred to by the same numerals, and a description thereof will be omitted.
The plasma display apparatus of
FIG. 9
includes the plasma display panel
20
, an odd-number Y electrode drive circuit
61
, an even-number Y electrode drive circuit
62
, an odd-number X electrode drive circuit
63
, an even-number X electrode drive circuit
64
, the address electrode drive circuit
23
, the discrimination decision circuit
24
, the memory
25
, the control circuit
26
, the scanning circuit
27
, and voltage fluctuation balancing units
31
A and
32
A. In the plasma display apparatus of
FIG. 9
, the respective electrode drive circuits for the Y electrodes and the X electrodes are each divided into a drive circuit for driving odd number electrodes and a drive circuit for driving even number electrodes. Such a configuration is suitable for driving the plasma display panel of the ALIS method shown in FIG.
2
.
In the following, embodiments of the voltage fluctuation balancing units
31
A and
32
A will be described.
FIG. 10
is a drawing showing a configuration of a fourth embodiment of the voltage fluctuation balancing unit.
The voltage fluctuation balancing unit
31
A or
32
A includes wiring lines S
1
through S
4
and a conductive board
71
. In the case of the voltage fluctuation balancing unit
31
A for the Y electrodes Y
1
through Yn, the wiring lines S
1
through S
4
correspond to the wiring lines y
1
through yn, which are connected to the respective Y electrodes Y
1
through Yn through the scanning circuit
27
. In the case of the voltage fluctuation balancing unit
32
A for the X electrodes X
1
through Xn, the wiring lines S
1
through S
4
correspond to the X electrodes X
1
through Xn. For the sake of simplicity of the figure, only 4 wiring lines are shown. In actuality, however, each one of the 4 wiring lines shown in the figure is comprised of a plurality of lines. The wiring lines S
1
and S
2
correspond to the odd number electrodes, and the wiring lines S
3
and S
4
correspond to even number wiring lines.
The conductive board
71
is made of conductive material such as copper. When currents run through the wiring lines, eddy currents will be generated in such a direction as to cancel the magnetic field generated by the running currents.
When currents run through the wiring lines to generate eddy currents in such a direction as to cancel the magnetic field generated by the running currents, the wiring inductance of the wiring lines are reduced. An effect of this wiring inductance reduction increases as the lengths of the wiring lines increase. Therefore, wiring inductance is reduced greatly with respect to wiring lines having relatively long wire lengths, and is not reduced so much with respect to wiring lines having relatively short wire lengths. It is thus possible to reduce the wiring inductance by the larger extent the longer the wire length becomes. As a result, voltage drops caused by the wiring inductance of wiring lines can be adjusted to be substantially the same.
FIG. 11
is a drawing showing a configuration of a fifth embodiment of a voltage fluctuation balancing unit.
The voltage fluctuation balancing unit
31
A or
32
A includes wiring lines S
1
through S
4
, reverse current lines
81
and
82
, and reverse current supply units
83
and
84
. The wiring lines S
1
and S
2
correspond to odd-number electrodes, and the wiring lines S
3
and S
4
correspond to the even-number electrodes. For the sake of simplicity of the figure, only 4 wiring lines are shown. In actuality, however, each one of the 4 wiring lines shown in the figure is comprised of a plurality of lines.
The reverse current supply unit
83
supplies an electric current to the reverse current line
81
where the supplied current runs in a direction opposite to the current running through wiring line S
3
. If the direction of the current running through the wiring line S
3
is reversed (the direction of electric currents alternates during sustain discharge), the direction of the current that is supplied by the reverse current supply unit
83
to the reverse current line
81
is also reversed. By the same token, the reverse current supply unit
84
supplies an electric current to the reverse current line
82
where the supplied current runs in a direction opposite to the current running through wiring line S
2
.
When currents run through the wiring lines S
2
and S
3
, and currents are supplied to the reverse current lines to run in such a direction as to cancel the magnetic field generated by the former currents, the wiring inductance of the wiring line S
2
is reduced. It is thus possible to reduce the wiring inductance with respect to the wiring lines S
2
and S
3
having relatively long wire lengths compared to the wiring lines S
1
and S
4
, thereby making voltage drops caused by the wiring inductance of wiring lines substantially the same.
FIG. 12
is a drawing showing a configuration of a sixth embodiment of the voltage fluctuation balancing unit.
The voltage fluctuation balancing unit
31
A or
32
A includes wiring lines S
1
through S
4
and voltage addition units
91
and
92
. The wiring lines S
1
and S
2
correspond to odd-number electrodes, and the wiring lines S
3
and S
4
correspond to the even-number electrodes. For the sake of simplicity of the figure, only 4 wiring lines are shown. In actuality, however, each one of the 4 wiring lines shown in the figure is comprised of a plurality of lines.
The voltage addition unit
91
applies an additional voltage having the same polarity as the voltage applied to the wiring line S
3
corresponding to the even-number electrodes. In detail, the voltage addition unit
91
is comprised of a voltage supply sources that supplies a pulse voltage as does the even-number Y electrode drive circuit
62
or the even-number X electrode drive circuit
64
, and supplies the additional voltage in synchronization with the operation of the even-number Y electrode drive circuit
62
or the even-number X electrode drive circuit
64
so as to add this additional voltage. By the same token, the voltage addition unit
92
applies an additional voltage having the same polarity as the voltage applied to the wiring line S
2
corresponding to the odd-number electrodes.
Along the wiring lines S
2
and S
3
having relatively long wire lengths compared to the wiring lines S
1
and S
4
, the additional voltage is added to compensate for the voltage drops caused by the wiring inductance, thereby making the voltage drops of wiring lines substantially the same.
FIG. 13
is a drawing showing a detailed configuration of the sixth embodiment of the voltage fluctuation balancing unit shown in FIG.
12
.
In the voltage fluctuation balancing unit
31
A or
32
A of
FIG. 13
, the voltage addition units
91
and
92
include respective switches. One terminal of a switch is connected to the wiring line S
2
or S
3
, and the other terminal is connected to a power supply pin of an electrode drive circuit. In this configuration, the voltage addition unit
91
that adds a voltage to the wiring line S
3
corresponding to the even-number electrodes is connected to the power supply pin of the odd-number Y electrode drive circuit
61
or the odd-number X electrode drive circuit
63
, and the voltage addition unit
92
that adds a voltage to the wiring line S
2
corresponding to the odd-number electrodes is connected to the power supply pin of the even-number Y electrode drive circuit
62
or the even-number X electrode drive circuit
64
.
In the following, operations of the configuration of
FIG. 13
will be described by taking the voltage fluctuation balancing unit
31
A as an example.
The voltage fluctuation balancing unit
31
A is connected to the odd-number Y electrode drive circuit
61
and the even-number Y electrode drive circuit
62
. The odd-number Y electrode drive circuit
61
supplies a voltage to the wiring lines S
1
and S
2
at predetermined timing from a capacitor C
1
connected to the power supply pin thereof. At this particular instant, the even-number Y electrode drive circuit
62
is not operating. During this operation cycle, on the X-electrode side, the odd-number X electrode drive circuit
63
is not being driven whereas the even-number X electrode drive circuit
64
is operating to supply a voltage. After this electric discharge is completed, the even-number Y electrode drive circuit
62
supplies a voltage to the wiring lines S
3
and S
4
from a capacitor C
2
connected to the power supply pin thereof, and the odd-number Y electrode drive circuit
61
is placed in an inactive state.
That is, the even-number Y electrode drive circuit
62
is not driven while the odd-number Y electrode drive circuit
61
is operating, and, conversely, the odd-number Y electrode drive circuit
61
is not driven when the even-number Y electrode drive circuit
62
is operating.
By utilizing this operation in the configuration of
FIG. 13
, the switch of the voltage addition unit
92
is turned on when the odd-number Y electrode drive circuit
61
is operating, thereby supplying electric charge from the capacitor C
2
connected to the power supply pin of the even-number Y electrode drive circuit
62
so as to add the voltage. When the even-number Y electrode drive circuit
62
is operating, on the other hand, the switch of the voltage addition unit
91
is turned on, thereby supplying electric charge from the capacitor C
1
connected to the power supply pin of the odd-number Y electrode drive circuit
61
so as to add the voltage.
Through the operations described above, a voltage addition unit is efficiently implemented by making use of the capacitors provided in a conventional configuration for the purpose of supplying power.
FIG. 14
is a drawing showing a configuration of a seventh embodiment of the voltage fluctuation balancing unit.
As described above, the even-number Y electrode drive circuit
62
is not driven while the odd-number Y electrode drive circuit
61
is operating. At this particular instant, as for the X electrodes on the opposite side, the odd-number X electrode drive circuit
63
serves as a ground end for the voltage supplied from the odd-number Y electrode drive circuit
61
, and the even-number X electrode drive circuit
64
is driven to supply a voltage, causing a current to run into the even-number Y electrode drive circuit
62
serving as a ground end. After electric discharge is performed in this manner, a current will run from the odd-number X electrode drive circuit
63
into the odd-number Y electrode drive circuit
61
placed in an inactive state, and a current will run into the even-number X electrode drive circuit
64
from the even-number Y electrode drive circuit
62
of an active state, thereby effecting electric discharge.
The configuration of
FIG. 14
can effectively prevent voltage drops caused by the wiring inductance by utilizing the operations as described above.
FIG. 14
shows the configuration of the seventh embodiment of the voltage fluctuation balancing unit by taking as an example the voltage fluctuation balancing unit
32
A provided on the side of X electrodes.
In this configuration, the odd-number X electrode drive circuit
63
is divided into a H-side odd-number X electrode drive circuit
63
-
1
serving as a voltage supply source and an L-side odd-number X electrode drive circuit
63
-
2
serving as a ground end. Further, the even-number X electrode drive circuit
64
is divided into an H-side even-number X electrode drive circuit
64
-
1
serving as a voltage supply source and an L-side even-number X electrode drive circuit
64
-
2
serving as a ground side.
At a particular discharge timing, currents are supplied to the Y electrode side from the H-side odd-number X electrode drive circuit
63
-
1
, and currents are supplied to the L-side even-number X electrode drive circuit
64
-
2
from the Y electrode side. The directions of these currents are shown by the solid lines. As can be seen in the figure, the directions of currents are opposite between adjacent wiring lines, so that voltage drops caused by the wiring inductance can be reduced.
At a next discharge timing, currents are supplied to the Y electrode side from the H-side even-number X electrode drive circuit
64
-
1
, and currents are supplied to the L-side odd-number X electrode drive circuit
63
-
2
from the Y electrode side. The directions of these currents are shown by the dotted lines. As can be seen in the figure, the directions of currents are opposite between adjacent wiring lines, so that voltage drops caused by the wiring inductance can be reduced.
In the seventh embodiment of the voltage fluctuation balancing unit as described above, each electrode drive circuit is divided into an H-side circuitry and an L-side circuitry, and electrode drive circuits and wiring lines are arranged such that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This makes it possible to cut down the influence of wiring inductance. In conventional configurations, H-side circuitry and L-side circuitry that correspond respectively to the pull-up end and the pull-down end of a push-pull circuit are provided as a single set. As a result, directions of running currents are not opposite in a given locality, so that there is a risk of having an increased inductance. In this embodiment, each electrode drive circuit is divided into the H side and the L side, thereby attaining completely opposite directions.
Although the above description has been provided by taking the X electrode side as an example, it is apparent that the same configuration is equally applicable to the Y electrode side.
FIG. 15
is a drawing showing a configuration of an eighth embodiment of the voltage fluctuation balancing unit.
FIG. 15
shows the configuration of the eighth embodiment of the voltage fluctuation balancing unit by taking as an example the voltage fluctuation balancing unit
32
A on the side of X electrodes.
In this configuration, the odd-number X electrode drive circuit
63
is divided into a first odd-number X electrode drive circuit
63
A-
1
and a second odd-number X electrode drive circuit
63
A-
2
, and the even-number X electrode drive circuit
64
is divided into a first even-number X electrode drive circuit
64
A-
1
and a second even-number X electrode drive circuit
64
A-
2
. In
FIG. 15
, a connector
95
is provided for the wiring lines that drive all electrodes in the upper half of the plasma display apparatus, and a connector
96
is provided for the wiring lines that drive all the electrodes in the lower half of the plasma display apparatus.
At a particular electric discharge timing, currents are supplied to the Y electrode side from the odd-number X electrode drive circuits
63
A-
1
and
63
A-
2
, and currents are supplied to the even-number X electrode drive circuits
64
A-
1
and
64
A-
2
from the Y electrode side. These currents are illustrated by the solid lines. As can be seen from the figure, the directions of currents are opposite between adjacent wiring lines, so that the voltage drop by the wiring inductance can be reduced. Division of each electrode drive circuit into a plurality of circuitries is significant when the connector arrangement of the electrodes extending to the plasma display panel
20
is taken into consideration. Namely, if connectors are provided at two separate positions as shown in
FIG. 15
, division of each electrode drive circuit into two circuitries makes it possible to eliminate redundant detours of wiring lines and to make the currents run in opposite directions between adjacent wiring lines, thereby suppressing an adverse effect of wiring inductance.
As described above, the seventh embodiment of the voltage fluctuation balancing unit divides each electrode drive circuit into a plurality of circuitries, and arranges each electrode drive circuit and wiring lines in such a manner that currents run in opposite directions between adjacent wiring lines at each electric discharge timing. This provides a basis for reducing the effect of wiring inductance.
Although the above description has been provided by taking the X electrode side as an example, it is apparent that the same configuration is equally applicable to the Y electrode side.
FIG. 16
is a circuit diagram showing a configuration of the odd-number X electrode drive circuit
63
and the even-number X electrode drive circuit
64
.
The odd-number X electrode drive circuit
63
of
FIG. 16
is implemented by using a power module or hybrid IC, and includes an L-side input pin
101
, an H-side input pin
102
, a ground pin
103
, an L-side output pin
104
, an H-side output pin
105
, a power supply pin
106
, switching devices
107
and
108
, and drive circuits
109
and
110
. The even-number X electrode drive circuit
64
is implemented by using a power module or hybrid IC, and includes an L-side input pin
201
, an H-side input pin
202
, a ground pin
203
, an L-side output pin
204
, an H-side output pin
205
, a power supply pin
206
, switching devices
207
and
208
, and drive circuits
209
and
210
.
The odd-number X electrode drive circuit
63
and the even-number X electrode drive circuit
64
of the present invention have pins thereof provided in a symmetrical arrangement between the odd-number X electrode drive circuit
63
and the even-number X electrode drive circuit
64
, as shown in FIG.
16
. That is, the odd-number X electrode drive circuit
63
has the ground pin thereof provided at the top and the L-side output pin thereof next to the ground pin, whereas the even-number X electrode drive circuit
64
has the ground pin thereof provided at the bottom, flanked by the L-side output pin.
Because of the symmetrical arrangement of pins as described above, it is possible to lay out the wiring lines in voltage fluctuation balancing unit
32
A in a balanced manner. This makes it easy to efficiently reduce voltage drops caused by the wiring inductance and to balance the voltage drops. Moreover, it is arranged for electric charge to easily move between the two capacitors C
1
and C
2
, so that the voltage fluctuation can be reduced.
As described hereinbefore, the present invention provides a voltage fluctuation balancing unit in order to reduce a voltage drop caused by wiring inductance. The voltage fluctuation balancing unit includes a conductive plate layer overlapping at least part of the wiring lines so as to reduce a variation in voltage drops by eddy currents generated in the conductive plate layer in response to currents running through the wiring lines. Alternatively, the voltage fluctuation balancing unit provides a reverse current to a reverse current line laid out along a wiring line, thereby reducing a variation in voltage drops. Alternatively, the voltage fluctuation balancing unit applies a voltage having the same polarity as a voltage applied to wiring lines, thereby reducing a variation in voltage drops.
The configurations as described above provide a plasma display panel apparatus in which a variation in voltage drops produced in accordance with wire lengths is reduced, thereby improving the quality of images.
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
The present application is based on Japanese priority application No. 2000-391389 filed on Dec. 22, 2000, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Claims
- 1. A plasma display apparatus, comprising:a plurality of first electrodes; a plurality of second electrodes which are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween; a first drive circuit which applies an electric discharge voltage to said plurality of first electrodes; a second drive circuit which applies an electric discharge voltage to said plurality of second electrodes; and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes, and each of which has a conductive plate layer overlapping at least part of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines by eddy currents generated in the conductive plate layer in response to currents running through the wiring lines.
- 2. A plasma display apparatus, comprising:a plurality of first electrodes; a plurality of second electrodes which are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween; a first drive circuit which applies an electric discharge voltage to said plurality of first electrodes; a second drive circuit which applies an electric discharge voltage to said plurality of second electrodes; and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes, and each of which includes a reverse current line laid out along one of the wiring lines and having a current running therethrough in a direction opposite to a current running through the one of the wiring lines so as to reduce a variation in voltage drops specific to the wiring lines.
- 3. A plasma display apparatus, comprising:a plurality of first electrodes; a plurality of second electrodes which are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween; a first drive circuit which applies an electric discharge voltage to said plurality of first electrodes; a second drive circuit which applies an electric discharge voltage to said plurality of second electrodes; and voltage fluctuation balancing units which are provided for wiring lines between the first and second drive circuits and the first and second electrodes and each of which applies a voltage that has an identical polarity to a voltage applied to at least one of the wiring lines to said at least one of the wiring lines additionally, thereby reducing a variation in voltage drops specific to the wiring lines.
- 4. A plasma display apparatus, comprising:a plurality of first electrodes; a plurality of second electrodes which are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween; a first drive circuit which applies an electric discharge voltage to odd-number electrodes of said plurality of first electrodes; and a second drive circuit which applies an electric discharge voltage to even-number electrodes of said plurality of first electrodes, wherein said first drive circuit and said second drive circuit have a mutually symmetrical input/output pin arrangement.
- 5. A plasma display apparatus, comprising:a plurality of first electrodes; a plurality of second electrodes which are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween; a first integrated circuit which includes a high-side odd-number electrode drive circuit for supplying a high voltage to odd-number electrodes of the first electrodes and a low-side even-number electrode drive circuit for supplying a low voltage to even-number electrodes of the first electrodes; and a second integrated circuit which includes a low-side odd-number electrode drive circuit for supplying a low voltage to the odd-number electrodes of the first electrodes and a high-side even-number electrode drive circuit for supplying a high voltage to the even-number electrodes of the first electrodes.
- 6. A plasma display apparatus which includes a plurality of first electrodes and a plurality of second electrodes that are arranged in substantially parallel to said plurality of first electrodes and generate electric discharge with said plurality of first electrodes at gaps therebetween, comprising:a plurality of blocks into which said plurality of first electrodes are divided, wherein each block is provided with an odd-number electrode drive circuit for driving odd-number electrodes of the first electrodes and an even-number electrode drive circuit for driving even-number electrodes of the first electrodes.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000-391389 |
Dec 2000 |
JP |
|
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Number |
Name |
Date |
Kind |
6281635 |
Lee |
Aug 2001 |
B1 |
6320326 |
Shino et al. |
Nov 2001 |
B1 |
6411268 |
Nakamura et al. |
Jun 2002 |
B1 |
6456263 |
Hashimoto et al. |
Sep 2002 |
B1 |
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Number |
Date |
Country |
9-160525 |
Jun 1997 |
JP |
11-065520 |
Mar 1999 |
JP |