BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a plasma display panel;
FIG. 2 is a block diagram showing a main part of a related-art plasma display apparatus;
FIG. 3 is a drawing showing an example of a basic operation of a drive circuit;
FIG. 4 is an illustrative drawing showing an address voltage waveform applied to an address electrode and a scan voltage waveform applied to a Y electrode;
FIG. 5 is a drawing for explaining a method of displaying gray scales based on a sub-frame method;
FIG. 6 is a drawing showing an example of the circuit configuration of a scan driver IC;
FIG. 7 is a drawing showing inputs and outputs of the scan driver IC during the address period and the sustain period;
FIG. 8 is a block diagram showing a main part of a plasma display apparatus according to the present invention;
FIG. 9 is a drawing showing a first embodiment of a delaying mechanism achieved by the delay units;
FIG. 10 is a drawing showing an example of the configuration of the delay units implemented by use of a CR circuit;
FIG. 11 is a drawing showing an example of an output control signal delayed by the CR circuits having different capacitances;
FIG. 12 is a drawing showing a second embodiment of a delaying mechanism achieved by the delay units; and
FIG. 13 is a drawing showing a third embodiment of a delaying mechanism achieved by the delay units.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 8 is a block diagram showing a main part of a plasma display apparatus according to the present invention. In FIG. 8, the same elements as those of FIG. 2 are referred to by the same numerals, and a description thereof will be omitted.
A plasma display apparatus shown in FIG. 8 includes a plasma display panel 110, an address-electrode drive circuit 111, a scan driver circuit 112, a Y-electrode drive circuit 113, an X-electrode drive circuit 114, and a control circuit 115. The scan driver circuit 112 includes a plurality of scan driver ICs 120 and delay units 130. The delay units 130 are inserted into paths through which the output control signal OC or the power supply voltage VH is supplied from the Y-electrode drive circuit 113 to the scan driver ICs 120, and serve to delay the timing at which the output control signal OC supplied to the scan driver ICs 120 changes or the timing at which the electric current of the power-supply voltage VH supplied to the scan driver ICs 120 flows. At least two delay units 130 corresponding to at least two respective scan driver ICs 120 are configured to have respective delay lengths different from each other. Accordingly, the timing at which the output control signal OC changes or the timing at which the electric current of the power supply voltage VH flows differs between these two scan driver ICs 120. As a result, these two scan driver ICs 120 do not have electric currents flowing simultaneously, thereby reducing the load on the power supply of the Y-electrode drive circuit 113.
FIG. 9 is a drawing showing a first embodiment of a delaying mechanism achieved by the delay units 130. In the first embodiment shown in FIG. 9, the delay units 130 are configured to delay the timing at which the output control signal OC changes.
In FIG. 9, the output control signal OC is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a signal line 140. Further, the power supply voltage VH is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a power supply line 141. The delay units 130 are inserted into the signal line 140 in one-to-one correspondence to the scan driver ICs 120. The delay length of a delay unit 130 may be increased as the length of the signal line 140 from the Y-electrode drive circuit 113 to the scan driver IC 120 increases, for example. In this manner, the timings at which the output control signal OC supplied to the scan driver ICs 120 change are reliably dispersed.
Instead of increasing the delay length as the distance from the Y-electrode drive circuit 113 increases, the delay length may be increased as the distance from the Y-electrode drive circuit 113 decreases. Alternatively, delay lengths may be randomly assigned independently of the distance. In reality, the delay of the signal line 140 is present to some degree. Because of this, it may be preferable to use the configuration in which the longer the path of signal propagation on the signal line 140, the longer the selected delay length is, because such configuration can easily and reliably disperse the timings of the signal change. It should be noted that the delay units 130 do not have to be provided in one-to-one correspondence to all the scan driver ICs 120. Alternatively, the delay units 130 may be provided only for some but not all of the scan driver ICs 120.
CR circuits or the like, for example, may be used as the delay units 130. FIG. 10 is a drawing showing an example of the configuration of the delay units 130 implemented by use of a CR circuit. As shown in FIG. 10, each of the delay units 130 includes a resistor R and a capacitor C. Due to the presence of the capacitor C, a change in the voltage of the output control signal OC delays on the signal line 140.
FIG. 11 is a drawing showing an example of the output control signal OC delayed by the CR circuits (delay units 130) having different capacitances for the capacitor C. When the capacitance of the capacitor C is smallest, the output control signal OC assumes a rise waveform 71 and a fall waveform 81. When the capacitance of the capacitor C is largest, the output control signal OC assumes a rise waveform 73 and a fall waveform 83. In the case of a capacitance having a mid value, the output control signal OC assumes a rise waveform 72 and a fall waveform 82. The larger the capacitance, the longer the signal delay is, as illustrated. The capacitance of the CR circuit of a delay unit 130 may be increased as the length of the signal line 140 from the Y-electrode drive circuit 113 to the scan driver IC 120 increases, for example. In this manner, the timings at which the output control signal OC supplied to the scan driver ICs 120 change are reliably dispersed.
FIG. 12 is a drawing showing a second embodiment of a delaying mechanism achieved by the delay units 130. In the second embodiment shown in FIG. 12, the delay units 130 are configured to delay the timing at which the electric current of the power supply voltage VH flows.
In FIG. 12, the output control signal OC is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a signal line 140. Further, the power supply voltage VH is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a power supply line 141. The delay units 130 are inserted into the power supply line 141 in one-to-one correspondence to the scan driver ICs 120. The delay length of a delay unit 130 may be increased as the length of the power supply line 141 from the Y-electrode drive circuit 113 to the scan driver IC 120 increases, for example. In this manner, the timings at which the electric current of the power supply voltage VH supplied to the scan driver ICs 120 change are reliably dispersed. Similarly to the first embodiment, instead of increasing the delay length as the distance from the Y-electrode drive circuit 113 increases, the delay length may be increased as the distance from the Y-electrode drive circuit 113 decreases. Alternatively, delay lengths may be randomly assigned independently of the distance. Further, the delay units 130 do not have to be provided in one-to-one correspondence to all the scan driver ICs 120. Alternatively, the delay units 130 may be provided only for some but not all of the scan driver ICs 120. CR circuits or the like, for example, may be used as the delay units 130. In this case, the capacitive load is increased to increase the delay. Alternatively, an inductor may be used as a delay unit 130 to create a delay.
FIG. 13 is a drawing showing a third embodiment of a delaying mechanism achieved by the delay units 130. In the third embodiment shown in FIG. 13, the delay units 130 are configured to delay the timing at which the output control signal OC changes.
In FIG. 13, the output control signal OC is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a signal line 140. Further, the power supply voltage VH is supplied from the Y-electrode drive circuit 113 to each of the scan driver ICs 120 via a power supply line 141. The delay units 130 are inserted into the signal line 140 in one-to-one correspondence to the scan driver ICs 120. The first embodiment and the third embodiment differ from each other in the positions at which the delay units 130 are inserted. In the case of the first embodiment, the signal line 140 branches into branch signal lines that are connected to the respective scan driver ICs 120, and each of the delay units 130 is inserted into a corresponding branch signal line extending between the branch point and the scan driver IC 120. In the case of the third embodiment, on the other hand, the signal line 140 branches into branch signal lines that are connected to the respective scan driver ICs 120, and each of the delay units 130 is inserted into a position between the branch point and the Y-electrode drive circuit 113 on the trunk signal line from which the branch signal lines extend. Namely, the delay units 130 are connected in parallel to each other in the first embodiment whereas the delay units 130 are connected in series in the third embodiment.
When the delay units 130 are connected in series as shown in FIG. 13, the delay units 130 may all be configured to have the same circuit configuration and the same circuit characteristics having the same delay. Even if all the delay units 130 have the same delay length, a signal with delay T after passing through a first delay unit 130 will have a delay equal to 2 T after gaining additional delay T by passing through a second delay unit 130. Accordingly, with the configuration in which the outputs of the delay units 130 connected in series are coupled to the respective scan driver ICs 120, signal timings for the scan driver ICs 120 can be made to differ. With this provision, the timings at which the output control signal OC supplied to the scan driver ICs 120 change can be reliably dispersed.
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
The present application is based on Japanese priority application No. 2006-206679 filed on Jul. 28, 2006, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Patent Application
20080024395
