Plasma display apparatus

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to the following drawings in which like numerals refer to like elements.

FIG. 1 is a perspective view illustrating a plasma display panel according to an exemplary embodiment of the present invention;

FIG. 2 illustrates an electrode arrangement of a plasma display panel according to an exemplary embodiment of the present invention;

FIG. 3 is a timing diagram illustrating a time-division driving method based on one frame divided into a plurality of subfields, according to an exemplary embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a construction of a scan driving circuit for supplying a driving signal to a plasma display panel according to an exemplary embodiment of the present invention;

FIG. 5 is a timing diagram illustrating driving signals for driving a plasma display panel in divided one subfield according to an exemplary embodiment of the present invention;

FIG. 6 is an exploded timing diagram illustrating a setup period of a driving signal supplied to a plasma display panel;

FIGS. 7A to 7C are circuit diagrams illustrating a flow of current of a scan driving circuit in response to a driving signal supplied to a plasma display panel during a setup period;

FIG. 8 is an exploded timing diagram illustrating a setdown period of a driving signal supplied to a plasma display panel;

FIGS. 9A to 9C are circuit diagrams illustrating a flow of current of a scan driving circuit in response to a driving signal applied to a plasma display panel during a setdown period;

FIG. 10 is an exploded timing diagram illustrating an address period of a driving signal supplied to a plasma display panel;

FIGS. 11A to 11C are circuit diagrams illustrating a flow of current of a scan driving circuit in response to a driving signal applied to a plasma display panel during an address period;

FIG. 12 is an exploded timing diagram illustrating a sustain period of a driving signal supplied to a plasma display panel; and

FIGS. 13A to 13B are circuit diagrams illustrating a flow of current of a scan driving circuit in response to a driving signal applied to a plasma display panel during a sustain period.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described in a more detailed manner with reference to the drawings.

However, it is expressed that a plasma display apparatus according to the present invention can be modified by a plurality of exemplary embodiments without being limited to exemplary embodiments disclosed in this specification.

FIG. 1 is a perspective view illustrating the plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11 and a sustain electrode 12 that are a sustain electrode pair provided on an upper substrate 10, and an address electrode 22 provided on a lower substrate 20.

The sustain electrode pair 11 and 12 includes transparent electrodes 11a and 12a and bus electrodes 11b and 12b that are formed of indium-tin-oxide (ITO). The bus electrodes 11b and 12b can be provided in a laminate type of metal such as silver (Ag) and chrome (Cr) or chrome/copper/chrome (Cr/Cu/Cr), or in a laminate type of chrome/aluminum/chrome (Cr/Al/Cr). The bus electrodes 11b and 12b are provided on the transparent electrodes 11a and 12a, and serve to reduce a voltage drop caused by the high-resistant transparent electrodes 11a and 12a.

According to an exemplary embodiment of the present invention, the sustain electrode pair 11 and 12 can be comprised of not only a layered structure of the transparent electrodes 11a and 12a and the bus electrodes 11b and 12b, but also a structure in which only the bus electrodes 11b and 12b are provided without the transparent electrodes 11a and 12a. This structure does not use the transparent electrodes 11a and 12a. Thus, it is advantageous of reducing a panel manufacturing cost. The bus electrodes 11b and 12b used for this structure can be of various materials such as photosensitive material, in addition to the above materials.

A black matrix (BM) is arranged between the transparent electrodes 11a and 12a and the bus electrodes 11b and 12b of the scan electrode 11 and the sustain electrode 12. The black matrix performs a light shield function of absorbing light generated outside the upper substrate 10, and reducing a reflection light, and a function of improving a purity and a contrast of the upper substrate 10.

The black matrix according to an exemplary embodiment of the present invention is provided on the upper substrate 10, and can be comprised of a first black matrix 15 provided at a position overlapping with a barrier rib 21, and second black matrixes 11c and 12c provided between the transparent electrodes 11a and 12a and the bus electrodes 11b and 12b. The first black matrix 15, and the second black matrixes 11c and 12c that are called black layers or black electrode layers, can be simultaneously formed in their forming processes and physically connected with each other, or not.

Being physically connected and formed, the first black matrix 15 and the second black matrixes 11c and 12c are formed of same material. However, being physically separated and provided, they can be formed of different materials.

An upper dielectric layer 13 and a protective film 14 are layered on the upper substrate 10 where the scan electrode 11 and the sustain electrode 12 are provided in parallel. The upper dielectric layer 13 can perform a function of storing charged particles generated by discharge, and protecting the sustain electrode pair 11 and 12. The protective film 14 protects the upper dielectric layer 13 from sputtering of the charged particles generated at the time of gas discharge, and enhances an emission efficiency of secondary electrons. Also, the protective film 14 can be formed of oxide magnesium (MgO), or can be formed of silicon (Si)-added oxide magnesium (Si—MgO). Here, a percentage of silicon (Si) added to the protective film 14 can be about 50 ppm to 200 ppm by weight percentage (wt %).

The address electrode 22 is provided in a direction intersecting with the scan electrode 11 and the sustain electrode 12. A lower dielectric layer 23 and a barrier rib 21 are provided on the lower substrate 20 having the address electrode 22.

A phosphor layer is provided on surfaces of the lower dielectric layer 23 and the barrier rib 21. The barrier rib 21 includes a vertical barrier rib 21a and a horizontal barrier rib 21b provided in a closed type. The vertical barrier rib 21a and the horizontal barrier rib 21b physically distinguish discharge cells, and prevent ultraviolet ray and visible ray generated by the discharge from leaking to an adjacent discharge cell.

In an exemplary embodiment of the present invention, not only a structure of the barrier rib 21 shown in FIG. 1 but also a multiform structure of the barrier rib 21 is possible. For example, a differential type barrier rib structure in which the vertical barrier rib 21a and the horizontal rib 21b are different in height, a channel type barrier rib structure in which a channel used as an exhaustion passage is provided at at least one of the vertical barrier rib 21a and the horizontal barrier rib 21b, and a hollow type barrier rib structure in which hollow is provided at at least one of the vertical barrier rib 21a and the horizontal barrier rib 21b.

In the differential type barrier rib structure, it is desirable that the horizontal barrier rib 21b is great in height. In the channel type barrier rib structure or the hollow type barrier rib structure, it is desirable that the horizontal barrier rib 21b has the channel or the hollow.

In an exemplary embodiment of the present invention, it is shown and described that Red (R), Green (G), and Blue (B) discharge cells are arranged on the same line, respectively, but it also possible that they are arranged in a different type. For example, it is also possible to provide delta type arrangement in which the R, G, and B discharge cells are arranged in a triangular shape. Also, it is possible to shape the discharge cell in not only a tetragonal shape but also various polygonal shapes such as pentagonal and hexagonal shapes.

The phosphor layer is excited by the ultraviolet ray generated in the gas discharge, and generates any one of R, G, and B visible rays. An inertia mixture gas such as He+Xe, Ne+Xe, and He+Ne+Xe for discharge is injected into a discharge space provided between the upper/lower substrates 10 and 20 and the barrier rib 21.

FIG. 2 illustrates an electrode arrangement of a plasma display panel according to an exemplary embodiment of the present invention. It is desirable that a plurality of discharge cells constituting the plasma display panel is arranged in matrix as shown in FIG. 2. The plurality of discharge cells is provided at intersection portions of scan electrode lines (Y1 to Ym), sustain electrode lines (Z1 to Zm), and address electrode lines (X1 to Xn), respectively. The scan electrode lines (Y1 to Ym) can be driven in sequence or at the same time. The sustain electrode lines (Z1 to Zm) can be driven at the same time. The address electrode lines (X1 to Xn) can be divided into odd-numbered lines and even-numbered lines and driven, or can be driven in sequence.

The electrode arrangement shown in FIG. 2 is merely one exemplary electrode arrangement of the plasma display panel according to an exemplary embodiment of the present invention. Accordingly, the present invention is not limited to the electrode arrangement and a driving method of the plasma display panel shown in FIG. 2. For example, it is possible to employ even a dual scan method in which two ones of the scan electrode lines (Y1 to Ym) are scanned at the same time. Also, the address electrode lines (X1 to Xn) can be also divided into upper and lower parts at a center of the plasma display panel and driven.

FIG. 3 is a timing diagram illustrating a time-division driving method based on one frame divided into a plurality of subfields, according to an exemplary embodiment of the present invention. A unit frame can be divided into a predetermined number of subfields, for example, eight subfields (SF1, . . . ,SF8), to realize time-division grayscale display. Each of the subfields (SF1, . . . ,SF8) is divided into a reset period (not shown), an address period (A1, . . . ,A8), and a sustain period (S1, . . . ,S8).

According to an exemplary embodiment of the present invention, the reset period can be omitted from at least one of the plurality of subfields. For example, the reset period can exist only at an initial subfield, or exist only at the initial subfield and an approximately middle subfield of a whole subfield.

In each of the sustain periods (S1, . . . ,S8), the sustain pulse is alternately applied to the scan electrode (Y) and the sustain electrode (Z), and induces a sustain discharge in the discharge cells in which wall charges are formed in the address periods (A1, . . . ,A8).

A luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods (S1, . . . ,S8) of the unit frame. In case where one frame forming a single image is expressed by eight subfields and 256 grayscales, different numbers of sustain pulses may be sequentially allocated to the respective subfields at a ratio of 1:2:4:8:16:32:64:128. Luminance corresponding to 133 grayscales can be obtained by addressing cells and sustaining a discharge during a first subfield, a third subfield, and an eighth subfield.

The number of sustain discharges allocated to each subfield can be variably determined depending on weights of the subfields according to an automatic power control (APC) level.

The number of sustain discharges allocated to each subfield can be variously changed taking account of gamma characteristics or panel characteristics. For example, a grayscale level allocated to a fourth subfield can be lowered from 8 to 6, and a grayscale level allocated to a sixth subfield can be increased from 32 to 34.

FIG. 4 is a circuit diagram illustrating a construction of a scan driving circuit for supplying a driving signal to the plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the scan driving circuit includes a scan electrode 110, an energy recovery unit 120, a sustain driving unit 130, a reset driving unit 140, and a scan integrated circuit (IC) 150.

The sustain driving unit 130 includes a first power source (Vsus) for supplying a high potential sustain voltage (Vsus) during the sustain period; a sus-up switch (Sus_up) for switching and supplying a sustain voltage (Vsus) to the scan electrode 110 and a sus-down switch (Sus_dn) for switching and lowering the supplied voltage of the scan electrode 110 to a ground (GND) voltage.

In other words, in the sustain driving unit 130, the sus-up switch (Sus_up) connects with the first power source (Vsus), and the sus-down switch (Sus_dn) connects with the sus-up switch (Sus_up) and the ground (GND).

The energy recovery unit 120 includes a capacitor (Cs) for recovering and supplying the sustain voltage (Vsus) supplied to the scan electrode 110 a supply switch (ER_up) for switching and supplying the sustain voltage recovered by the capacitor (Cs), to the scan electrode 110 and a recovery switch (ER_dn) for switching and recovering the sustain voltage (Vsus) from the scan electrode 110 to the capacitor (Cs).

The reset driving unit 140 includes a setup switch (Set_up) for supplying a gradually rising setup signal to the scan electrode 110 a setdown switch (Set_dn) connecting with a negative voltage (−Vy), and supplying a setdown signal gradually falling to the negative voltage (−Vy); and a pass switch (Pass_sw) for forming a current pass path with the scan electrode 110.

The set-up switch (Set-up) has a drain connecting with the first power source (Vsus) for supplying the sustain voltage (Vsus); a source connecting with the pass switch (Pass_sw); and a gate connecting with a variable resistor (not shown). The setup switch (Set-up) generates the setup signal gradually rising depending on a variation of a resistance of the variable resistor.

The setdown switch (Set_dn) has a drain connecting with the scan IC 150 a source connecting with the negative voltage (−Vy); and a gate connecting with a variable resistor (not shown). The setdown switch (Set_dn) generates the setdown signal gradually falling depending on the variation of the resistance of the variable resistor.

The scan IC 150 includes a first switch (Q1) connecting with a second power source (Vsc) for supplying a scan voltage (Vsc); and a second switch (Q2) connecting with the first switch (Q1). The scan electrode 110 is connected between the first switch (Q1) and the second switch (Q2).

The scan IC 150 includes a first diode (D1) connecting in parallel with the first switch (Q1); and a second diode (D2) connecting in parallel with the second switch (Q2).

The first diode (D1) connects in parallel with the first switch (Q1), and has a cathode connecting to the drain of the first switch (Q1) and an anode connecting to the source. The second diode (D2) connects in parallel with the second switch (Q2), and has a cathode connecting with the drain of the second switch (Q2) and an anode connecting with the source.

The first and second switches (Q1) and (Q2) of the scan IC 150 according to the present invention not only perform a complementary operation, but also any one of the first and second switches Q1 and Q2 is sustained in an off state for a predetermined time so that they have the same cross terminal voltage, and supply a voltage to the scan electrode 110.

The predetermined time is preferably about 8 μs to 12 μs. The predetermined time refers to a time for making the cross terminal voltages of the first and second switches (Q1) and (Q2) identical before the first and second switches (Q1) and (Q2) are complementarily switched, by lowering capacitances of parasitic capacitors (not shown) provided within the first and second switches (Q1) and (Q2).

FIG. 5 is a timing diagram illustrating driving signals for driving the plasma display panel in divided one subfield according to an exemplary embodiment of the present invention.

The subfield includes a pre reset period (not shown) for forming positive wall charges on the scan electrode (Y) and forming negative wall charges on the sustain electrode (Z); a reset period for initializing the discharge cells of a whole screen, using a distribution of the wall charges formed during the pre reset period; and an address period for selecting the discharge cell; and a sustain period for sustaining a discharge of the selected discharge cell.

The reset period includes a setup period and a setdown period. In the setup period, the gradually rising setup signal is simultaneously applied to all the scan electrodes (Y), thereby inducing a micro discharge in all the discharge cells and thus, generating the wall charges. In the setdown period, the setdown signal gradually falling from a positive voltage lower than a peak voltage of the setup signal is simultaneously applied to all the scan electrodes (Y), thereby inducing an erasure discharge in all the discharge cells and thus, erasing unnecessary charges among space charges and the wall charges generated by a setup discharge.

In the address period, a negative scan signal (scan) is sequentially applied to the scan electrode (Y) and at the same time, a positive data signal (data) is applied to the address electrode (X). A voltage difference between the scan signal (scan) and the data signal (data), and a wall voltage generated during the reset period induce an address discharge, thereby selecting the cell.

In the sustain period, the sustain signal is alternately applied to the scan electrode (Y) and the sustain electrode (Z), and the sustain discharge is induced in a surface discharge type between the scan electrode (Y) and the sustain electrode (Z).

In other words, as shown in FIG. 5, the reset period is comprised of the setup period for supplying a first setup signal gradually rising from the ground (GND) to the sustain voltage (Vsus), and a second setup signal gradually rising to a sum voltage of the scan voltage (Vsc) and the sustain voltage (Vsus); and the setdown period for supplying the setdown signal falling from the second setup signal to the ground (GND) and gradually falling to the negative voltage (−Vy).

The setup period includes a first period for supplying the first setup signal; a second period for falling by a predetermined voltage from the sustain voltage (Vsus) of the first setup signal, and sustaining a fall voltage; and a third period for supplying the second setup signal that gradually rises from the fall voltage falling by the predetermined voltage of the second period to the scan voltage (Vsc).

It is desirable that the predetermined voltage is 20V to 50V at the sustain voltage (Vsus).

The setdown period includes a setdown initiation period for falling from the sum voltage of the scan voltage (Vsc) and the sustain voltage (Vsus) of the second setup signal, to the ground (GND); and a setdown start period for supplying the setdown signal gradually falling to the negative voltage (−Vy).

The setdown initiation period includes a first period for falling from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) of the setup signal; a second period for rising from the scan voltage (Vsc) to the sustain voltage (Vsus); and a third period for falling from the sustain voltage (Vsus) to the ground (GND).

In the address period, the setdown signal rises from the negative voltage (−Vy) to a scan bias voltage (Vsc−Vy), and is sustained until the scan signal is applied.

The address period includes an address initiation period. The address initiation period includes a first period for rising from the negative voltage (−Vy) by the sustain voltage (Vsus); a second period for falling from a rise voltage rising by the sustain voltage (Vsus) of the first period, to the scan bias voltage (Vsc−Vy); and a third period for sustaining the scan bias voltage (Vsc−Vy) until the scan signal is applied.

The sustain period includes a sustain initiation period for rising to the sustain voltage (Vsus) before the applying of the sustain signal for the address period.

The sustain initiation period includes a first period for rising by a predetermined voltage from the scan bias voltage (Vsc−Vy) of the address period; and a second period for rising from a rise voltage of the first period to the ground (GND).

The predetermined voltage is a difference voltage between the scan bias voltage (Vsc−Vy), and a sum voltage of the negative voltage (−Vy) and the sustain voltage (Vsus).

The driving signal shown in FIG. 5 refers to a signal for driving the plasma display panel according to a first exemplary embodiment of the present invention. The driving signal shown in FIG. 5 does not limit a scope of the present invention. For example, the pre reset period can be omitted, and the driving signals shown in FIG. 4 can change in polarity and voltage level according to need, and an erasure signal for erasing the wall charges can be applied to the sustain electrode after the sustain discharge is completed. Also, it is possible to perform single sustain driving for applying the sustain signal to only any one of the scan electrode (Y) and the sustain electrode (Z), and inducing the sustain discharge.

FIG. 6 is an exploded timing diagram illustrating a setup period of a driving signal supplied to the plasma display panel. FIGS. 7A to 7C are circuit diagrams illustrating current pass paths for a flow of current of the scan driving circuit in response to the driving signal applied to the plasma display panel during the setup period.

FIG. 6 shows a detail of an “A” range shown in FIG. 4. As shown, FIG. 6 shows the first period for supplying the first setup signal, the second period for falling by the predetermined voltage at an end time point of the first setup signal, and sustaining a fall voltage, and the third period for supplying the second setup signal in the second period.

In the first period, the pass switch (Pass_sw), the setup switch (Set_up), and the second switch (Q2) turn on, and the supply switch (ER_up), the recovery switch (ER_dn), the sus-up switch (Sus_up), the sus-down switch (Sus_dn), and the first switch (Q1) turn off, so that the scan driving circuit supplies the first setup signal to the scan electrode 110.

In the second period, the pass switch (Pass_sw) and the recovery switch (ER_dn) turn on, and the setup switch (Set_up), the supply switch (ER_up), the sus-up switch (Sus_up), the sus-down switch (Sus_dn), the first switch (Q1), and the second switch (Q2) turn off, to fall by the predetermined voltage from the first setup voltage and sustain a fall voltage falling from the scan driving circuit to the scan electrode 110.

In the third period, the pass switch (Pass_sw), the first switch (Q1), and the setup switch (Set-up) turn on, and the second switch (Q2), the supply switch (ER_up), the recovery switch (ER_dn), the sus-up switch (Sus_up), and the sus-down switch (Sus_dn) turn off so that the scan driving circuit supplies the second setup signal to the scan electrode 110.

A description of the first period will be made using the current pass path shown in FIG. 7A. First, in the first period, the setup switch (Set_up) of the reset driving unit 140 and the second switch (Q2) of the scan IC 50, which connect with the first power source (Vsus) for supplying the sustain voltage (Vsus), turn on, thereby connecting to the scan electrode 110 so that the first setup signal gradually rising from the ground voltage (GND) to the sustain voltage (Vsus) is applied to the scan electrode 110.

The setup switch (Set-up) supplies the first setup signal, which gradually rises to the sustain voltage (Vsus) by controlling the resistance of the variable resistor (not shown), to the scan electrode 110 through the second switch (Q2) of the scan IC 150.

Thus, the scan electrode 110 initializes the discharge cell by the first setup signal.

A description of the second period shown in FIG. 6 will be made using the current pass path of FIG. 7B. First, the second period is a period for falling by the predetermined voltage from the sustain voltage (Vsus) of the first period.

In other words, the current pass path of the second period simultaneously turns off the first switch (Q1) and the second switch (Q2) of the scan IC 150 for a predetermined time, and connects to the first diode (D1) connecting with the scan electrode 110, the external power source (Vsc), the pass switch (Pass_sw), and the recovery switch (ER_dn) and the capacitor (Cs) of the energy recovery unit 120, to recover a predetermined voltage from the scan electrode 110 so that the sustain voltage (Vsus) supplied to the scan electrode 110 is applied to the energy recovery unit 120 through the first diode (D1) connecting in parallel with the first switch (Q1).

The predetermined voltage, a difference voltage between the sustain voltage (Vsus) and the scan voltage (Vsc), is about 20V to 50V, and is variable depending on a capacitance of the capacitor (Cs) of the energy recovery unit 120.

It is desirable that the predetermined time is about 8 μs to 12 μs, and is variable depending on the capacitance of the capacitor (Cs).

A description of the third period shown in FIG. 6 will be made using the current pass path of FIG. 7C. First, the third period is a period for gradually rising from the voltage of the second period to the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc).

In other words, the current pass path of the third period turns on the first switch (Q1) of the scan IC 150, and applies the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) to the scan electrode 110. In other words, the current pass path turns on the setup switch (Set_up) and the pass switch (Pass_sw) for supplying the sustain voltage (Vsus), the first power source (Vsc) for supplying the scan voltage (Vsc), and the first switch (Q1) of the scan IC 150, thereby connecting with the scan electrode 110.

Accordingly, the scan electrode 110 receives the first setup signal for supplying the sustain voltage (Vsus) of the first period, and the second setup signal for supplying the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) of the second period.

A comparison of the present invention with the conventional art will be made. In the conventional art, a first switch (Q1) of a scan IC 150 turns on, and a sus-down switch (Sus_dn) of a sustain driving unit 130 turns on, thereby connecting with the ground (GND) so that a first setup signal is supplied to a scan electrode 110.

In order to supply a second setup signal, the first switch (Q1) turns off, and a second switch (Q2) complementarily turns on, thereby inducing a sudden rise by a scan voltage (Vsc) and inducing a gradual rise by a sustain voltage (Vsus). Here, the conventional art has a drawback that, when the first and second switches (Q1) and (Q2) are simultaneously switched and spontaneously short-circuited due to each of their parasitic capacitors, thereby generating a peaking current.

The present invention supplies the first setup signal and then, in the second period, simultaneously turns off the first and second switches (Q1) and (Q2) for a predetermined time, and turns on the recovery switch (ER_dn) of the energy recovery unit 120 to lower by a predetermined voltage the sustain voltage (Vsus) supplied to the scan electrode 110 through the first diode (D1), thereby inducing a recovery to the capacitor (Cs).

The predetermined time varies depending on a recovery time based on the capacitance of the capacitor (Cs), and is about 8 μs to 12 μs. It is desirable that the predetermined voltage is 20V to 50V.

In the third period, the scan IC 150 turns on the first switch (Q1) to supply the second setup signal to the scan electrode 110, and sustains the second switch (Q2) in an off state. Therefore, the peaking current is prevented from resulting from the spontaneous short-circuit caused by the simultaneous switching of the first and second switches (Q1) and (Q2).

FIG. 8 is an exploded view illustrating a “B” range of the setdown period of the driving signal shown in FIG. 6. FIGS. 9A to 9C are circuit diagrams illustrating current pass paths for a flow of current of the scan driving circuit in response to the driving signal applied to the plasma display panel during the setdown period. A description will be made as in FIG. 4.

FIG. 8 shows a detail of the “B” range shown in FIG. 4. As shown, FIG. 8 shows the first period for falling by the sustain voltage (Vsus) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) of the second setup signal, the second period for rising by the predetermined voltage from the voltage of the first period, and the third period for falling from the voltage of the second period to the ground (GND) voltage.

In the first period, the first switch (Q1), the pass switch (Pass_sw), and the recovery switch (ER_dn) turn on and then, the first switch (Q1), the pass switch (Pass_sw), and the sus-down switch (Sus_dn) turn on, so that the scan driving circuit supplies a fall voltage, which falls by the sustain voltage (Vsus) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) of the second setup signal, to the scan electrode 110.

In the second period, the pass switch (Pass_sw) and the supply switch (ER_up) turn on and then, the pass switch (Pass_sw) and the sus-up switch (Sus_up) turn on, to rise by the predetermined voltage from the voltage of the first period and sustain a rise voltage from the scan driving circuit to the scan electrode 110. Also, the recovery switch (ER_dn), the setup switch (Set_up), the sus-down switch (Sus_dn), the first switch (Q1), and the second switch (Q2) turn off.

In the third period, the second switch (Q2), the pass switch (Pass_sw), and the recovery switch (ER_dn) turn on and then, the second switch (Q2), the pass switch (Pass_sw), and the sus-down switch (Sus_dn) turn on, so that the voltage of the second period falls to the ground (GND) voltage from the scan driving circuit to the scan electrode 110.

A description of the first period shown in FIG. 8 will be made using the current pass path shown in FIG. 9A. First, the first period is a period for falling by the sustain voltage (Vsus) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) supplied to the scan electrode 110.

In other words, a first current pass path of the first period turns on the first switch (Q1) of the scan IC 150 connecting with the second power source (Vsc) for supplying the scan voltage (Vsc) and the scan electrode 110, and turns on the recovery switch (ER_dn) of the energy recovery unit 120, thereby connecting with the capacitor (Cs).

Thus, the scan electrode 110 receives a fall voltage falling by the scan voltage (Vsc) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc).

A second current pass path of the first period turns on the first switch (Q1) of the scan IC 150 connecting with the second power source (Vsc) for supplying the scan voltage (Vsc) and the scan electrode 110, and turns on the sus-down switch (Sus_dn) of the sustain driving unit 130, thereby connecting with the ground (GND).

The scan electrode 110 sustains the fall voltage falling by the sustain voltage (Vsus) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc).

In the first period, there is not a sudden fall due to charging of the capacitor (Cs).

A description of the second period shown in FIG. 8 will be made using the current pass path of FIG. 9B. First, the second period is a period for rising by a predetermined voltage from the fall voltage falling by the scan voltage (Vsc).

In other words, the first current pass path of the second period simultaneously turns off the first switch (Q1) and the second switch (Q2) of the scan IC 150 for a predetermined time, and turns on the second diode (D2) connecting in parallel with the second switch (Q2) to the scan electrode 110, and the pass switch (Pass_sw) of the reset driving unit 140, thereby connecting with the capacitor (Cs) through the supply switch (ER_up) of the energy recovery unit 120.

The scan electrode 110 receives the sustain voltage (Vsus) from the capacitor (Cs) of the energy recovery unit 120, to induce a rise by a predetermined voltage.

It is desirable that the predetermined voltage is about 20V to 50V, and a time for simultaneously turning off the first and second switches (Q1) and (Q2) is about 8 μs to 12 μs.

The second current pass path of the second period simultaneously turns off the first and second switches (Q1) and (Q2) of the scan IC 150, and turns on the second diode (D2) connecting in parallel with the second switch (Q2) to the scan electrode 110, and the pass switch (Pass_sw) of the reset driving unit 140, thereby connecting with the sus-up switch (Sus_up) of the sustain driving unit 130.

The scan electrode 110 receives the voltage transmitted to the first current pass path, that is, the sustain voltage (Vsus).

A description of the third period shown in FIG. 8 will be made using the current pass path of FIG. 9C. First, the third period is a period for falling from a rise voltage rising by the sustain voltage (Vsus), to the ground (GND).

In other words, a first current pass path of the third period turns on the scan electrode 110 and the second switch (Q2) of the scan IC 150, and turns on the recovery switch (ER_dn) of the energy recovery unit 120, thereby connecting with the capacitor (Cs).

Thus, the capacitor (Cs) recovers by the sustain voltage (Vsus) from the scan electrode 110.

Also, a second current pass path of the third period turns on the second switch (Q2) of the scan IC 150 connecting with the scan electrode 110, and turns on the sus-down switch (Sus_dn) of the sustain driving unit 130, thereby connecting with the ground (GND).

The scan electrode 110 has a fall to the ground voltage (GND).

In other words, in case where the scan electrode 110 has the fall to the ground voltage (GND), the first current pass path turns off the recovery switch (ER_dn), and turns on the sus-down switch (Sus_dn) of the sustain driving unit 130 connecting with the ground (GND), thereby sustaining the ground voltage (GND).

A comparison of the present invention with the conventional art will be made. In the conventional art, in order to fall from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) to a ground voltage (GND) in a setdown initiation period for falling to the ground voltage (GND) before application of the setdown signal after application of the setup signal, the scan IC 150 turn on the sus-down switch (Sus_dn) of the sustain driving unit 130 and connect with the scan electrode 110, and connect with the ground (GND). The conventional art has a drawback that, when the first and second switches (Q1) and (Q2) are simultaneously switched and spontaneously short-circuited by each of their parasitic capacitors, thereby generating the peaking current.

In the present invention, in the setdown initiation period before application of the setdown signal after application of the setup signal, in state where the first switch (Q1) turns on, the recovery switch (ER_dn) of the energy recovery unit 120 turns on, thereby inducing the recovery to the capacitor (Cs) so that the fall is induced by the scan voltage (Vsc) from the sum voltage of the sustain voltage (Vsus) and the scan voltage (Vsc) supplied to the scan electrode 110.

In the scan electrode 110, after the fall is induced by the scan voltage (Vsc), the first and second switches (Q1) and (Q2) simultaneously turn off, thereby inducing the rise by the sustain voltage (Vsus) recovered to the capacitor (Cs) through the second diode (D2) by turning on the supply switch (ER_up). After that, the recovery switch (ER_dn) turns on, thereby inducing and sustaining the fall to the ground voltage (GND).

Thus, in the second period for rising by the sustain voltage (Vsus), the peaking current is prevented from resulting from the spontaneous short-circuit caused by the simultaneous switching of the first and second switches (Q1) and (Q2).

FIG. 10 is an exploded view illustrating a “C” range of the setdown period of the driving signal shown in FIG. 6. FIGS. 11A to 11C are circuit diagrams illustrating current pass paths for a flow of current of the scan driving circuit in response to the driving signal applied to the plasma display panel during the address period. A description will be made as in FIG. 4.

FIG. 10 shows a detail of the “C” range shown in FIG. 4. As shown, FIG. 11 shows the first period for rising by the sustain voltage (Vsus) from the voltage of the setdown signal gradually falling to the negative voltage (−Vy), and the second period for falling from the voltage of the first period by a predetermined voltage, and a third period for sustaining the voltage of the second period.

In the first period, the second switch (Q2), the setdown switch (Set_dn), and the supply switch (ER_up) turn on and then, the second switch (Q2), the setdown switch (Set_dn), and the sus-up switch (Sus_up) turn on, so that the scan driving circuit supplies the rise voltage, which rises by the sustain voltage (Vsus) from the negative voltage (−Vy) of the setdown signal, to the scan electrode 110.

In the second period, the setdown switch (Set_dn) and the recovery switch (ER_dn) turn on and then, the setdown switch (Set_dn) and the sus-down switch (Sus_dn) turn on, so that the scan driving circuit supplies the fall voltage falling by the predetermined voltage from the voltage of the first period, to the scan electrode.

In the third period, the first switch (Q1) and the sus-down switch (Sus_dn) turn on so that the voltage of the second period is sustained from the scan driving circuit to the scan electrode 110.

A description of the first period shown in FIG. 10 will be made using the current pass path shown in FIG. 11A. First, the first period is a period for falling by the sustain voltage (Vsus) from the negative voltage (−Vy) of the setdown signal supplied to the scan electrode 110.

In other words, a first current pass path of the first period turns on the first switch (Q1) of the scan IC 150 connecting with the scan electrode 110, turns on the setdown switch (Set_dn) of the reset driving unit 140, and turns on the recovery switch (ER_dn) of the energy recovery unit 120, thereby connecting with the capacitor (Cs).

Thus, the scan electrode 110 receives the rise voltage rising by the sustain voltage (Vsus) recovered to the capacitor (Cs).

A second current pass path of the first period turns on the second switch (Q2) of the scan IC 150 connecting with the scan electrode 110, turns on the setdown switch (Set_dn) of the reset driving unit 140, and turns the sus-up switch (Sus_up) of the sustain driving unit 130, thereby connecting with the first power source (Vsus).

The scan electrode 110 sustains the voltage applied from the first current pass path.

A description of the second period shown in FIG. 10 will be made using the current pass path of FIG. 11B. First, the second period is a period for supplying and sustaining a fall voltage falling by a predetermined voltage from the voltage of the first period.

In other words, the first current pass path of the second period simultaneously turns off the first switch (Q1) and the second switch (Q2) of the scan IC 150, and turns on the first diode (D1) connecting in parallel with the first switch (Q1) to the scan electrode 110, and the setdown switch (Set_dn) of the reset driving unit 140, thereby connecting with the capacitor (Cs) through the recovery switch (ER_dn) of the energy recovery unit 120.

The scan electrode 110 has a fall by the predetermined voltage from the rise voltage of the first period.

It is desirable that the predetermined voltage is about 20V to 50V, and a time for simultaneously turning off the first and second switches (Q1) and (Q2) is about 8 μs to 12 μs.

The second current pass path of the second period simultaneously turns off the first and second switches (Q1) and (Q2) of the scan IC 150, and turns on the first diode (D1) connecting in parallel with the first switch (Q1) to the scan electrode 110, and the setdown switch (Set_dn) of the reset driving unit 140, thereby connecting with the ground (GND) through the sus-down switch (Sus_dn) of the sustain driving unit 130.

The scan electrode 110 sustains the voltage transmitted to the first current pass path.

A description of the third period shown in FIG. 10 will be made using the current pass path of FIG. 11C. First, the third period is a period for sustaining the voltage of the second period.

In other words, the current pass path of the third period simultaneously turns on the first switch (Q1) of the scan IC 150, and turns on the setdown switch (Set_dn) of the reset driving unit 140, thereby connecting with the ground (GND) through the sus-down switch (Sus_dn) of the sustain driving unit 130.

Thus, the scan electrode 110 sustains the voltage of the second period, that is, the scan bias voltage (Vsc−Vy).

In the conventional scan IC 150, the first and second switches (Q1) and (Q2) change in state and complementarily turn on or off, thereby inducing a rise to the scan bias voltage (Vsc−Vy). However, in the scan IC 150 according to the present invention, the rise voltage rising by the sustain voltage (Vsus) stored in the capacitor (Cs) of the energy recovery unit 120 without the switching change of the first and second switches (Q1) and (Q2) is supplied to the scan electrode 110.

As a result, in the address initiation period, a higher voltage than the scan bias voltage (Vsc−Vy) is applied. In order to fall to the scan bias voltage (Vsc−Vy), the first and second switches (Q1) and (Q2) are simultaneously turned off. This will be described in the second period.

A comparison of the present invention with the conventional art will be made. In the conventional art, there is a drawback that, as the address period initiates, the first and second switches (Q1) and (Q2) are simultaneously switched and thus, one of the first and second switches (Q1) and (Q2) is short-circuited, thereby generating the peaking current. However, in the present invention, as the address period initiates, the first and second switches (Q1) and (Q2) induce the rise by the sustain voltage (Vsus) from the negative voltage (−Vy), without switching, so that one of the first and second switches (Q1) and (Q2) is prevented from being short-circuited due to the parasitic capacitor, and the first and second switches (Q1) and (Q2) turn off to induce the fall to the scan bias voltage (Vsc−Vy), thereby preventing the peaking current.

In the above constructed plasma display apparatus, the first and second switches of the scan IC turn off for a predetermined time, so that one of the first and second switches is prevented from being short-circuited due to the parasitic capacitor, and the same voltage is applied to both terminals so that the peaking current can be prevented from being applied to the scan IC.

FIG. 12 is an exploded view illustrating a “D” range of the setdown period of the driving signal shown in FIG. 6. FIGS. 13A to 11B are circuit diagrams illustrating current pass paths for a flow of current of the scan driving circuit in response to the driving signal applied to the plasma display panel during the sustain period. A description will be made as in FIG. 4.

FIG. 12 shows a detail of the “D” range shown in FIG. 4. As shown, FIG. 12 shows the first period for rising by the predetermined voltage from the scan bias voltage (Vsc−Vy) in the address period, and the second period for rising from the voltage of the first period to the ground voltage (GND).

In the first period, the setdown switch (Set_dn) and the supply switch (ER_up) turn on so that the scan driving circuit supplies the rise voltage, which rises by the predetermined voltage from the scan bias voltage (Vsc_Vy), to the scan electrode 110.

In the second period, the second switch (Q2), the pass switch (Pass_sw), the sus-down switch (Sus_dn), and the recovery switch (ER_dn) turn on so that the scan driving circuit supplies the ground voltage (GND) rising from the voltage of the first period, to the scan electrode 110.

A description of the first period shown in FIG. 12 will be made using the current pass path shown in FIG. 13A. First, the first period is a period for rising by the predetermined voltage from the scan bias voltage (Vsc−Vy), to the scan electrode 110.

In other words, the current pass path of the first period turns off the first and second switch (Q1) and (Q2) of the scan IC 150 connecting with the scan electrode 110, turns on the second diode (D2) connecting in parallel with the second switch (Q2) and the setdown switch (Set_dn) of the reset driving unit 140, and turns on the supply switch (ER_up) of the energy recovery unit 120, thereby connecting with the capacitor (Cs).

Thus, the scan electrode 110 receives the rise voltage rising by the predetermined voltage from the scan bias voltage (Vsc−Vy), using the sustain voltage (Vsus) recovered to the capacitor (Cs).

It is desirable that the predetermined voltage is about 20V to 50V, and a time for simultaneously turning off the first and second switches (Q1) and (Q2) is about 8 μs to 12 μs.

A description of the second period shown in FIG. 12 will be made using the current pass path of FIG. 13B. First, the second period is a period for rising from the voltage of the first period to the ground voltage (GND), to the scan electrode 110.

In other words, the first current pass path of the second period simultaneously turns on the second switch (Q2) of the scan IC 150 connecting with scan electrode 110, and turns on the pass switch (Pass_sw) of the reset driving unit 140, and, at this time, turns on the recovery switch (ER_dn) of the energy recovery unit 120 to sustain the voltage of the first period, thereby connecting with the capacitor (Cs). After that, the recovery switch (ER_dn) of the energy recovery unit 120 turns off, and the sus-down (Sus_dn) of the sustain driving unit 130 turns on.

Thus, the scan electrode 110 receives the rise voltage rising from the voltage of the first period to the ground voltage (GND).

In the conventional scan IC 150, the first and second switches (Q1) and (Q2) change in state and complementarily turn on or off, thereby inducing the rise from the scan bias voltage (Vsc−Vy) to the rise voltage (Vsus−Vy) by the sustain voltage (Vsus). However, in the scan IC 150 according to the present invention, the first and second switches (Q1) and (Q2) simultaneously turn off.

The first and second switches (Q1) and (Q2) of the scan IC 150 are sustained in the off state for a predetermined time. The predetermined time is a time for which the voltage supplied to the scan electrode 110 rises by the sustain voltage (Vsus), and is based on a range of about 8 μs to 12 μs depending on a supply of the capacitor (Cs).

A comparison of the present invention with the conventional art will be made. In the conventional art, there is a drawback that, as the sustain period initiates, the first and second switches (Q1) and (Q2) are simultaneously switched and thus, one of the first and second switches (Q1) and (Q2) is short-circuited, thereby generating the peaking current. However, in the present invention, as the sustain period initiates, the first and second switches (Q1) and (Q2) simultaneously turn off and perform the rise by the sustain voltage (Vsus) from the scan bias voltage (Vsc−Vy) so that one of the first and second switches (Q1) and (Q2) is prevented from being short-circuited due to the parasitic capacitor, and the first and second switches (Q1) and (Q2) turn on to induce the rise to the ground voltage (GND), thereby preventing the peaking current.

An operation and an effect of the above constructed plasma display apparatus according to the present invention will be described below.

The present invention has an effect that the first and second switches (Q1) and (Q2) of the scan IC 150 simultaneously turn off for a predetermined time, thereby, when the first and second switches (Q1) and (Q2) are complementarily switched, preventing any one of the first and second switches (Q1) and (Q2) from being spontaneously short-circuited by the parasitic capacitor, preventing the peaking current from being introduced into the scan IC 150, preventing a damage of the scan IC 150, and improving a picture quality owing to the non-occurrence of the heat.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Number	Date	Country	Kind
10-2006-0045084	May 2006	KR	national
10-2006-0045085	May 2006	KR	national
10-2006-0045086	May 2006	KR	national

Plasma display apparatus

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CPC

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Priority Claims (3)