This application claims the benefit of Korea Patent Application No. 10-2008-0114986 filed on Nov. 19, 2008, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
1. Field
Embodiments relate to a plasma display apparatus.
2. Description of the Background Art
A plasma display apparatus includes a plasma display panel. The plasma display panel includes a phosphor layer inside discharge cells partitioned by barrier ribs and a plurality of electrodes.
When driving signals are applied to the electrodes of the plasma display panel, a discharge occurs inside the discharge cells. More specifically, when the discharge occurs in the discharge cells by applying the driving signals to the electrodes, a discharge gas filled in the discharge cells generates vacuum ultraviolet rays, which thereby cause phosphors between the barrier ribs to emit visible light. An image is displayed on the screen of the plasma display panel using the visible light.
In one aspect, there is a plasma display apparatus comprising a plasma display panel including a scan electrode and a sustain electrode that are positioned parallel to each other, and an address electrode crossing the scan electrode and the sustain electrode and a driver that supplies a reset signal to the scan electrode and supplies a first signal, whose a direction is the same as a direction of the reset signal, to the sustain electrode in a reset period of at least one of a plurality of subfields of a frame, wherein the first signal overlaps a predetermined period during which the reset signal rises to a maximum voltage and then again rises to a voltage less than the maximum voltage.
In another aspect, there is a plasma display apparatus comprising a plasma display panel including a scan electrode and a sustain electrode that are positioned parallel to each other, and an address electrode crossing the scan electrode and the sustain electrode and a driver that supplies a first reset signal to the scan electrode and supplies a first signal, whose a direction is the same as a direction of the first reset signal, to the sustain electrode in a reset period of a first subfield of a plurality of subfields of a frame, and supplies a second reset signal, whose a voltage magnitude is smaller than a voltage magnitude of the first reset signal, to the scan electrode and supplies the first signal, whose a direction is the same as a direction of the second reset signal, to the sustain electrode in a reset period of a second subfield following the first subfield, wherein the first signal overlaps a predetermined period during which each of the first and second reset signals rises to a maximum voltage and then again rises to a voltage less than the maximum voltage.
In still one aspect, there is a plasma display apparatus comprising a plasma display panel including a scan electrode and a sustain electrode that are positioned parallel to each other, and an address electrode crossing the scan electrode and the sustain electrode and a driver that supplies a reset signal to the scan electrode and supplies a first signal overlapping the reset signal to the sustain electrode in a reset period of at least one of a plurality of subfields of a frame, wherein the reset signal includes a ramp-up signal, whose a voltage gradually rises in a setup period of the reset period, and a ramp-down signal, whose a voltage gradually falls in a set-down period following the setup period, wherein an erase period is arranged between the setup period and the set-down period, wherein during the erase period, the reset signal falls to a first voltage, that is less than a maximum voltage of the ramp-up signal and is greater than a ground level voltage, and then again rises to a second voltage less than the maximum voltage of the ramp-up signal, wherein the first signal overlaps the erase period.
Further scope of applicability of the invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail embodiments of the invention examples of which are illustrated in the accompanying drawings.
As shown in
The plasma display panel 100 includes scan electrodes Y1 to Yn and sustain electrodes Z1 to Zn positioned parallel to each other, and address electrodes X1 to Xm positioned to cross the scan electrodes Y1 to Yn and the sustain electrodes Z1 to Zn.
The driver 110 displays an image on the plasma display panel 100 in a frame including a plurality of subfields. More specifically, the driver 110 supplies driving signals to at least one of the scan electrodes Y1 to Yn, the sustain electrodes Z1 to Zn, or the address electrodes X1 to Xm to thereby display an image on the screen of the plasma display panel 100.
For example, during a reset period of at least one of a plurality of subfields of a frame, the driver 110 supplies a reset signal to the scan electrode and supplies a first signal overlapping the reset signal to the sustain electrode and thus may generate an erase discharge in the discharge cells.
Although
As shown in
An upper dielectric layer 204 may be formed on the scan electrode 202 and the sustain electrode 203 to limit a discharge current of the scan electrode 202 and the sustain electrode 203 and to provide insulation between the scan electrode 202 and the sustain electrode 203. A protective layer 205 may be formed on the upper dielectric layer 204 to facilitate discharge conditions. The protective layer 205 may be formed of a material having a high secondary electron emission coefficient, for example, magnesium oxide (MgO).
A lower dielectric layer 215 may be formed on the address electrode 213 to provide insulation between the address electrodes 213.
Barrier ribs 212 of a stripe type, a well type, a delta type, a honeycomb type, etc. may be formed on the lower dielectric layer 215 to partition discharge spaces (i.e., discharge cells). Hence, a first discharge cell emitting red light, a second discharge cell emitting blue light, and a third discharge cell emitting green light, etc. may be formed between the front substrate 201 and the rear substrate 211. The address electrode 213 may cross the scan electrode 202 and the sustain electrode 203 in one discharge cell. Namely, each discharge cell is formed at a crossing of the scan electrode 202, the sustain electrode 203, and the address electrode 213.
The barrier rib 212 may have various forms of structures as well as a structure shown in
In the differential type barrier rib structure, a height of the first barrier rib 212b may be smaller than a height of the second barrier rib 212a. In the channel type barrier rib structure, a channel may be formed on the first barrier rib 212b.
Each of the discharge cells partitioned by the barrier ribs 212 may be filled with a predetermined discharge gas.
A phosphor layer 214 may be formed inside the discharge cells to emit visible light for an image display during an address discharge. For example, first, second, and third phosphor layers that respectively generate red, blue, and green light may be formed inside the discharge cells.
While the address electrode 213 may have a substantially constant width or thickness, a width or thickness of the address electrode 213 inside the discharge cell may be different from a width or thickness of the address electrode 213 outside the discharge cell. For example, a width or thickness of the address electrode 213 inside the discharge cell may be larger than a width or thickness of the address electrode 213 outside the discharge cell.
When a predetermined signal is supplied to at least one of the scan electrode 202, the sustain electrode 203, and the address electrode 213, a discharge may occur inside the discharge cell. The discharge may allow the discharge gas filled in the discharge cell to generate ultraviolet rays. The ultraviolet rays may be incident on phosphor particles of the phosphor layer 214, and then the phosphor particles may emit visible light. Hence, an image may be displayed on the screen of the plasma display panel 100.
As shown in
For example, if an image with 256-gray level is to be displayed, as shown in
Furthermore, at least one of a plurality of subfields of a frame may further include a reset period for initialization. At least one of a plurality of subfields of a frame may not include a sustain period.
The number of sustain signals supplied during the sustain period may determine a gray level of each of the subfields. For example, in such a method of setting a gray level of a first subfield at 20 and a gray level of a second subfield at 21, the sustain period increases in a ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) in each of the subfields. Hence, various gray levels of an image may be achieved by controlling the number of sustain signals supplied during the sustain period of each subfield depending on a gray level of each subfield.
Although
At least one of a plurality of subfields of a frame may be a selective erase subfield or a selective write subfield.
If a frame includes at least one selective erase subfield and at least one selective write subfield, it may be preferable that a first subfield of a plurality of subfields of the frame is a selective write subfield and the other subfields are selective erase subfields. Alternatively, all the subfields of the frame may be selective erase subfields.
In the selective erase subfield, the discharge cell to which a data signal is supplied during an address period is turned off during a sustain period following the address period. In the selective write subfield, the discharge cell to which a data signal is supplied during an address period is turned on during a sustain period following the address period.
As shown in
More specifically, the ramp-up signal RU may be supplied to the scan electrode Y during a setup period SU of the reset period RP, and the ramp-down signal RD may be supplied to the scan electrode Y during a set-down period SD following the setup period SU. The ramp-up signal RU may generate a weak dark discharge (i.e., a setup discharge) inside the discharge cells. Hence, the wall charges may be uniformly distributed inside the discharge cells. The ramp-down signal RD subsequent to the ramp-up signal RU may generate a weak erase discharge (i.e., a set-down discharge) inside the discharge cells. Hence, the remaining wall charges may be uniformly distributed inside the discharge cells to the extent that an address discharge occurs stably.
The ramp-up signal RU may include a first ramp-up signal RU1 and a second ramp-up signal RU2 each having a different voltage change rate over time. The first ramp-up signal RU1 may gradually rise from a ground level voltage GND to a fourth voltage V4 with a first voltage change rate, and the second ramp-up signal RU2 may gradually rise from the fourth voltage V4 to a third voltage V3 with a second voltage change rate less than the first voltage change rate. The first and second ramp-up signals RU1 and RU2 may further stabilize the setup discharge. More specifically, because the first and second ramp-up signals RU1 and RU2 rapidly raise a voltage before a generation of the setup discharge and relatively slowly raise the voltage immediately after the setup discharge occurs, an amount of light generated during the setup period SU may be reduced and also contrast characteristics may be improved.
The ramp-down signal RD may include a first ramp-down signal RD1 and a second ramp-down signal RD2 each having a different voltage change rate over time. The first ramp-down signal RD1 may gradually fall from a second voltage V2 to a fifth voltage V5 with a third voltage change rate, and the second ramp-down signal RD2 may gradually fall from the fifth voltage V5 to a sixth voltage V6 with a fourth voltage change rate whose a magnitude is less than a magnitude of the third voltage change rate. The first and second ramp-down signals RD1 and RF2 may further stabilize the set-down discharge and may reduce an amount of light generated during the set-down period SD. Hence, the contrast characteristics may be improved.
A predetermined period may be arranged between the setup period SU and the set-down period SD. During the predetermined period, the reset signal RS may rise to the third voltage V3 (i.e., a maximum voltage of the reset signal RS) and then may again rise to the second voltage V2 less than the maximum voltage V3. Hence, an erase discharge may occur in the discharge cells during the predetermined period, and thus an amount of wall charges remaining in the discharge cells may be reduced. The predetermined period may be referred to as an erase period.
During an erase period EP, the reset signal RS between the ramp-up signal RU and the ramp-down signal RD may fall to a first voltage V1, that is less than the maximum voltage V3 of the ramp-up signal RU and is greater than the ground level voltage GND, and then may rise to the second voltage V2, that is greater than the first voltage V1 and is less than the maximum voltage V3. Further, during the erase period EP, a first signal PS overlapping the reset signal RS may be supplied to the sustain electrode Z. The first signal PS has the same direction as the reset signal RS. Hence, an erase discharge occurs between the scan electrode Y and the sustain electrode Z, and thus an amount of wall charges remaining in the discharge cells may be reduced. Preferably, the first signal PS may overlap a period during which the voltage of the reset signal RS again rises.
If there in no erase period EP between the setup period SU and the set-down period SD, an amount of wall charges remaining in the discharge cells may excessively increase at an end of the reset period RP. In this case, even if a data signal is not supplied to the address electrode during an address period AP following the reset period RP, an address discharge may occur during the address period AP. Namely, an erroneous discharge occurs during the address period AP. As a result, because a sustain discharge may occur during a sustain period SP following the address period AP, the image quality may worsen.
On the other hand, as shown in
Further, if a proper amount of wall charges remain in the discharge cells after the setup period SU, an erase discharge may not occur during the erase period EP.
In other words, if the erase period EP is arranged between the setup period SU and the set-down period SD, the erase discharge occurs during the erase period EP when an excessive amount of wall charges remain in the discharge cells at an end of the setup period SU. Hence, the excessive amount of wall charges may be reduced. Further, if a proper amount of wall charges remain in the discharge cells at the end of the setup period SU, the erase discharge does not occur even if the erase period EP is arranged. Hence, the generation of erroneous discharge may be prevented.
As shown in
As shown in
Further, because the sustain signal SUS is supplied using an energy recovery circuit including an inductor, the sustain signal SUS may include a voltage rising period d10 during which a voltage of the sustain signal SUS gradually rises, a voltage hold period d20 during which the sustain signal SUS is substantially held at the maximum voltage Vs, and a voltage falling period d30 during which the voltage of the sustain signal SUS gradually falls. The voltage rising period d10 may be referred to as an ER-Up period, and the voltage falling period d30 may be referred to as an ER-Down period.
Further, the first signal PS may be supplied using the energy recovery circuit used to generate the sustain signal SUS. Therefore, the first signal PS may include a voltage rising period d1 during which a voltage of the first signal PS gradually rises, a voltage hold period d2 during which the first signal PS is substantially held at the maximum voltage V7, and a voltage falling period d3 during which the voltage of the first signal PS gradually falls. A length and a voltage change rate of the voltage rising period d1 of the first signal PS may be substantially equal to a length and a voltage change rate of the voltage rising period d10 of the sustain signal SUS. In addition, a length and a voltage change rate of the voltage falling period d3 of the first signal PS may be substantially equal to a length and a voltage change rate of the voltage falling period d30 of the sustain signal SUS.
Referring again to
A pulse width of a scan signal supplied to the scan electrode during an address period of at least one subfield of a frame may be different from pulse widths of scan signals supplied during address periods of the other subfields of the frame. A pulse width of a scan signal in a subfield may be greater than a pulse width of a scan signal in a next subfield. For example, a pulse width of the scan signal may be gradually reduced in the order of 2.6 μs, 2.3 μs, 2.1 μs, 1.9 μs, etc. or may be reduced in the order of 2.6 μs, 2.3 μs, 2.3 μs, 2.1 μs, . . . , 1.9 μs, 1.9 μs, etc. in the successively arranged subfields.
As above, when the scan signal Sc is supplied to the scan electrode Y, a data signal Dt corresponding to the scan signal Sc may be supplied to the address electrode X. As a voltage difference between the scan signal Sc and the data signal Dt is added to a wall voltage obtained by the wall charges produced during the reset period RP, an address discharge may occur inside the discharge cell to which the data signal Dt is supplied. In addition, during the address period AP, a sustain reference signal Zbias may be supplied to the sustain electrode Z, so that the address discharge efficiently occurs between the scan electrode Y and the address electrode X.
During the sustain period SP, the sustain signal SUS may be supplied to at least one of the scan electrode Y or the sustain electrode Z. In
As shown in
In this case, because a voltage difference between the scan electrode Y and the sustain electrode Z in the erase period EP is relatively small, an intensity of the erase discharge excessively decreases or the erase discharge may not occur in the erase period EP. In
Further, as shown in
On the other hand, as shown in
The first signal PS may not overlap at least one of the ramp-up signal RU and the ramp-down signal RD. In
In
A hold time of an erase discharge, i.e., a time interval Δt1 between the time points t4 and t2 may be adjusted so that a sufficient amount of wall charges are erased through the erase discharge.
More specifically, as shown in
A pulse width W2 of the first signal PS may variously change on condition that a hold time of the erase discharge (i.e., the time interval Δt1) is less than the pulse width W1 of the sustain signal SUS. For example, the pulse width W2 of the first signal PS may be greater or less than the pulse width W1 of the sustain signal SUS. Otherwise, the pulse width W2 of the first signal PS may be substantially equal to the pulse width W1 of the sustain signal SUS.
The driving time characteristic was estimated by deciding whether or not sufficient time required to drive the plasma display apparatus is secured as a length of the time interval Δt1 in a set driving waveform increases. In the driving time characteristic, □ indicates an excellent state because the sufficient driving time is secured; ∘ indicates a good state; and X indicates a bad state, in which it is difficult to secure the driving time because the length of the time interval Δt1 excessively increases in the erase period.
When the length of the time interval Δt1 is about 20 ns, the characteristic of the amount of wall charges erased in the erase period represents the bad state. In this case, because the length of the time interval Δt1 is excessively short (i.e., the hold time of the erase discharge is excessively short), the excessively small amount of wall charges may be erased in the erase period or an erase discharge may not occur in the erase period.
On the other hand, when the length of the time interval Δt1 is about 100 ns to 200 ns, the characteristic of the amount of wall charges represents the excellent state. In this case, the sufficient amount of wall charges may be erased in the erase period because of the proper length of the time interval Δt1.
Further, when the length of the time interval Δt1 is about 50 ns or 250 ns, the characteristic of the amount of wall charges erased in the erase period represents the good state.
When the length of the time interval Δt1 is about 300 ns to 400 ns, the characteristic of the amount of wall charges erased in the erase period represents the bad state. In this case, as the length of the time interval Δt1 excessively increases, the amount of wall charges erased by the erase discharge occurring in the erase period may decrease. As the length of the time interval Δt1 more excessively increases, the amount of wall charges may increase subsequent to the erase discharge.
When the length of the time interval Δt1 is about 20 ns or 300 ns, the excessively large amount of wall charges may remain in the discharge cells after the erase period because the excessively small amount of wall charges are erased in the erase period. Hence, even if the data voltage is not supplied, the address discharge may occur.
When the length of the time interval Δt1 is about 100 ns to 200 ns, the amount of wall charges remaining in the discharge cells after the erase period is within an allowable range because the sufficient amount of wall charges are erased in the erase period.
When the length of the time interval Δt1 is about 50 ns or 250 ns, the sufficient amount of wall charges are not erased in the erase period. However, the amount of wall charges remaining in the discharge cells after the erase period is within a possible range.
When the length of the time interval Δt1 is equal to or greater than about 400 ns, the driving time characteristic represents the bad state. In this case, the driving time may be insufficient because of the excessively long length of the time interval Δt1.
When the length of the time interval Δt1 is about 20 ns to 250 ns, the driving time characteristic represents the excellent state. In this case, the driving time may be easily secured because of the sufficiently short length of the time interval Δt1.
When the length of the time interval Δt1 is about 300 ns, the driving time characteristic represents the good state.
Considering the descriptions of
As shown in
More specifically, the erase period EP in which an erase discharge occurs in the discharge cells to reduce an amount of wall charges may include a first hold period P1 during which the reset signal RS is held at a first voltage V1, a second hold period P2 during which the reset signal RS is held at the second voltage V2, and a third hold period P3 during which the reset signal RS is held at the tenth voltage V10 less than the first voltage V1. The ramp-down signal RD may fall from an end of the third hold period P3, i.e., the tenth voltage V10. In this case, the tenth voltage V10 may be substantially equal to the ground level voltage. In this case, an erase discharge may occur between the scan electrode and the sustain electrode by supplying a first signal PS to the sustain electrode in the erase period EP.
A maximum voltage of the reset signal RS shown in
As shown in
The reset signal RS shown in
In other words, the ramp-down signal RD of the first reset signal RS1 in the first subfield SF1 may fall from a second voltage V2 less than the maximum voltage V3 of the first reset signal RS1, and the ramp-down signal RD of the second reset signal RS2 in the second subfield SF2 may fall from the ground level voltage GND.
As above, because the second reset signal RS2, whose the maximum voltage V11 is less than the maximum voltage V3 of the first reset signal RS1, is supplied in the second subfield SF2, in which the number of sustain signals is more than that in the first subfield SF1, and the first reset signal RS1 is supplied in the first subfield SF1, the wall charges are uniformly distributed in the first subfield SF1 because of the first reset signal RS1 having the relatively higher maximum voltage V3. Hence, the entire discharge may be stabilized. Further, even if the maximum voltage V11 of the second reset signal RS2 supplied in the second subfield SF2 subsequent to the first subfield SF1 is lowered, the entire discharge in the second subfield SF2 may be stabilized.
In this case, the first signal PS in each of the first and second subfields SF1 and SF2 may overlap a period in which voltages of the first and second reset signals RS1 and RS2 rise to the maximum voltages V3 and V11 and then again rise to voltages less than the maximum voltages V3 and V11.
As shown in
An erase period EP may include a first hold period P1 during which a voltage of a reset signal RS is held at a first voltage V1, a second hold period P2 during which the voltage of the reset signal RS is held at a second voltage V2, and a third hold period P3 during which the voltage of the reset signal RS falls from the second voltage V2 to a tenth voltage V10 (i.e., the ground level voltage GND) and then is held at the tenth voltage V10.
The second signal PS2 may overlap the first hold period P1 and the second hold period P2, and the third signal PS3 may overlap the second hold period P2 and the third hold period P3.
In
In this case, a hold time of an erase discharge exists between the time points t14 and t11 and between the time points t12 and t17. Namely, a voltage difference between the scan electrode and the sustain electrode increases at the time point t14 of the erase period EP, and thus an erase discharge first occurs. Then, a voltage difference between the scan electrode and the sustain electrode increases at the time point t12 of the erase period EP, and thus an erase discharge secondly occurs. In this case, the wall charges in the discharge cells may be erased more stably.
Further, the hold time of the erase discharge, i.e., a length of a time interval Δt2 between the time points t14 and t11 and a length of a time interval Δt3 between the time points t12 and t17 may be approximately 50 ns to 250 ns, and preferably, may be approximately 100 ns to 200 ns as illustrated in
The reset signal RS illustrated in
As above, the number of first signals supplied in reset periods of two subfields of a plurality of subfields may be different from each other. Preferably, the number of first signals in one subfield of a plurality of subfields may be less than the number of first signals in a subfield following the one subfield (or a subfield whose a gray weight value is greater than a gray weight value of the one subfield).
Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Number | Date | Country | Kind |
---|---|---|---|
10-2008-0114986 | Nov 2008 | KR | national |
Number | Name | Date | Kind |
---|---|---|---|
6294875 | Kurata et al. | Sep 2001 | B1 |
20030122738 | Lee | Jul 2003 | A1 |
20060050019 | Kim | Mar 2006 | A1 |
20070008248 | Jung et al. | Jan 2007 | A1 |
20070268284 | Kim et al. | Nov 2007 | A1 |
20080122742 | Huh et al. | May 2008 | A1 |
20090128537 | Cho et al. | May 2009 | A1 |
Number | Date | Country | |
---|---|---|---|
20100123709 A1 | May 2010 | US |