Plasma display apparatus

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a plasma display apparatus.

2. Description of Related Art

In recent years, a variety of thin display apparatuses have been brought into practical use in response to a demand for a reduction in thickness of such apparatuses to the accompaniment of an increase in size of the screen. An AC discharge type plasma display panel has drawn attention as one of the thin display apparatuses.

A plasma display panel (PDP) has a plurality of display lines, each of which corresponds to one line of a screen.

A conventional plasma display panel requires a sufficient pitch between display lines in order to prevent an erroneous discharge between the display lines. This results in difficulties in improving the resolution by reducing the pitch between the display lines.

Further, since the coventional plasma display panel cosumes more power than CRT, liquid crystal display and so on, a reduction in power consumption is desired for the plasma display panel.

OBJECT AND SUMMARY OF THE INVENTION

The present invention has been made to solve the problems as mentioned above, and an object of the invention is to provide a plasma display apparatus which is capable of providing a high definition display with low power consumption.

A plasma display apparatus according to a first aspect of the present invention is a plasma display apparatus for displaying an image corresponding to an input video signal, which comprises a plasma display panel including a plurality of first row electrodes and second row electrodes extending in a horizontal direction and formed in alternation, a discharge space filled with a discharge gas, and a plurality of column electrodes formed opposite to and extending in a direction perpendicular to the first row electrodes and the second row electrodes through the discharge space, wherein discharge cells corresponding to pixels are formed at respective intersections of the first row electrodes and second row electrodes with the column electrodes, and a spacing between each of the first row electrodes and each of the second row electrode is conformed to a display line on the screen; reset driving means for causing a reset discharge to occur for forming wall charges in all of the discharge cells; write driving means for causing a selective erasure discharge to occur for selectively erasing the wall charges formed in the discharge cells in accordance with the input video signal and light emission sustain driving means for causing a sustaining discharge to occur for forcing only discharge cells formed with the wall charges therein out of the discharge cells to repeatedly emit light.

A plasma display apparatus according to a second aspect of the present invention is a plasma display apparatus for displaying an image corresponding to an input video signal, which comprises a plasma display panel including a plurality of first row electrodes and second row electrodes extending in a horizontal direction and formed in alternation, a discharge space filled with a discharge gas, and a plurality of column electrodes formed opposite to and extending in a direction perpendicular to the first row electrodes and the second row electrodes through the discharge space, wherein discharge cells corresponding to pixels are formed at respective intersections of the first row electrodes and second row electrodes with the column electrodes, and a spacing between each of the first row electrodes and each of the second row electrode is conformed to each of display lines on the screen; a power supply circuit including a capacitor, a first switching current path for selectively discharging a charge accumulated on the capacitor to supply the charge to a power supply line, a second switching current path for selectively applying a power supply potential to the power supply line, and a third switching current path for selectively charging the capacitor with charges accumulated on the column electrodes through the power supply line; and a pixel data pulse generator circuit for connecting the power supply line to the column electrodes for a predetermined period of time in response to the input video signal to generate pixel data pulses corresponding to the input video signal and applying the pixel data pulses onto the column electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a diagram generally illustrating the structure of a conventional plasma display apparatus;

FIG. 2

is a timing chart showing timings of application of a variety of driving pulses to column electrodes and row electrodes of a plasma display panel in the conventional plasma display apparatus;

FIG. 3

is a diagram generally illustrating the structure of a plasma display apparatus according to the present invention;

FIG. 4

is a diagram illustrating a portion of an overall electrode structure of a PDP

20

in the plasma display apparatus of the present invention;

FIGS. 5A and 5B

are timing charts showing timings of application of a variety of driving pulses are applied to column electrodes and row electrodes of the PDP

20

in the plasma display apparatus of the present invention;

FIG. 6

is a diagram generally illustrating the structure of a plasma display apparatus according to a second aspect of the present invention;

FIG. 7

is a circuit diagram illustrating the internal configuration of a column electrode driving circuit

30

;

FIG. 8

is a timing chart showing waveforms which represent internal operations in the column electrode driving circuit

30

;

FIG. 9

is a circuit diagram illustrating the internal configuration of a column electrode driving circuit

30

′; and

FIG. 10

is a timing chart showing waveforms which represent internal operations in the column electrode driving circuit

30

′.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to describing in detail a plasma display apparatus according to the present invention, an example of a conventional plasma display will be discussed with reference to the accompanying drawings.

FIG. 1

is a diagram generally illustrating the configuration of a plasma display apparatus which comprises a plasma display panel and a driving unit for driving the plasma display panel.

In

FIG. 1

, a plasma display panel (PDP)

10

comprises m column electrodes D

1

-D

m

as data electrodes; and n row electrodes X

1

-X

n

and n row electrodes Y

1

-Y

n

which intersect the respective column electrodes D

1

-D

m

. These row electrodes X

1

-X

n

and row electrodes Y

1

-Y

n

form pairs of row electrodes X, Y, each of which serves as a display line corresponding to one line on the screen. Stated another way, the PDP

10

is comprised of a number of display lines equal to n, comprised of display lines L

1

-Ln, as illustrated in FIG.

1

. The column electrodes D and the row electrodes X, Y are formed on two glass substrates which are positioned opposite to each other with a discharge space interposed therebetween. Then, as illustrated in

FIG. 1

, discharge cells G, corresponding to respective pixels, are formed at respective intersections of the display lines L and the column lines D.

In this event, since each of the discharge cells utilizes a discharge phenomenon to emit light, it only has two states, i.e., a “light emitting” state and a “non-light emitting” state. In other words, each cell can represent the luminance only at two levels of gradation, i.e., a minimum luminance (non-light emitting state) and a maximum luminance (light emitting state). Therefore, a driving circuit

100

implements subfield-based gradation driving in order to realize a half-tone luminance display corresponding to a video signal input to the PDP

10

. The subfield method converts an input video signal to, for example, n-bit pixel data corresponding to each pixel, and divides one field into n subfields corresponding to respective bit digits of the n-bit pixel data.

FIG. 2

is a timing chart showing applying timings at which the driving circuit

100

applies a variety of driving pulses to the row electrode pairs and the column electrodes of the PDP

10

in one subfield.

As shown in

FIG. 2

, the driving circuit

100

first applies a reset pulse RP

X

of positive polarity to the row electrodes X

1

-X

n

, and a reset pulse RP

Y

of negative polarity to the row electrodes Y

1

-Y

n

. In response to the application of these reset pulses RP

X

and RP

Y

, all the discharge cells in the PDP

10

are reset discharged to uniformly form a predetermined amount of wall charge in each of the discharge cells. Immediately after the formation of the wall charges, the driving circuit

100

applies an erasure pulse EP simultaneously to the row electrodes X

1

-X

n

of the PDP

10

. This causes an erasure discharge to occur in all the discharge cells to extinguish the wall charges (a simultaneous reset stage Rc). The simultaneous reset stage Rc initializes all the discharge cells in the PDP

10

into the state of “non-light emission cell.” Next, the driving circuit

100

sequentially applies a group of pixel data pulses DP

1

-DP

n

for one line corresponding to the input video signal to column electrodes D

1−m

, and also generates a scanning pulse SP at the timing at which each of the pixel data pulses DP in the group is applied, and sequentially applies the scanning pulse SP to the row electrodes Y

1

-Y

n

(pixel data writing stage Wc). In this event, a discharge occurs only in discharge cells at intersections of “rows” which are applied with the scanning pulse SP and “columns” which are applied with the high voltage pixel data pulses (selective writing discharge) to form wall charges in these discharge cells. The discharge cells, which have been initialized to the “non-light emitting cell” state in the simultaneous reset stage Rc” proceed to “light emitting cells.” On the other hand, those discharge cells which are applied with the scanning pulse SP but also applied with low voltage image data pulses do not undergo the selective writing discharge, and remain in the initialized state in the simultaneous reset stage Rc, i.e., the “non-light emitting cell” state. Next, as illustrated in

FIG. 2

, the driving circuit

100

alternately and repeatedly applies sustain pulses IP

X

, IP

Y

to the row electrodes X

1

-X

n

and the row electrodes Y

1

-Y

n

(light emission sustaining stage Ic). It should be noted that the number of times the sustain pulses IP

X

, IP

Y

are applied in one subfield is set in accordance with weighting applied to each subfield. Here, those discharge cells in which the wall charge exists, i.e., only “light emitting cells” discharge each time they are applied with the sustain pulses IP

X

, IP

Y

(sustain discharge). In other words, only discharge cells which have been set in “light emitting cells” in the pixel data writing stage Wc repeat the sustain discharge, which results in emitting light, a number of times corresponding to the weighting applied to each subfield to sustain their light emitting state.

The driving circuit

100

performs the operation as described in each subfield to represent a half-tone luminance corresponding to a video signal through the total number of times (in one field) of the sustain discharges caused in one subfield.

In this event, the electrode configuration of the PDP

10

illustrated in

FIG. 1

experiences a potential difference generated due to the sustain pulses IP

X

, IP

Y

even between respective display lines, for example, between a row electrode Y

1

of a display line L

1

and a row electrode X

2

of a display line L

2

. Since this potential difference may cause an erroneous discharge irrelevant to pixel data between these display lines as described above, the pitch LP between the display lines must be sufficiently large to prevent the erroneous discharge, as illustrated in FIG.

1

. This results in difficulties in improving the resolution by reducing the pitch LP between the display lines.

Also, as described above, since the plasma display panel consumes more power than CRT, liquid crystal display and so on, a reduction in power consumption is desired for the plasma display panel.

In the following, the present invention will be described in connection with an embodiment thereof with reference to the accompanying drawings.

FIG. 3

generally illustrates the configuration of a plasma display apparatus according to the present invention.

In

FIG. 3

, a plasma display panel (PDP)

20

comprises m column electrodes D

1

-D

m

as data electrodes; and n row electrodes X

1

-X

n

and n row electrodes Y

1

-Y

n

which intersect the respective column electrodes D

1

-D

m

. The PDP

20

comprises (2n−1) display lines L

1

-L(2n−1) comprised of these row electrodes X

1

-X

n

and row electrodes Y

1

-Y

n

.

FIG. 4

illustrates the structure of the electrodes in the PDP

20

. Specifically,

FIG. 4

illustrates intersections of column electrodes D

1

-D

6

with row electrodes X

1

-X

5

and row electrodes Y

1

-Y

5

, which are extracted from the entire PDP

20

.

In

FIG. 4

, the row electrodes X and the row electrodes Y, which comprise display lines, are alternately formed on the inner surface of a front glass substrate (not shown). These row electrodes X, Y are covered with a dielectric layer. A discharge space (not shown) is formed between the dielectric layer and a back glass substrate (not shown), and is filled with a mixture of rare gases encapsulated therein as a discharge gas. Then, on the inner surface of the back glass substrate, i.e., the surface opposing the front glass substrate, respective column electrodes D are formed extending in a direction in which they intersect the row electrodes X, Y, as illustrated in FIG.

4

. In this structure, discharge cells corresponding to pixels are formed at intersections of the row electrodes X, Y (or the row electrodes Y, X) with the column electrodes D, i.e., in portions including the discharge space within regions surrounded by broken lines in FIG.

4

. Further, the PDP

20

is provided with ribs LB in a tessellation shape, as illustrated in

FIG. 4

, to prevent discharge light emitted from respective discharge cells from leaking into neighboring discharge cells.

A driving circuit

200

generates a variety of driving pulses for driving the PDP

20

in accordance with an input video signal, and applies the driving pulses to the column electrodes D

1

-D

m

as well as to the row electrodes X

1

-X

n

and the row electrodes Y

1

-Y

n

of the PDP

20

.

FIGS. 5A and 5B

show timings of application, in one subfield, of a variety of driving pulses to the PDP

20

by the driving circuit

200

.

First, in an odd-numbered field operation, the driving circuit

200

applies the column electrodes D

1

-D

m

, the row electrodes X

1

-X

n

and the row electrodes Y

1

-Y

n

of the PDP

20

with the variety of driving pulses at the timings shown in FIG.

5

A.

More specifically, the driving circuit

200

first generates a reset pulse RP

Y

having a pulse voltage of positive polarity as shown in

FIG. 5A

, and simultaneously applies the reset pulse RP

Y

to all the row electrodes Y

1

-Y

n

(simultaneous reset stage Rc).

The simultaneous reset stage Rc performed in this way causes a discharge to occur between the adjacent row electrodes X and Y, for example, between the respective row electrodes X and Y on display lines L

1

-L

8

in FIG.

4

. In this event, electrons and positive ions produced by the discharge are drawn by an electric field generated by a voltage between the row electrodes X and Y to form a wall charge of negative polarity on the row electrode Y. In this way, all the discharge cells are once set in “light emitting cells.”

Next, the driving circuit

200

converts an input video signal to pixel data corresponding to respective pixels which comprise one screen [(2n−1) rows×m columns] of the PDP

20

, and extracts from the pixel data those corresponding to odd-numbered display lines L

1

, L

3

, L

5

, . . . , L(2n−1). Then, the driving circuit

200

converts m pixel data for each odd-numbered display line to m pixel data pulses having voltages corresponding to respective logical levels. For example, the driving circuit

200

generates a pixel data pulse at a low voltage (zero volt) when the pixel data is at logical level “0,” and a pixel data pulse at a high voltage when the pixel data is at logical level “1.” Then, the driving circuit

200

sequentially applies the column electrodes D

1

-D

m

with the m pixel data pulses as a group of pixel data pulses DP

1

, DP

3

, DP

5

, . . . , DP

(2n−1)

, each for a corresponding one of the odd-numbered display lines L

1

-L(2n−1), as shown in FIG.

5

A. Further, the driving circuit

200

generates a scanning pulse SP having a pulse voltage of negative polarity and sequentially applies the scanning pulse SP to the row electrodes Y

1

-Yn simultaneously with the timing at which each of the pixel data pulses DP

1

, DP

3

, DP

5

, . . . , DP

(2n−1)

are applied (pixel data writing stage Wc

o

).

The pixel data writing stage Wc

o

performed as described above causes a discharge (selective erasure discharge) to occur in discharge cells which include column electrodes D applied with the high voltage pixel data pulse and row electrodes Y applied with the scanning pulse SP. For example, when the high voltage pixel data pulse is applied to the column electrode D

1

illustrated in FIG.

4

and the scanning pulse SP is applied to the row electrode Y

1

, the selective erasure discharge takes place in each of discharge cells which are formed at the intersection of the column electrode D

1

with the display line L

1

and at the intersection of the column electrode D

1

with the display line L

2

. As a result, wall charges are extinguished only in discharge cells, in which the selective erasure discharge took place, of all the discharge cells. Stated another way, in this event, the discharge cells, which have been initialized to the “light emitting cell” state in the simultaneous reset stage Rc, proceed to the “non-light emitting cell” state. On the other hand, the selective erasure discharge does not take place in those discharge cells which have been applied with the scanning pulse SP but applied also with the low voltage pixel data pulse, so that the currently formed wall charges are maintained therein. In other words, in the discharge cells which have been formed with the wall charges of negative polarity on the row electrodes Y thereof, resulting from the execution of the simultaneous reset stage Rc, the wall charges remain therein as they are, so that the discharge cells maintain the “light emitting cell” state.

Next, the driving circuit

200

generates a sustain pulse IP

XO

having a pulse voltage of positive polarity as shown in

FIG. 5A

, and repeatedly applies this sustain pulse IP

XO

to odd-numbered row electrodes X

1

, X

3

, X

5

, . . . , X

n−1

within the row electrodes X

1

-X

n

. After applying the first one of the sustain pulse IP

XO

, the driving circuit

200

generates a sustain pulse IP

YO

having a pulse voltage of positive polarity at a timing deviated from the timing at which the sustain pulse IP

XO

is applied, and repeatedly applies the sustain pulse IP

YO

to odd-numbered row electrodes Y

1

, Y

3

, Y

5

, . . . , Y

n−1

within the row electrodes Y

1

-Y

n

. Further, the driving circuit

200

generates a sustain pulse IP

XE

having a pulse voltage of positive polarity as shown in

FIG. 5A

at the same timing at which the sustain pulse IP

YO

is applied, and repeatedly applies the sustain pulse IP

XE

to even-numbered row electrodes X

2

, X

4

, X

6

, . . . , X

n

within the row electrodes X

1

-X

n

. Also, the driving circuit

200

generates a sustain pulse IP

YE

having a pulse voltage of positive polarity at the same timing at which the sustain pulse IP

XO

is applied, and repeatedly applies the sustain pulse IP

YE

to even-numbered row electrodes Y

2

, Y

4

, Y

6

, . . . , Y

n

within the row electrodes Y

1-Y

n

(light emission sustaining stage Ic

o

).

The light emission sustaining stage Ic

o

performed as described above causes a discharge (sustaining discharge) to occur when the odd-numbered row electrodes X

1

, X

3

, X

5

, . . . , X

n−1

are applied with the first sustain pulse IP

XO

as shown in

FIG. 5A

, due to the influence of the wall charges of negative polarity which remain on the row electrodes Y of the associated discharge cells. Then, after the sustaining discharge comes to an end, wall charges of negative polarity are formed on the row electrodes X of the discharge cells. On the other hand, since the sustain pulse IP

YE

as shown in

FIG. 5A

is applied to the even-numbered row electrodes Y

2

, Y

4

, Y

6

, . . . , Y

n

at the same timing as the sustain pulse IP

XO

, no discharge takes place in this event. In other words, since the wall charges of negative polarity have been formed on the row electrodes Y at the time the sustain pulse IP

YE

is applied, no discharge takes place even if the sustain pulse IP

YE

of positive polarity is applied to the row electrodes Y. Subsequently, as shown in

FIG. 5A

, when the sustain pulse IP

YO

of positive polarity is applied to the odd-numbered row electrodes Y

1

, Y

3

, Y

5

, . . . , Y

n−1

, a sustaining discharge takes place due to the influence of the wall charges of negative polarity formed on the row electrodes X. Then, after the sustaining discharge comes to an end, wall charges of negative polarity are formed on the row electrodes Y of the discharge cells. However, the sustaining discharge does not take place even if the first sustain pulse IP

EX

as shown in

FIG. 5A

is applied to the even-numbered row electrodes X

2

, X

4

, X

6

, . . . , X

n

at the same timing as the sustain pulse IP

YO

. However, the sustaining discharge does not take place even if the first sustain pulse IP

YO

as shown in

FIG. 5B

is applied to the odd-numbered row electrodes Y

1

, Y

3

, Y

5

, . . . Y

n−1

at the same time as the sustain pulse IP

XE

. Specifically, since the wall charges of negative polarity have been formed on the row electrodes X at the time the sustain pulse IP

XE

is applied, no discharge takes place even if the sustain pulse IP

XE

of positive polarity is applied to the row electrodes X. In the light emission sustaining stage Ic

o

, a sequence of the foregoing operations is repeatedly performed. Specifically, in the light emission sustaining stage Ic

o

, the sustain pulse trains IP

XO

, IP

YO

for promoting the discharge are alternately applied to the odd-numbered row electrodes X, Y, as shown in FIG.

5

A. Then, the sustain pulses IP

YE

, IP

XE

having the phases opposite to those of the sustain pulse trains IP

XO

, IP

YO

, as shown in

FIG. 5A

, are alternately applied to the even-numbered row electrodes Y, X for preventing erroneous discharges.

Thus, according to the driving sequence shown in

FIG. 5A

, the sustain discharge takes place only on the odd-numbered display lines L

1

, L

3

, L

5

, . . . , L(2n−1) to emit light for a display corresponding to an input video signal.

In an even field operation, on the other hand, the driving circuit

200

applies a variety of driving pulses to the column electrodes D

1

-D

m

, the row electrodes X

1

-X

n

, and the row electrodes Y

1

-Y

n

of the PDP

20

at timings as shown in FIG.

5

B.

Specifically, the driving circuit

200

first applies a reset pulse RP

Y

having a pulse voltage of positive polarity as shown in FIG.

5

B and simultaneously applies the reset pulse RP

Y

to all the row electrodes Y

1

-Y

n

(simultaneous reset stage Rc).

The simultaneous reset stage Rc performed in this way causes a discharge to occur between adjacent row electrodes X and Y, for example, between the respective row electrodes X and Y on the display lines L

1

-L

8

in FIG.

4

. In this event, electrons and positive ions produced by the discharge are drawn by an electric field generated by a voltage between the row electrodes X and Y to form a wall charge of negative polarity on the row electrode Y. In this way, all the discharge cells are once set in “light emitting cells.”

Next, the driving circuit

200

converts an input video signal to pixel data corresponding to respective pixels which comprise one screen [(2n−1) rows×m columns] of the PDP

20

, and extracts from the pixel data those corresponding to even-numbered display lines L

2

, L

4

, L

6

, . . . , L(2n−2). Then, the driving circuit

200

converts m pixel data for each even-numbered display line to m pixel data pulses having voltages corresponding to respective logical levels. For example, the driving circuit

200

generates a pixel data pulse at a low voltage (zero volt) when the pixel data is at logical level “0,” and a pixel data pulse at a high voltage when the pixel data is at logical level “1.” Then, the driving circuit

200

sequentially applies the column electrodes D

1

-D

m

with the m pixel data pulses as a group of pixel data pulses DP

2

, DP

4

, DP

6

, . . . , DP

(2n−2)

, each for a corresponding one of the even-numbered display lines L

2

-L(2n−2), as shown in FIG.

5

B. Further, the driving circuit

200

generates a scanning pulse SP having a pulse voltage of negative polarity and sequentially applies the scanning pulse SP to the row electrodes Y

1-Y

n

simultaneously with the timing at which each of the pixel data pulses DP

2

, DP

4

, DP

6

, . . . , DP

(2n−2)

in the group are applied (pixel data writing stage WC

E

).

The pixel data writing stage WC

E

performed as described above causes a discharge (selective erasure discharge) to occur in discharge cells which include column electrodes D applied with the high voltage pixel data pulse and row electrodes Y applied with the scanning pulse SP. For example, when the high voltage pixel data pulse is applied to the column electrode D

2

illustrated in FIG.

4

and the scanning pulse SP is applied to the row electrode Y

2

, the selective erasure discharge takes place in each of discharge cells which are formed at the intersection of the column electrode D

2

with the display line L

3

and at the intersection of the column electrode D

2

with the display line L

4

. As a result, wall charges are extinguished only in discharge cells, in which the selective erasure display took place, of all the discharge cells. Stated another way, in this event, the discharge cells, which have been initialized to the “light emitting cell” state in the simultaneous reset stage Rc, proceed to the “non-light emitting cell” state. On the other hand, the selective erasure discharge does not take place in those discharge cells which have been applied with the scanning pulse SP but applied also with the low voltage pixel data pulse, so that the currently formed wall charges are maintained therein. In other words, in the discharge cells which have been formed with the wall charges of negative polarity on the row electrodes Y thereof, resulting from the execution of the simultaneous reset stage Rc, the wall charges remain therein as they are, so that the discharge cells maintain the “light emitting cell” state.

Next, the driving circuit

200

generates a sustain pulse IP

XE

having a pulse voltage of positive polarity as shown in

FIG. 5B

, and repeatedly applies this sustain pulse IP

XE

to even-numbered row electrodes X

2

, X

4

, X

6

, . . . , X

n

within the row electrodes X

1-X

n

. After applying the first one of the sustain pulse IP

XE

, the driving circuit

200

generates a sustain pulse IP

YE

having a pulse voltage of positive polarity at a timing deviated from the timing at which the sustain pulse IP

XE

is applied, and repeatedly applies the sustain pulse IP

YE

to even-numbered row electrodes Y

2

, Y

4

, Y

6

, . . . , Y

n

within the row electrodes Y

1

-Y

n

. Further, the driving circuit

200

generates a sustain pulse IP

XO

having a pulse voltage of positive polarity as shown in

FIG. 5B

at the same timing at which the sustain pulse IP

YE

is applied, and repeatedly applies the sustain pulse IP

XO

to odd-numbered row electrodes X

1

, X

3

, X

5

, . . . , X

n−1

within the row electrodes X

1

-X

n

. Also, the driving circuit

200

generates a sustain pulse IP

YO

having a pulse voltage of positive polarity at the same timing at which the sustain pulse IP

XE

is applied, and repeatedly applies the sustain pulse IP

YO

to odd-numbered row electrodes Y

1, Y

3

, Y

5

, . . . , Y

n−1

within the row electrodes Y

1

-Y

n

(light emission sustaining stage IC

E

) The light emission sustaining stage IC

E

performed as described above causes a discharge (sustaining discharge) to occur when the even-numbered row electrodes X

2

, X

4

, X

6

, . . . , X

n

are applied with the first sustain pulse IP

XO

as shown in

FIG. 5B

, due to the influence of the wall charges of negative polarity which remain on the row electrodes Y of the associated discharge cells. Then, after the sustaining discharge comes to an end, wall charges are formed on the row electrodes X of the discharge cells. However, no sustaining discharge takes place even if the first sustain pulse IP

YO

as shown in

FIG. 5B

is applied to the odd-numbered row electrodes Y

1

, Y

3

, Y

5

, . . . , Y

n−1

at the same timing as the sustain pulse IP

XE

. In other words, since the wall charges of negative polarity have been formed on the row electrodes Y at the time the sustain pulse IP

YO

is applied, no sustaining discharge takes place even if the sustain pulse IP

YO

of positive polarity is applied to the row electrodes Y. Subsequently, as shown in

FIG. 5B

, when the first sustain pulse IP

YE

of positive polarity is applied to the even-numbered row electrodes Y

2

, Y

4

, Y

6

, . . . , Y

n

, a sustaining A discharge takes place due to the influence of the wall charges of negative polarity formed on the row electrodes X. Then, after the sustaining discharge comes to an end, wall charges of negative polarity are formed on the row electrodes Y of the discharge cells. However, the sustaining discharge does not take place even if the first sustain pulse IP

XO

of positive polarity as shown in

FIG. 5B

is applied to the odd-numbered row electrodes X

1

, X

3

, X

5

, . . . , X

n−1

at the same timing as the sustain pulse IP

YE

. Specifically, since the wall charges of negative polarity have been formed on the row electrodes X at the time the sustain pulse IP

XO

is applied, no discharge takes place even if the sustain pulse IP

XO

of positive polarity is applied to the row electrodes X. In the light emission sustaining stage IC

E

, a sequence of the foregoing operations is repeatedly performed.

Specifically, in the light emission sustaining stage IC

E

, the sustain pulse trains IP

XE

, IP

YE

for promoting the discharge are alternately applied to the even-numbered row electrodes X, Y, as shown in FIG.

5

B. Then, the sustain pulses IP

YO

, IP

XO

having the phases opposite to those of the sustain pulse trains IP

XE

, IP

YE

as shown in

FIG. 5B

, are alternately applied to the odd-numbered row electrodes Y, X for preventing erroneous discharges.

Therefore, according to the driving sequence shown in

FIG. 5B

, the sustaining discharge takes place only on the even-numbered display lines L

2

, L

4

, L

6

, . . . , L(2n−2) to emit light for a display corresponding to an input video signal.

It should be noted that the foregoing embodiment employs a so-called interlace driving sequence which temporally separates the driving for the odd-numbered display lines from the driving for the even-numbered display lines. In this event, when display lines in one group are driven, row electrodes belonging to display lines in the other group are applied with a sustain pulse train, the phase of which is opposite to that of the sustain pulse train applied to drive the display line in the one group. In this way, erroneous discharges are prevented between the even-numbered display lines and the odd-numbered display lines.

As described above, in the plasma display apparatus according to a first feature of the present invention, a pair of row electrodes is shared to drive the odd-numbered display lines and to drive the even-numbered display lines. Also, the plasma display apparatus employs, as a pixel data writing method, the so-called selective erasure address method which involves previously forming wall charges in all discharge cells, and selectively erasing the wall charges to set respective discharge cells in a light emitting cell state or a non-light emitting cell state corresponding to an input video signal. With this configuration, the number of display lines of pixels can be increased more than the number of row electrode pairs to provide a higher definition display and to reduce the power consumption.

Next, a second embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 6

generally illustrates the configuration of a plasma display apparatus according to a second feature of the present invention.

In

FIG. 6

, a driving control circuit

50

generates a variety of timing signals for driving a PDP

20

to emit light based on a subfield method, in response to a synchronization signal in an input video signal, and supplies the timing signals to a row electrode driving circuit

40

. The driving control circuit

50

also converts the input video signal to pixel data corresponding to respective pixels which comprise one screen [(2n−1) rows×m columns] of the PDP

20

, and groups the pixel data into m pixel data bits DB

1

-DB

m

for each display line. Then, in an odd-numbered field period, the driving control circuit

50

sequentially supplies the column electrode driving circuit

30

with the pixel data bits DB

1

-DBm corresponding to odd-numbered display lines L

1

, L

3

, L

5

, . . . , L(2n−1), respectively, for each odd-numbered display line. In an even-numbered field period, on the other hand, the driving control circuit

50

sequentially supplies the column electrode driving circuit

30

with the pixel data bits DB

1

-DB

m

corresponding to even-numbered display lines L

2

, L

4

, L

6

, . . . , L(2n−2), respectively, for each even-numbered display line. The driving control circuit

50

also generates switching signals SW

1

-SW

4

, each of which varies in accordance with a predetermined sequence, in synchronism with the timing at which the pixel data bit DB is supplied for each display line, and supplies the column electrode driving circuit

30

with these switching signals SW

1

-SW

4

.

The column electrode driving circuit

30

generates m pixel data pulses having voltages corresponding to logical levels of the respective pixel data bits DB

1

-DB

m

in response to the switching signals SW

1

-SW

4

, and applies column electrodes D

1

-D

m

of the PDP

20

simultaneously with these pixel data pulses.

FIG. 7

illustrates the internal configuration of the column electrode driving circuit

30

.

As illustrated in

FIG. 7

, the column electrode driving circuit

30

comprises a power supply circuit

31

and a pixel data pulse generator circuit

32

.

The power supply circuit

31

includes a capacitor C

1

which has one end connected to a PDP ground potential Vs serving as a ground potential of the PDP

20

. A switching element S

1

is in OFF state when it is supplied with the switching signal SW

1

at logical level “0” from the driving control circuit

50

. On the other hand, the switching element S

1

turns ON when the switching signal SW

1

changes to logical level “1” to apply a potential generated at the other end of the capacitor C

1

to a power supply line

2

through a coil L

1

and a diode DD

1

. This causes the capacitor C

1

to begin discharging, and a potential resulting from the discharge is applied onto the power supply line

2

. A switching element S

2

is in OFF state when it is supplied with the switching signal SW

2

at logical level “0” from the driving control circuit

50

. On the other hand, the switching element S

2

turns ON when the switching signal SW

2

changes to logical level “1” to apply the potential on the power supply line

2

to the other end of the capacitor C

1

through a coil L

2

and a diode DD

2

. In this event, the capacitor C

1

is charged with the potential on the power supply line

2

. A switching element S

3

is in OFF state when it is supplied with the switching signal SW

3

at logical level “0” from the driving control circuit

50

. On the other hand, the switching element S

3

turns ON when the switching signal SW

3

changes to logical level “1” to apply a power supply potential Va generated by a DC power supply B

1

onto the power supply line

2

. The DC power supply B

1

has a negative terminal grounded at the PDP ground potential Vs. A switching element S

4

is in OFF state when it is supplied with the switching signal SW

4

at logical level “0” from the driving control circuit

50

. On the other hand, the switching element S

4

turns ON when the switching signal SW

4

changes to logical level “1” to ground the power supply line

2

to the PDP ground potential Vs.

The pixel data pulse generator circuit

32

comprises switching elements SWZ

1

-SWZ

m

and SWZ

10

-SWZ

m0

which are independently controlled ON/OFF in response to one line (m) of pixel data bits DB

1

-DB

m

supplied from the driving control circuit

50

. Each of the switching elements SWZ

1

-SWZ

m

remains in ON state as long as the pixel data bit DB supplied thereto is at logical level “1” to apply a potential existing on the power supply line

2

to the column electrodes D

1

-D

m

of the PDP

20

. Each of the switching elements SWZ

10

-SWZ

m0

remains in ON state as long as the corresponding pixel data bit DB is at logical level “0” to ground a potential on an associated column electrode to the PDP ground potential Vs.

FIG. 8

is a timing chart showing waveforms which represent internal operations in the column electrode driving circuit

30

.

First, the driving control circuit

50

supplies the power supply circuit

31

with the switching signals SW

2

-SW

4

at logical level “0” and the switching signal SW

1

at logical level “1” (driving stage G

1

). This causes only the switching element S

1

of the switching elements S

1

-S

4

to turn ON to discharge a charge accumulated on the capacitor C

1

. Therefore, when the pixel data bit DB is at logical level “1” for this period, a switching element SWZ

1

turns ON, allowing a current to flow into a column electrode Di through the coil L

1

, diode DD

1

, switching element S

1

and switching element SWZ

i

. Then, a load capacitance C

o

of the PDP

20

is charged with this current. In this event, the potential on the column electrode Di gradually increases by a time constant determined by the coil L

1

and the load capacitance C

o

as shown in FIG.

8

.

The driving control circuit

50

switches only the switching signal SW

3

to logical level “1” at the time one half of a resonance period, determined by the coil L

1

and the load capacitance C

o

, is elapsed (driving stage G

2

). This causes the switching element S

3

to turn ON to apply the power supply potential Va generated by the DC power supply B

1

onto the power supply line

2

, so that the potential on the column electrode D

i

is fixed to the power supply potential Va as shown in FIG.

8

.

Next, the driving control circuit

50

switches the switching signal SW

1

to logical level “0” (driving stage G

3

). This causes the switching element S

1

to turn OFF to stop a resonant operation by the coil L

1

and the load capacitance C

o

.

Next, the driving control circuit

50

switches the switching signal SW

2

to logical “1” and the switching signal SW

3

to logical level “0,” respectively (driving stage G

4

).

This results in discharging the charge accumulated on the load capacitance C

o

. Therefore, a current flows into the capacitor C

1

through the switching element SWZ

i

, coil L

2

, diode DD

2

and switching element S

2

to charge the capacitor C

1

. In this event, the potential on the column electrode Di gradually decreases by a time constant determined by the coil L

2

and the load capacitance C

o

, as shown in FIG.

8

.

Then, at the time one half of the resonance period, determined by the coil L

1

and the load capacitance, is elapsed, the driving control circuit

50

supplies the power supply circuit

31

with the switching signal SW

4

at logical level “1” in the form of short pulse in order to turn ON the switching element S

4

only for a predetermined short period of time (driving stage G

5

). This causes the power supply line

2

to be grounded to the PDP ground potential Vs only for the short period of time. Meanwhile, a current flows into the switching element S

4

from the PDP

20

through the switching element SWZ

i

and the power supply line

2

.

The driving control circuit

50

repeatedly supplies the column electrode driving circuit

30

with the switching signals SW

1

-SW

4

having a sequence as shown in

FIG. 8

to repeatedly perform a sequence of operations consisting of the driving stages G

1

-G

5

. During this sequence of operations, when the pixel data bit DB is at logical level “1,” the power supply potential Va generated on the power supply line

2

is applied to the column electrode D, as shown in

FIG. 8

, and serves as a high voltage pixel data pulse. On the other hand, when the pixel data bit DB is at logical level “0,” causing a switching element SWZ

i0

to turn ON, the column electrode D is grounded to the PDP ground potential Vs which serves as a low voltage pixel data pulse.

As described above, in the column electrode driving circuit

30

, a charge accumulated on the capacitor C

1

is selectively discharged through a first switching current path comprised of the coil L

1

, diode DD

1

and switching element S

1

to generate a rising edge of a pixel data pulse. Next, the power supply potential is applied on the power supply line

2

through a second switching current path comprised of the DC power supply B

1

and the switching element S

3

to generate the pulse voltage Va as the pixel data pulse. Next, the capacitor C

1

is charged selectively with a charge accumulated on the load capacitance C

o

existing on column electrodes through the power supply line

2

for recovering the charge through a third switching current path comprised of the coil L

2

, diode DD

2

and the switching element S

2

, to generate a falling edge of the pixel data pulse. Then, finally, the power supply line

2

is forcedly grounded only for a predetermined short period of time through the switching element S

4

as a fourth switching current path to determine a minimum potential as the pixel data pulse.

As described above, the column electrode driving circuit

30

is configured to generate the pixel data pulse through the resonance-based operation using the resonance circuit comprised of a capacitor and a coil. Since the pixel data pulse can be generated with a DC power supply having a lower voltage value than a peak value of the pixel data pulse, the power consumption can be reduced.

The row electrode driving circuit

40

generates a variety of driving pulses (later described) in response to a variety of timing signals supplied from the driving control circuit

50

, and applies the driving pulses to the row electrodes X

1

-X

n

and the row electrodes Y

1

-Y

n

.

Since the row electrode driving circuit

40

and the column electrode driving circuit

30

apply the PDP

10

with a variety of driving pulses at applying timings in one subfield identical to those shown in

FIGS. 5A

,

5

B, description thereon will not be repeated.

While the foregoing embodiment has been described for an example in which a resonance circuit is used as the power supply circuit

31

of the column electrode driving circuit

30

, a pump up circuit may be employed instead of the resonance circuit.

FIG. 9

illustrates the internal configuration of a column electrode driving circuit

30

′ which employs a pump up circuit as a power supply circuit.

As illustrated in

FIG. 9

, the column electrode driving circuit

30

′ comprises a power supply circuit

31

′ and a pixel data pulse generator circuit

32

′.

In the power supply circuit

31

′, a DC power supply B

2

has a positive terminal connected to a power supply line

2

through a diode D

10

, and a negative terminal grounded to a PDP ground potential Vs. A switching element S

11

has one end connected to the positive terminal of the DC power supply B

2

and the other end connected to one end of a capacitor C

10

. A switching element S

12

has one end connected to the one end of the capacitor C

10

and the other end grounded to the PCP ground potential Vs. The capacitor C

10

has the other end connected to the power supply line

2

.

The switching element S

11

is in OFF state when it is supplied with a switching signal SW

11

at logical level “0” from the driving control circuit

50

. The switching element S

12

is in ON state when it is supplied with a switching signal SW

12

at logical level “1” from the driving control circuit

50

. Then, when the switching element S

11

is in OFF state and the switching element S

12

is in ON state, a power supply potential Vd/

2

is applied onto the power supply line

2

by the DC power supply B

2

through the diode D

10

, and the one end of the capacitor C

10

is grounded to the PDP ground potential Vs.

When the switching signal SW

11

is at logical level “1” and the switching signal SW

12

is at logical level “0,” the switching element S

11

turns ON and the switching element S

12

turns OFF, causing a potential produced at the other end of the capacitor C

10

to be applied onto the power supply line

2

. In this way, the capacitor C

10

starts discharging, and the power supply line

2

is applied with a potential Vd which is the sum of a potential Vd/

2

produced by the discharge and the power supply potential Vd/

2

.

The pixel data pulse generator circuit

32

′ comprises switching elements SWD

1

-SWD

m

and SWD

1

-SWD

m0

which are independently controlled ON/OF in response to one line (m) of corresponding pixel data bits DB

1

-DB

m

supplied from the driving control circuit

50

. Also, diodes DD

11

-DD

m1

are connected in parallel with the switching elements SWD

1

-SWD

m

, while diodes DD

12

-DD

m2

are connected in parallel with the switching elements SWD

10

-SWD

n0

. Each of the switching elements SWD

1

-SWD

m

is in ON state as long as a pixel data bit DB supplied thereto is at logical level “1” to apply a potential existing on the power supply line

2

to row electrodes D

1

-D

m

of the PDP

10

. Each of the switching elements SWD

10

-SWD

m0

is in ON state as long as a pixel data bit DB supplied thereto is at logical level “0” to ground potentials on the column electrodes D

1

-D

m

to the PDP ground potential Vs.

FIG. 10

is a timing chart showing waveforms which represent internal operations in the column electrode driving circuit

30

′ illustrated in FIG.

9

.

First, the driving control circuit

50

supplies the switching signal SW

11

at logical level “0” and the switching signal SW

12

at logical level “1” (driving stage G

10

). This causes the switching element S

11

to turn OFF and the switching element S

12

to turn ON, resulting in the potential on the power supply line

2

equal to the power supply potential Vd/2.

In the meantime, when the pixel data bit DB is at logical level “0,” a switching element SWD

i

turns OFF, and a switching element SWD

i0

turns ON, resulting in the potential on a column electrode D

i

equal to the PDP ground potential Vs.

On the other hand, when the pixel data bit DB is at logical level “1,” the switching element SWD

i

turns ON, and the switching element SWD

i0

turns OFF, causing a current to flow from the DC power supply B

2

to the column electrode D

i

through the diode D

10

and the switching element SWD

i

. Then, a load capacitance C

0

of the PDP

10

is charged with this current, causing the potential on the column electrode D

i

to increase to the power supply potential Vd/2 (driving stage G

11

).

Next, at the time a predetermined period of time is elapsed from the time at which the pixel data bit DB changes to logical level “1,” the switching signal SW

11

is switched to logical level “1” and the switching signal SW

12

is switched to logical level “0,” respectively (driving stage G

12

). Thus, the power supply line

2

is applied with a potential Vd which is the sum of the power supply potential Vd/2 and the potential Vd/2 on the capacitor C

10

, causing the capacitor C

10

to begin discharging, followed by a current flowing into the column electrode D

i

through the switching element S

11

, capacitor C

10

and the switching element SWD

i

. Then, the load capacitance C

o

of the PDP

10

is charged with this current, and the potential on the column electrode D

i

is increased from the power supply potential Vd/2 to the potential Vd by the potential Vd/2 generated by the discharging capacitor C

10

.

Next, at the time a predetermined period of time is elapsed from the time at which the switching signal SW

11

changes to logical level “1,” the switching signal SW

11

is switched to logical level “0” and the switching signal SW

12

is switched to logical level “1,” respectively (driving stage G

13

). Thus, the charge accumulated on the load capacitance C

0

is discharged. As a result, a current flows through the switching element SWD

i

, capacitor C

10

and switching element S

12

, and charges the capacitor C

10

. In this event, the potential on the column electrode D

i

and the potential on the power supply line

2

are decreased from Vd to Vd/2 (power supply potential) by the potential Vd/2.

Next, when the pixel data bit DB changes to logical level “0” at the time a predetermined period of time is elapsed from the time at which the switching signal S

11

changes to logical level “0,” the switching element SWD

i

turns OFF, and the switching element SWD

i0

turns ON (driving stage G

14

). Thus, the charge accumulated on the load capacitance C

0

is discharged. As a result, a current flows through the switching element SWD

i0

, and the potential on the column electrode D

i

is grounded to the PDP ground potential Vs.

The driving control circuit

50

repeatedly supplies the column electrode driving circuit

20

′ with the switching signals SW

11

, SW

12

, which have a sequence as shown in

FIG. 10

, to repetitively execute a sequence of operations comprised of the driving stages G

10

-G

14

. In the meantime, when the pixel data bit DB is at logical level “1,” the potentials Vd/2, Vd produced on the power supply line

2

are applied to a column electrode D and serves as a high voltage pixel data pulse, as shown in FIG.

10

. On the other hand, when the pixel data bit DB is at logical level “0,” the switching element SWD

i0

turns ON, and the column electrode D is grounded to the PDP ground potential Vs which serves as a low voltage pixel data pulse.

As described above, in the column electrode driving circuit

30

′, the power supply line

2

is applied with the power supply potential Vd/2 through a current path comprised of the DC power supply B

2

and the diode D

10

. Then, the power supply line

2

is applied with the potential Vd which is produced by selectively adding the potential Vd/2 on the capacitor C

10

, on which a charge has been accumulated, to the power supply potential Vd/2 through a first switching current path comprised of the switching element S

11

. Further, the capacitor C

10

is charged selectively with a charge accumulated on the load capacitance C

o

through the power supply line

2

for recovering the charge through a second switching current path comprised of the switching element S

12

.

Therefore, according to the column electrode driving circuit

30

′ which employs the pump up circuit as illustrated in

FIG. 9

, the pixel data pulse presents an output waveform which includes stepped rising and falling edges as shown in

FIG. 10

, so that the power consumption is reduced.

As described above, in the plasma display apparatus according to a second feature of the present invention, a pair of row electrodes X, Y is commonly used for driving odd-numbered display lines as well as for driving even-numbered display lines. Thus, since the number of display lines on the screen can be increased more than the number of row electrode pairs, a high definition display can be achieved. Further, in the present invention, the resonance, produced by a resonance circuit, is utilized to generate a pixel data pulse having a predetermined pulse voltage value which is applied to row electrodes. Since the pixel data pulse can be generated with a DC power supply having a lower voltage value than a peak value of the pixel data pulse, the power consumption can be reduced.

Number	Date	Country	Kind
2000-030071	Feb 2000	JP
2000-044630	Feb 2000	JP

Number	Name	Date	Kind
5446344	Kanazawa	Aug 1995	A
5877734	Amemiya	Mar 1999	A
6317105	Eo et al.	Nov 2001	B1
6496164	Kuwahara et al.	Dec 2002	B1

Plasma display apparatus

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (2)

US Referenced Citations (4)