Patent Application
20070080901
This application claims priority to and the benefit of Korean Patent Application No. 10-2005-0095997 filed in the Korean Intellectual Property Office on Oct. 12, 2005, the entire contents of which is incorporated herein by reference.
(a) Field of the Invention
The present invention relates to a plasma display device and a driving method thereof.
(b) Description of the Related Art
A plasma display panel (PDP) is a flat panel display that uses plasma generated by gas discharge to display characters or images.
According to a driving method of such a plasma display device, one frame is divided into a plurality of subfields, each having weight values.
Each subfield has an address period in which an address operation for selecting discharge cells to emit light from among a plurality of discharge cells, and a sustain period in which a sustain discharge occurs in the selected discharge cells to perform a display operation.
At this time, in order to select a turn-on discharge cell (or on-cell) among discharge cells formed at regions at which display lines and address electrodes cross, a scan pulse is applied to the respective display lines. Also, in order to apply a scan pulse to the respective display lines, scan circuits for selecting the respective display lines are provided. Such scan circuits are connected to correspond to the scan electrodes.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
One aspect of the present invention provides a plasma display device and a driving method thereof having advantages of reducing the number of scan circuits and normally generating a weak discharge during a main reset period.
Another aspect of the present invention provides a driving method of a plasma display device having a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed crossing the first electrodes and the second electrodes is provided. The driving method includes, at a first subfield, selecting light-emitting cells using a first address scheme for converting the state of the light-emitting cells to a non-light-emitting cell state during an address period, alternately applying a first voltage that is a sustain discharge voltage to the plurality of first and second electrodes during a sustain period, and increasing a second voltage corresponding to a voltage difference between the plurality of first and second electrodes to a third voltage that is greater than the first voltage during a first period; and at a second subfield, generating a sustain discharge after selecting the light-emitting cells using a second address scheme for converting the non-light-emitting cell state to the light-emitting cell state.
Another aspect of the present invention provides a driving method of a plasma display device having a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed crossing the first electrodes and the second electrodes is provided. The driving method includes, at a first subfield, selecting light-emitting cells using a first address scheme for converting the state of the light-emitting cells to a non-light-emitting cell state and generating a sustain discharge in the selected cells, and during a first period, generating a discharge in the cells having been converted to the non-light-emitting cell state by the first address scheme and the cells having undergone a sustain discharge; and at a second subfield, generating a reset discharge so as to initialize all the discharged cells.
Still another aspect of the present invention provides a plasma display device is provided. The plasma display device includes a PDP including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed crossing the first electrodes and the second electrodes; and a driver for applying a voltage such that a voltage difference between the plurality of first and second electrodes is greater than a first voltage during a first period between a first subfield and a second subfield, the first subfield alternately applying the first voltage to the plurality of first and second electrodes using a first address scheme for converting the state of light-emitting cells to a non-light-emitting cell state during a sustain period, and the second subfield using a second address scheme for converting the state of the non-light-emitting cells to the light-emitting cell state.
In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.
When it is described that an element “includes” another element, it is meant that the element may further include the other element but not excluding others.
The wall charges being described in embodiments of the present invention mean charges formed on a wall close to each electrode of a discharge cell. The wall charge will be described as being “formed” or “accumulated” on the electrode, although the wall charge do not actually touch the electrodes. Further, a wall voltage means a potential difference formed on the wall of the discharge cell by the wall charge.
First, a configuration of a plasma display device according to an exemplary embodiment of the present invention will be described with reference to
Referring to
The PDP 100 includes a plurality of address electrodes A1 to Am extending in a column direction, a plurality of sustain electrodes X1 to Xn extending in a row direction, and a plurality of scan electrodes Y1 to Yn extending in a row direction.
The controller 200 receives an external video signal and outputs an address driving control signal, a sustain electrode driving control signal, and a sustain electrode driving control signal. In addition, the controller 200 controls the plasma display device by dividing a frame into a plurality of subfields having respective brightness weight values. Further, according to an exemplary embodiment of the present invention, the controller 200 controls the plasma display device such that even-numbered X electrodes (Xeven) and odd-numbered X electrodes (Xodd) of the plurality of X electrodes X1 to Xn are differently driven.
The address electrode driver 300 receives the address electrode driving control signal from the controller 200 and applies a driving voltage to the address electrodes.
The scan electrode driver 400 receives the scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrodes.
The sustain electrode driver 500 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrodes.
As shown in
Discharge cells 28 are formed at respective discharge spaces formed at regions which these display lines L1 to L2n−1 cross the address electrodes A1 to Am. The discharge cells 28 are partitioned in the row direction by barrier ribs 29. Such sustain electrodes X1 to Xn and scan electrodes Y1 to Yn include bus electrodes 31a and 32a having a narrow width and transparent electrodes 31b and 32b having a wide width, which are extended in a row direction. The transparent electrodes 31b and 32b are respectively connected with the bus electrodes 31a and 32a. Alternatively, only the bus electrodes 31a and 32a may form the sustain and scan electrodes without the transparent electrodes 31b and 32b, or only the transparent electrodes 31b and 32b may form the sustain and scan electrodes without the bus electrodes 31a and 32a. In addition, barrier ribs (not shown in
According to a first exemplary embodiment of the present invention, since the sustain and scan electrodes are arranged such that they respectively share the two adjacent display lines, it is possible to reduce the number of sustain and scan electrodes in comparison with the conventional structure that uses one sustain electrode and one scan electrode for one display line. For example, when 512 display lines are driven, 512 sustain and scan electrodes are required in the conventional plasma display panel. However, according to one embodiment of the present invention, it is sufficient for the plasma display panel to have half of 512 sustain and scan electrodes because of the shared structure. In this embodiment, the PDP 100 may have approximately twice the number of display lines as the number of scan and sustain electrodes. Accordingly, given the same resolution, the number of scan and sustain electrodes in one embodiment of the invention may be reduced approximately by half compared to the conventional PDP.
Such a structure of the PDP 100 is merely one example. Accordingly, other panel structures may be applied to an exemplary embodiment of the present invention if the driving waveforms described below can be applied.
The difference between the
Therefore, the number of display lines is reduced to half (i.e., n) in comparison with the first exemplary embodiment. Accordingly, when a PDP is designed to have the same resolution as that of the first exemplary embodiment, the number of sustain and scan electrodes is doubled. However, in the case of the electrode arrangement according to the second exemplary embodiment, a scan pulse is simultaneously applied to two scan electrodes during the respective address periods when a driving method described below is applied. In this case, the driving method described below may be equally applied except that one scan circuit is connected to two scan electrodes so that the scan pulse is simultaneously applied to two scan electrodes during the respective address periods.
A driving method of a plasma display device having a PDP structure according to the first and second exemplary embodiments of the present invention will be described hereinafter. For convenience of description, a driving method of a plasma display device will be described based on only the PDP of the first exemplary embodiment of the present invention shown in
Hereinafter, an “Xodd line cell” is referred to as a discharge cell on the display lines formed between the odd-numbered sustain electrodes (Xodd) and the scan electrodes Y1 to Yn, and an “Xeven line cell” is referred to as a discharge cell on the display lines formed between the even-numbered sustain electrodes (Xeven) and the scan electrodes Y1 to Yn. In addition, a discharge cell having wall charges appropriately formed to generate a sustain discharge during the sustain period is called a “light-emitting cell (or on-cell)”, and a discharge cell having wall charges appropriately formed to not generate a sustain discharge during the sustain period is called a “non-light-emitting cell (or off-cell)”. In addition, a “main reset period MR” represents a reset period for generating a reset discharge in all cells that have undergone or have not undergone the sustain discharge at the previous subfield, thereby initializing all the cells, and a “selective reset period SR” represents a reset period for generating a reset discharge in only the cells that have undergone a sustain discharge at the previous subfield, thereby initializing only the same. Meanwhile, a “write address period WA” is referred to as one address period for applying an addressing method (i.e., a write addressing method) for generating an address discharge such that a non-light-emitting cell state is changed to a light-emitting cell state, and an “erase address period EA” is referred to as another address period for applying an addressing method (i.e., an erase addressing method) for generating an address discharge such that a light-emitting cell state is changed to a non-light-emitting cell state.
In one embodiment, as shown in
At the first to third subfields SF1 to SF3 of the odd-numbered frame, the respective subfield is operated for the Xodd line cells and is not operated for the Xeven line cells. In addition, at the first to third subfields SF1 to SF3 of the even-numbered frame, the respective subfield is operated for the Xeven line cells and is not operated for the Xodd line cell. As a result, the first to third subfields SF1 to SF3 emit light every two frames. That is, low grayscales of the first to third subfields SF1 to SF3 express all cells through two frames, i.e., one odd-numbered frame and one even-numbered frame. In another embodiment, the subfields for the low grayscales may be changed to, for example, SF1 to SF2, SF1 to SF4 or SF1 to SF5 depending on applications.
The first subfield SF1 of the odd-numbered frame includes a main reset period MR, a write address period WA, and a sustain period S. Subsequently, the second and third subfields SF2 and SF3 respectively include a selective reset period SR, a write address period WA, and a sustain period S. As described above, at the first to third subfields SF1 to SF3 of the odd-numbered frame, the reset period, the address period, and the sustain period are performed only for the Xodd line cells. Meanwhile, in
Subsequently, at the fourth subfield SF4 of the odd-numbered frame, the main reset period MR, a first write address period WA1, and a first sustain period S1 are sequentially performed for the Xodd line cells, and then the main reset period MR, the first write address period WA1, and the second sustain period S2 are sequentially performed for the Xeven line cells. At this time, the main reset period MR is performed for the Xeven line cells to initialize the same because no operations are performed for the Xeven line cells at previous subfields (i.e., the first to third subfields SF1 to SF3). When the sustain discharge is generated at the second sustain period S2, the sustain discharge is repeatedly generated for the Xodd line cell because the sustain discharge had been generated during the first sustain period S1.
At the fifth to tenth subfields SF5 to SF10, each subfield is operated for all the cells Xodd and Xeven. The fifth to tenth subfields SF5 to SF10 respectively include erase address periods EA1 and EA2 and sustain periods S1 and S2. At the fifth to tenth subfields SF5 to SF10, the first erase address period EA1 and the first sustain period S1 are sequentially performed for the Xodd line cells, and then the second erase address period EA2 and the second sustain period S2 are sequentially performed for the Xeven line cell. All the cells that had undergone a sustain discharge during the sustain period of the fourth subfield SF4 are in the light-emitting cell state. Accordingly, at the erase periods EA1 and EA2 of the fifth subfield SF5, the cells to be selected among the light-emitting cells are set as the non-light-emitting cell state. In addition, at the respective erase address periods EA1 and EA2 of the sixth to tenth subfields SF6 to SF10, the cells to be set as the non-light-emitting cell state are selected among the cells (i.e., light-emitting cells) that have undergone a sustain discharge at the sustain period of the previous subfield. In
Meanwhile, a driving method of the even-numbered frame is substantially the same as that of the odd-numbered frame except that the operation order is reversed for the Xodd line cells and the Xeven line cells. Accordingly, the driving method of the even-numbered frame will not be described in detail. That is, at the first to the third subfields SF1 to SF3 of the even-numbered frame, the reset period, the write address period, and the sustain period are respectively performed only for the Xeven line cells, and at the fourth subfield SF4, the reset period, the write address period, and the sustain period are respectively performed for the Xeven line cells and then for the Xodd line cells. In addition, at the fifth to tenth subfields SF5 to SF10 of the even-numbered frame, the erase address period and the sustain period are respectively performed for the Xeven line cells and then for the Xodd line cells.
In
A driving waveform of a plasma display panel according to a first embodiment of the present invention is hereinafter described in detail with reference to
As shown in
The main reset period MR of the first subfield SF1 includes an erase period I, a rising period II, and a falling period III.
During the erase period I of the main reset period MR, a voltage of the scan electrodes Y1 to Yn gradually decreases from a voltage Vs to a reference voltage (0V in
Subsequently, the voltage of the scan electrodes Y1 to Yn gradually increases from the voltage Vs to the voltage Vset during the rising period (II) of the main reset period (MR), while the voltage Ve and the reference voltage 0V are respectively applied to the even-numbered and odd-numbered sustain electrodes Xeven and Xodd. In addition, the reference voltage 0V is applied to the address electrodes A1 to Am. Since the reference voltage 0V is applied only to the odd-numbered sustain electrodes Xodd, a weak discharge, that is, a reset discharge is generated between the odd-numbered sustain electrodes Xodd and scan electrodes (hereinafter called “Yxo”) for forming display lines therewith among all the scan electrodes Y1 to Yn, and since the voltage Ve is applied to the even-numbered sustain electrodes Xeven, a weak discharge, that is, a reset discharge is not generated between the even-numbered sustain electrodes Xeven and the scan electrodes (hereinafter called “Yxe”) for forming display lines therewith. In the electrode arrangement of the
In addition, during the falling period III of the main reset period MR, the voltage applied to the scan electrodes Y1 to Yn is gradually decreased from the voltage Vs to the voltage Vnf. At this time, the reference voltage 0V is applied to the even-numbered scan electrodes Xeven, the voltage Ve is applied to the odd-numbered scan electrodes Xodd, and the reference voltage 0V is applied to the address electrodes A1 to Am. As a result, the weak reset discharge is generated between the scan electrodes Yxo and the odd-numbered sustain electrodes Xodd and between the scan and address electrodes Y1 to Xn and A1 to Am, while the voltage of the scan electrodes Y1 to Yn is decreased. Thus, the negative (−) wall charge formed on the scan electrodes Yxo, the positive (+) wall charge formed on the odd-numbered sustain electrodes Xodd, and the positive (+) wall charge formed on the address electrodes A1 to Am are erased. However, as described above, the reset discharge is not generated between the scan electrodes Yxe and the even-numbered sustain electrodes Xeven, since the weak discharge is not generated between the scan electrodes Yxe and the even-numbered sustain electrodes Xeven in the rising period II, and the reference voltage 0V is applied to the even-numbered sustain electrodes Xeven in the falling period III. Therefore, the reset discharge is generated only in the Xodd line cells so that the Xodd line cells are initialized into the non-light-emitting cell state and come to have the wall charge state appropriate for the addressing. Generally, the voltages Ve and Vnf are set such that the wall voltage between the scan electrodes Yxo and the odd-numbered sustain electrodes Xodd becomes near 0V, and accordingly, the discharge cell that has not undergone an address discharge in the address period may be prevented from misfiring in the sustain period. In addition, the wall voltage between the scan and address electrodes Yxo and A1 to Am is determined by the voltage Vnf because the address electrodes A1 to Am are maintained at the reference voltage 0V.
In such a main reset period of the first subfield SF1, the reset discharge is generated only in the Xodd line cells so that the Xodd line cells have the wall charge state appropriate for the addressing. However, the reset discharge is not generated in the Xeven line cells, and accordingly the Xeven line cells may have the wall charge state appropriate for the addressing. The wall charge state of the Xodd line cells becomes the non-light-emitting state by the reset discharge.
Subsequently, in order to select cells to have the light-emitting cell state among the Xodd line cells, during the write address WA of the first subfield SF1, in the first exemplary embodiment, a scan pulse having a voltage Vscl is sequentially applied to the scan electrodes Y1 to Yn and the voltage Vsch is applied to the scan electrodes not applied with the voltage Vscl. Furthermore, in the second exemplary embodiment, the scan pulse having the voltage Vscl is sequentially applied to two adjacent scan electrodes Y1 and Y2, Y3 to Y4, and Y5 and Y6, and the voltage Vsch is applied to the scan electrodes that are not applied with the voltage Vscl. For example, in the
As such, in order to select cells to emit light in the sustain period during the write address period WA of the first subfield SF1, the corresponding cells among the Xodd line discharge cells generate a discharge and form the wall charges thereon such that the non-light-emitting cell state is changed to the light-emitting cell state.
In the sustain period S of the first subfield SF1, a sustain pulse having a sustain discharge voltage Vs is alternately applied to the scan electrodes Y1 to Yn and the sustain electrodes Xodd and Xeven. By means of such a sustain pulse, the sustain discharge is generated in the predetermined cells during the write address period WA of the first subfield, such that the predetermined cells come to have the light-emitting cell state. In this case, the number of sustain pulses is selected appropriately for the weight values of the first subfield.
A driving waveform applied to the second and third subfields SF2 and SF3 is substantially the same as the driving waveform applied to the first subfield SF1, except that the different driving waveform is applied in the reset period. Accordingly, it is not described in detail.
As shown in
The negative (−) wall discharges and the positive (+) wall charges are respectively formed on the scan and sustain electrodes of the cells that have experienced a sustain discharge (that is, the cells that have undergone a sustain discharge during the first subfield among the Xodd line cells), because the last sustain pulse is applied to the scan electrodes Y1 to Yn during the sustain period of the first subfield SF1, that is, the previous subfield of the second subfield SF2. The voltage that has gradually decreased from the voltage Vs to the voltage Vnf is applied to the scan electrodes Y1 to Yn, while the reference voltage 0V and the voltage Ve are respectively to the even-numbered and odd-numbered sustain electrodes Xeven and Xodd. The reset discharge is then generated in the cells that have undergone a sustain discharge during the sustain period of the first subfield SF1. However, the reset discharge is not generated in the cells that have not undergone a sustain discharge during the sustain period of the first subfield SF1 among the Xodd line cells since the cells maintain the wall charge state of the main reset period MR of the first subfield SF1. That is, because the cells that have not experienced a sustain discharge during the first subfield SF1 among the Xodd line cells maintain the wall charge state after the main reset period MR, the reset discharge is not needed again in the cells. Accordingly, by applying the voltage that decreases from the voltage Vs to the voltage Vnf to the scan electrodes Y1 to Yn, the reset discharge is generated only in the cells that have undergone a sustain discharge during the first subfield SF1. Meanwhile, since the voltage Ve is only applied to the odd-numbered sustain electrodes Xodd in the selective reset period SR of the second subfield, the reset discharge is generated only in the cells that have undergone a sustain discharge during the first subfield SF1. Therefore, all the Xodd line cells are initialized to the non-light-emitting cell state because the reset discharge is generated in the cells that have undergone a sustain discharge during the selective reset period SR of the second subfield SF2, and the state of the wall charges after the main reset period MR of the first subfield SF1 is maintained in the cells that have not undergone a sustain discharge in the first subfield SF1 among the Xodd line cells.
Meanwhile, the selective reset period SR of the third subfield SF3 is operated in the same manner as the reset period SR of the second subfield. Accordingly, the driving method of the selective period SR of the third subfield SF3 will not be described in detail. The respective sustain periods of the second subfield SF2 and the third subfield SF3 have the number of sustain discharge pulses set appropriately for the weight values of the corresponding subfield.
Through such a driving waveform shown in
First, a selective reset period SR, a first write address period WA1, and a first sustain period S1 are performed for the Xodd line cells. As shown in
Subsequently, the main reset period MR, the second write address period WA2, and the second sustain period S2 are performed for the Xeven line cells.
As shown in
Subsequently, the write address operation is performed only for the Xeven line cells, because the voltage Ve and the reference voltage 0V are respectively applied to the even-numbered and odd-numbered sustain electrodes Xeven and Xodd even during the second write address period WA2 in the inverse of the write address period WA of the first subfield SF1.
In addition, the sustain pulse is alternately applied to the scan and sustain electrodes Y1 to Yn and Xeven and Xodd so that the sustain discharge is generated only in the cells selected during the second sustain period S2. At this time, the cells that have undergone a sustain discharge during the first sustain period S1 may not generate a discharge during the main reset period MR and the second write address period WA2, and accordingly the light-emitting cell state is maintained. Thus, even the cells that have completed a sustain discharge in the first sustain period S1 may generate a sustain discharge when the sustain pulse is applied during the second sustain period S2. That is, the predetermined cells that are selected as the light-emitting cells in the second write address period WA2 as well as in the first write address period WA1 undergo a sustain discharge during the second sustain period S2. Therefore, the Xodd line cells undergo a greater number of sustain discharges than the Xeven line cells because the Xodd line cells undergo a sustain discharge during the first and second sustain periods. The number difference of the sustain discharges generated between the Xodd and Xeven line cells during the fourth subfield SF4 is supplemented as described below, and accordingly, it is controlled such that the same number of sustain discharges are generated.
The negative (−) wall charge and the positive (+) wall charges respectively form on the scan and sustain electrodes of the cells that have completed a sustain discharge during the first sustain period S1 because the last sustain pulse is applied to the scan electrodes Y1 to Yn during the first sustain period S1 of the fourth subfield. Accordingly, a wall voltage Vwxy is formed between the sustain and scan electrodes such that a potential of the scan electrodes becomes higher than the same of the sustain electrodes.
The state of the wall charges is maintained even at the finishing point of the main reset period MR because the reset discharge is not generated during the main reset period MR.
As shown in
First, during the first erase address period EA1 of the fifth subfield SF5, a ground voltage 0V and a voltage Ve′ are respectively applied to the even-numbered and odd-numbered sustain electrodes Xeven and Xodd. At this time, in the FIG.2 embodiment, the scan pulse having the voltage Vscl is sequentially applied to the scan electrodes Y1 to Yn and the voltage Vsch is applied to the scan electrodes that are not applied with the voltage Vscl. Furthermore, in the
That is, the erase address operation can be performed depending on the application of the voltage Ve′. Therefore, the light-emitting cell state is changed into the non-light-emitting cell state only in the cells selected among the Xeven line cells during the first erase address period EA1 so that the erase address operation is performed in the selected cells.
Meanwhile, the voltage Ve′ applied during the first erase address period. EA1 is set to be less than the voltage Ve as described above. This is because the last sustain pulse is applied to the scan electrodes Y1 to Yn, and accordingly, the negative (−) and positive (+) wall charges are respectively formed on the scan and sustain electrodes of the cells that have undergone a sustain discharge so that the erase address operation can be operated even by the voltage Ve′ that is less than the voltage Ve in the cells that have undergone a sustain discharge during the sustain period of the fourth subfield SF4. However, since there are somewhat lesser wall charges after the reset period, the voltage Ve applied during the write address period of the first to the fourth subfields SF1 to SF4 is set to be somewhat higher. Meanwhile, in
In the first sustain period S1 of the fifth subfield SF5, the sustain pulse is alternately applied to the scan and sustain electrodes Y1 to Yn and Xodd and Xeven so that the sustain discharge is generated on the cell maintaining the light-emitting cell state. At this time, the number of the sustain pulses is appropriately selected corresponding to the weight values of the fifth subfield SF5.
Meanwhile, the sustain pulse applied in the first sustain period S1 serves to supplement the wall charges for the Xeven line cells, which are partly erased during the first erase address period EA1. As described above, the weak discharge is generated between the scan and address electrodes of the Xeven line cell even though the reference voltage 0V is applied to the even-numbered sustain electrodes Xeven when the scan and address voltages Vscl′ and Va′ are respectively applied to the scan and address electrodes during the first erase address period EA1. As a result, the wall charges formed on the address electrodes of the cells maintaining the light-emitting cell state among the Xeven line cells are erased, and accordingly, the erase addressing is not sufficiently performed during the second erase address period EA2. However, the erased wall charge is supplemented during the second sustain period S2. Although the wall charges are partly erased from the light-emitting cells among the Xeven line cells because the Xeven line cells are not selected during the first erase address period EA1, the sustain discharge is generated during the first sustain period S when the sustain pulse is applied, and accordingly the erased wall charges are supplemented by the sustain discharges.
Subsequently, the voltage Ve′ and the reference voltage 0V are respectively applied to the even-numbered and odd-numbered sustain electrodes Xeven and Xodd during the second erase address period EA2. In addition, in the first exemplary embodiment of
In addition, the sustain pulse is applied to the scan electrodes Y1 to Yn and the sustain electrodes Xodd and Xeven during the second sustain period S2. The sustain discharge is then generated in the cells maintaining the light-emitting cell state. At this time, the number of sustain pulses applied during the second sustain period S2 is set to be equal to the number of sustain pulses applied during the first sustain period S1 such that the sustain discharge number of Xodd line cells is in accord with that of the Xeven line cell. Meanwhile, the wall charges, which are partly erased or dissipated in the cell maintaining the light-emitting cell state among the Xodd line cells in the same manner as the first sustain period S1, are supplemented by the sustain discharge of the second sustain period S2 even during the second erase address period EA2. Therethrough, the Xodd line cells regularly performs an erase addressing operation during the first erase address period EA1 of the sixth subfield SF1 corresponding to the next subfield of the fifth subfield SF5.
In addition, the driving waveforms applied to the sixth to ninth subfields SF6 to SF9 are substantially the same as the driving waveform of the fifth subfield SF5 shown in
Meanwhile, there is a problem in the main reset operation because the wall charge states after the write address operation are different from that after the fifth subfield, that is, the wall charges are erased by the erase address operation. The reset operation may not be normally performed in the cells in which the wall charges are erased by the erase address operation because the main reset is designed to expect the write address operation.
Therefore, at the odd-numbered frame, a driving waveform shown in
As shown in
Generally, the wall charge state of the cells that have undergone a sustain discharge is given as
At this time, the erase discharge is generated between the scan and address electrodes Y1 to Yn and A1 to An, and accordingly the wall charges are erased during the erase address period, when the cells are selected as the non-light-emitting cell state and the erase address operation is performed in the cells during the erase address period of the fifth to tenth subfields SF5 to SF10. That is, when the erase addressing operation is performed, the negative voltage Vscl′ is applied to the scan electrodes Y1 to Yn and the positive voltage Va′ is applied to the address electrodes A1 to An so that the negative (−) wall charges formed on the scan electrodes Y1 to Yn are largely erased, and a predetermined amount of the negative (−) wall charges are formed on the address electrodes A1 to An, as shown in
However, when the main reset period MR is performed at the first subfield SF1 of the even-numbered frame while forming the negative (−) wall charges on the address electrodes A1 to An as shown in
Therefore, as shown in
At this time, the voltage Vb is set such that the voltage difference between the sustain electrodes Xeven and Xodd and the scan electrodes Y1 to Yn is less than the discharge firing voltage and greater than the voltage Vs. That is, the sustain discharge is generated in the cells in which the wall charges have been erased by the erase address operation, as well as the cells that have undergone a sustain discharge at the tenth subfield SF10. The cells that have undergone an erase address operation have the wall charge state as shown in
Therefore, the erase addressed cells are initialized from the wall charge state as shown in
Meanwhile, when the amend period M is added, it may be difficult to express the entirety of grayscales. More specially, in the case of the cells that have experienced a sustain discharge between the fourth subfield SF4 and the tenth subfield SF10, the discharges are generated whenever the voltage is applied to the scan electrodes Y1 to Yn and the sustain electrodes Xeven and Xodd during the amend period M, and accordingly, a higher grayscale than the desired grayscale is expressed. However, since the number of sustain discharges generated during the amend period M can be controlled, and because the discharge generated during the amend period M is weak in comparison with the entire grayscale value in that the cell undergoes light-emitting at the subfield having a larger weight value, it has no large effect on the expression of the entire grayscales. Particularly, experimentally, the wall charge state that is appropriate for performing a main reset operation of the even-numbered frame is given when the voltages Vs and 0V are alternately applied about 3 times after the voltages Vs and Vb are respectively applied to the sustain electrodes Xeven and Xodd and the scan electrodes Y1 to Yn during the amend period M. There is no significant effect on the expression of the entire grayscale when the sustain discharge is generated a further 3 times.
In addition, in the case of the cells (i.e., Xodd line cells) in which the sustain discharge is generated between the first subfield SF1 and the third subfield SF3, and the sustain discharge is not generated after the fourth subfield SF4, the discharge may not be generated even during the amend period M. Accordingly, there is no large effect on the expression of the entire grayscale.
For example, in the case of the cell in which the sustain discharge is generated at the third subfield SF3 and the sustain discharge is not generated after the fourth subfield SF4, only the cells that have undergone a sustain discharge at the third subfield are initialized during the selective reset period SR of the fourth subfield SF4 the third subfield SF3. Accordingly, the wall charge state having the wholly erased wall charge as shown in
Meanwhile, according to an exemplary embodiment of the present invention, the amend period M is performed after the second sustain period S2 at the tenth subfield SF10. However, the amend period M may replace the second sustain period S2. That is, when the same number of discharge pulses is applied during the second sustain period S2 and during the amend period M, the time allocated in the tenth subfield SF10 may be reduced.
In addition, according to an exemplary embodiment of the present invention, the voltage difference between the scan and sustain electrodes Y1 to Yn and Xeven and Xodd increases when the voltage Vb applied to the scan electrodes Y1 to Yn decreases during the amend period M. However, the voltage difference between the scan and sustain electrodes Y1 to Yn and Xeven and Xodd may also increase when the ground voltage is applied to the scan electrodes Y1 to Yn and the voltage applied to the sustain electrodes Xeven and Xodd is greater than the voltage Vs.
As described above, according to an exemplary embodiment of the present invention, the number of scan circuits can be reduced when the number of electrodes are reduced such that the sustain and scan electrodes respectively share two adjacent display lines.
In addition, the wall charges are sufficiently initialized during the next main reset period by replacing the amend period for the predetermined period when the write address and erase address periods are mixed at the plurality of subfields.
While the above description has pointed out novel features of the invention as applied to various embodiments, the skilled person will understand that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made without departing from the scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description. All variations coming within the meaning and range of equivalency of the claims are embraced within their scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2005-0095997 | Oct 2005 | KR | national |
