Patent Application
20100103161
The present invention relates to a plasma display device that selectively causes a plurality of discharge cells to discharge to display an image and a method of driving the same.
(Configuration of Plasma Display Panel)
An AC surface discharge type panel that is typical as a plasma display panel (hereinafter abbreviated as a “panel”) includes a number of discharge cells between a front plate and a back plate arranged so as to face each other.
The front plate is constituted by a front glass substrate, a plurality of display electrodes, a dielectric layer and a protective layer. Each display electrode is composed of a pair of scan electrode and sustain electrode. The plurality of display electrodes are formed in parallel with one another on the front glass substrate, and the dielectric layer and the protective layer are formed so as to cover the display electrodes.
The back plate is constituted by a back glass substrate, a plurality of data electrodes, a dielectric layer, a plurality of barrier ribs and phosphor layers. The plurality of data electrodes are formed in parallel with one another on the back glass substrate, and the dielectric layer is formed so as to cover the data electrodes. The plurality of barrier ribs are formed in parallel with the data electrodes, respectively, on the dielectric layer, and the phosphor layers of R (red), G (green) and B (blue) are formed on a surface of the dielectric layer and side surfaces of the barrier ribs.
The front plate and the back plate are arranged to face each other such that the display electrodes intersect with the data electrodes in three dimensions, and then sealed. An inside discharge space is filled with a discharge gas. The discharge cells are formed at respective portions at which the display electrodes and the data electrodes face one another.
In the panel having such a configuration, a gas discharge generates ultraviolet rays, which cause phosphors of R, G and B to be excited and to emit light in each of the discharge cells. Accordingly, color display is performed.
A sub-field method is employed as a method of driving the panel. In the sub-field method, one field period is divided into a plurality of sub-fields, and the discharge cells are caused to emit light or not in the respective sub-fields, so that a gray scale display is performed. Each of the sub-fields has a setup period, a write period and a sustain period.
(Method 1 of Driving Conventional Panel)
In the setup period, a weak discharge (setup discharge) is performed, and wall charges required for a subsequent write operation is formed in each discharge cell. In addition, the setup period has a function of generating priming for reducing a discharge time lag to stably generate a write discharge. Here, the priming means an excited particle that serves as an initiating agent for the discharge.
In the write period, scan pulses are applied to the scan electrodes in sequence while write pulses corresponding to image signals to be displayed are applied to the data electrodes. This selectively generates the write discharges between the scan electrodes and the data electrodes, causing the wall charges to be selectively formed.
In the subsequent sustain period, the sustain pulses are applied between the scan electrodes and the sustain electrodes a predetermined number of times corresponding to luminances to be displayed. Accordingly, discharges are selectively induced in the discharge cells in which the wall charges have been formed by the write discharges, causing the discharge cells to emit light.
Here, respective voltages applied to the scan electrodes, the sustain electrodes and the data electrodes are adjusted in order to generate the weak discharges in the discharge cells in the foregoing setup period.
Specifically, a ramp voltage gradually rising is applied to the scan electrodes while the voltage of the data electrodes is held at a ground potential (a reference voltage) in the first half of the setup period (hereinafter referred to as a rise period). This generates the weak discharges between the scan electrodes and the data electrodes and between the sustain electrodes and the data electrodes in the rise period.
Moreover, a ramp voltage gradually dropping is applied to the scan electrodes while the voltage of the data electrodes is held at the ground potential in the second half of the setup period (hereinafter referred to as a drop period). This generates the weak discharges between the scan electrodes and the data electrodes and between the sustain electrodes and the data electrodes in the drop period.
As described above, Patent Document 1, for example, discloses the method of driving the panel in which the ramp voltage or a voltage gradually rising or dropping is applied to the scan electrodes during the setup period. Thus, the wall charges stored in the scan electrodes and sustain electrodes are erased, and the wall charges required for the write operation are stored in each of the scan electrodes, the sustain electrodes and the data electrodes.
In practice, however, strong discharges may be generated between the scan electrodes and the data electrodes in the rise period. In this case, the strong discharges are generated between the scan electrodes and the sustain electrodes to generate a large amount of wall charges and a large amount of priming in the discharge cells, resulting in a higher possibility of the strong discharges to be generated also in the drop period.
The generation of the strong discharges in the setup period erases the wall charges stored in the scan electrodes, the sustain electrodes and the data electrodes. Thus, an appropriate amount of wall discharges required for the write discharges cannot be formed in each electrode.
Therefore, Patent Document 2 discloses a method of driving the panel that prevents the generation of the strong discharges in the setup period.
(Method 2 of Driving Conventional Panel)
As shown in
In this case, a voltage between the scan electrodes and the data electrodes is smaller than that when the data electrodes are held at the ground potential. Accordingly, a voltage between the scan electrodes and the sustain electrodes exceeds a discharge start voltage before the voltage between the scan electrodes and the data electrodes exceeds the discharge start voltage.
As described above, the weak discharges are induced between the scan electrodes and the sustain electrodes at an earlier timing, thereby generating the priming in the rise period. After that, the weak discharges are induced between the scan electrodes and the data electrodes, so that the wall charges required for the write operation are formed in each of the scan electrodes, the sustain electrodes and the data electrodes.
For example, the negative wall charges are stored in the scan electrodes and the positive wall charges are stored in the data electrodes when the write period shown in
[Patent Document 1] JP 2003-15599 A
[Patent Document 2] JP 2006-18298 A
In recent years, the number of discharge cells has been increased (an increase of pixels) while distances between adjacent discharge cells have been reduced with a larger screen and higher precision of a panel. As a result, crosstalk is liable to occur between the adjacent discharge cells, as will be described below.
As shown in
Next, a ramp voltage gradually rising is applied to the scan electrodes while the data electrodes are held at the voltage Vd in the rise period of the setup period. Thus, the weak discharges are generated between the scan electrodes and the sustain electrodes, and the weak discharges are subsequently generated between the scan electrodes and the data electrodes. As a result, the negative wall charges are stored in the scan electrodes, and the positive wall charges are stored in the sustain electrodes. At this time, the positive wall charges are stored in the data electrodes.
In the drop period of the setup period, a ramp voltage gradually dropping is applied to the scan electrodes while the data electrodes are held at the ground potential. This generates the weak discharges between the scan electrodes and the data electrodes and between the sustain electrodes and the data electrodes. This results in the reduced negative wall charges stored in the scan electrodes and the reduced positive wall charges stored in the sustain electrodes. At this time, the positive wall charges are stored in the data electrodes.
In this manner, the negative wall charges are stored in the scan electrodes and the positive wall charges are stored in the data electrodes when the write period is started. In this state, negative-polarity write pulses are applied to the scan electrodes and positive-polarity write pulses are applied to the data electrodes in the write period. In this case, the foregoing wall charges cause the voltage between the scan electrodes and the data electrodes to be high, thus stably generating the write discharges between the scan electrodes and the data electrodes.
At this time, since the positive wall charges are stored in the sustain electrodes, a large volume of write discharges are generated between the scan electrodes and the sustain electrodes. Accordingly, when the distances between the adjacent discharge cells are small, crosstalk is liable to occur between the adjacent discharge cells to cause erroneous discharges. Therefore, a method of driving the panel described below has been put into practical use in order to prevent generation of such crosstalk.
(Method 3 of Driving Conventional Panel)
In the driving waveforms of
According to the experiments conducted by the inventor, however, it was found that the following phenomenon would occur in practice. As shown in
As described above, a large amount of positive wall charges is stored in the scan electrodes and a large amount of negative wall is stored in the sustain electrodes before the setup period. Therefore, when the voltage Vm is applied to the scan electrodes, the strong discharges are generated between the sustain electrodes and the data electrodes, thus generating the strong discharges between the scan electrodes and the sustain electrodes accordingly.
Such strong discharges are generated to erase the wall charges stored in the scan electrodes, the sustain electrodes and the data electrodes. Thus, the voltage between the scan electrodes and the sustain electrodes does not exceed the discharge start voltage even though the ramp voltage rising by the voltage Vset is applied to the scan electrodes, so that the weak discharges cannot be generated between the scan electrodes and the sustain electrodes.
Accordingly, it is difficult to adjust the wall charges in the scan electrodes, the sustain electrodes and the data electrodes to amounts necessary for the write discharges in the write period.
Therefore, it is considered that the ramp voltage applied to the scan electrodes is increased in order to generate the weak discharges after generation of the foregoing strong discharges. However, this increases a driving circuit in cost.
An object of the present invention is to provide a plasma display device capable of preventing the crosstalk generated between the adjacent discharge cells and forming desired amounts of wall charges in the plurality of electrodes constituting the discharge cells and a method of driving the same.
(1) According to an aspect of the present invention, a plasma display device that drives a plasma display panel including a plurality of discharge cells at intersections of a scan electrode and a sustain electrode with a plurality of data electrodes by a sub-field method in which one field period includes a plurality of sub-fields includes a scan electrode driving circuit that drives the scan electrode, a sustain electrode driving circuit that drives the sustain electrode, and a data electrode driving circuit that drives the data electrodes, wherein at least one sub-field of the plurality of sub-fields includes a setup period in which wall charges of the plurality of discharge cells are adjusted such that write discharges can be performed, the scan electrode driving circuit applies a ramp voltage that changes from a first potential to a second potential to the scan electrode for setup discharges in the setup period, the sustain electrode driving circuit applies a voltage that changes from a third potential to a fourth potential to the sustain electrode before a time point when a potential of the scan electrode starts changing to the first potential so that a potential difference between the scan electrode and the sustain electrode is increased, and the data electrode driving circuit applies to each of the data electrodes a voltage that changes from a fifth potential to a sixth potential before the time point when the potential of the scan electrode starts changing to the first potential so that a potential difference between the scan electrode and each of the data electrodes is reduced in synchronization with change in a voltage of the sustain electrode.
In this plasma display device, the at least one sub-field of the plurality of sub-fields includes the setup period in which the wall charges of the plurality of discharge cells are adjusted so that the write discharges can be performed. In this setup period, the ramp voltage changing from the first potential to the second potential is applied to the scan electrode by the scan electrode driving circuit.
Meanwhile, the voltage changing from the third potential to the fourth potential is applied to the sustain electrode by the sustain electrode driving circuit so that the potential difference between the scan electrode and the sustain electrode is increased before the time point when the potential of the scan electrode starts changing to the first potential in the setup period. In addition, the voltage changing from the fifth potential to the sixth potential is applied to the data electrodes by the data electrode driving circuit before the time point when the potential of the scan electrode starts changing to the first potential in the setup period so that the potential difference between the scan electrode and each of the data electrodes is reduced in synchronization with the change in the voltage applied to the sustain electrode.
As described above, a potential difference between the sustain electrode and each of the data electrodes is increased before the time point when the potential of the scan electrode starts changing to the first potential, generating the discharge between the sustain electrode and each of the data electrodes. As a result, the wall charges on the sustain electrode and each of the data electrodes are erased or reduced.
In addition, when weak erase discharges are performed at an end of a preceding sustain period for prevention of crosstalk, a large amount of wall charges is stored on the sustain electrode before start of the setup period. Since the wall charges are erased or reduced by the discharges between the sustain electrode and each of the data electrodes even in such a case, generation of strong discharges between the scan electrode and the sustain electrode is prevented at the time point when the potential of the scan electrode starts changing to the first potential. In this case, the wall charges remain on the scan electrode and the sustain electrode.
After that, the voltage between the scan electrode and the sustain electrode can be reliably made higher than a discharge start voltage during a period in which the ramp voltage applied to the scan electrode changes from the first potential to the second potential as described above. This generates a weak setup discharge between the scan electrode and the sustain electrode. As a result, the wall charges of the plurality of discharge cells can be reliably adjusted to an amount necessary for the write discharges.
Since the voltage of each of the data electrodes attains the fifth potential so that the potential difference between the scan electrode and each of the data electrodes is reduced, generation of strong discharges between the scan electrode and each of the data electrodes and generation of the strong discharges between the scan electrode and the sustain electrode are prevented.
As a result, the wall charges on the scan electrode, the sustain electrode and each of the data electrodes are not erased by the strong discharges, and the wall charges of the plurality of discharge cells can be adjusted to a value suitable for the write discharges.
(2) The data electrode driving circuit may cause a voltage of each of the data electrodes to change from the sixth potential to the fifth potential before the time point when the potential of the scan electrode starts changing to the first potential, and subsequently cause the voltage of each of the data electrodes to return to the sixth potential after the time point when the potential of the scan electrode starts changing to the first potential.
In this case, generation of a ripple in the voltage of each of the data electrodes at the time of the change of the ramp voltage is prevented. Thus, a component with low breakdown voltage can be used in the data electrode driving circuit.
(3) The data electrode driving circuit may maintain a voltage of each of the data electrodes at the sixth potential during application of the ramp voltage. In this case, the voltage applied to each of the data electrodes is easily controlled.
(4) The second potential may be a positive potential that is higher than the first potential, the third potential may be a positive potential that is higher than the fourth potential, and the sixth potential may be a positive potential that is higher than the fifth potential.
In this case, the ramp voltage applied to the scan electrode rises from the first potential to the second potential. In addition, the voltage applied to the sustain electrode drops from the third potential to the fourth potential before the time point when the potential of the scan electrode starts changing to the first potential. Furthermore, the voltage applied to each of the data electrodes rises from the fifth potential to the sixth potential before the time point when the potential of the scan electrode starts changing to the first potential. In this manner, the positive voltages are applied to the scan electrode, the sustain electrode and each data electrode, thus preventing a complicated configuration of a power supply circuit.
(5) The fourth potential and the sixth potential may be set so that a first discharge is generated between the sustain electrode and each of the data electrodes, the ramp voltage may be set so that a second discharge is generated, after the first discharge, between the scan electrode and the sustain electrode during change in the ramp voltage from the first potential to the second potential, and a discharge current in the second discharge may be smaller than a discharge current in the first discharge.
In this case, since the discharge current in the second discharges is smaller than the discharge current in the first discharges, the wall charges stored on the scan electrode and the wall charges stored on the sustain electrode are adjusted to appropriate amounts without being erased.
(6) The scan electrode driving circuit may apply a pulse voltage having a seventh potential to the scan electrode at an end of a sustain period preceding the setup period, and the sustain electrode driving circuit may apply a voltage that changes from the fourth potential to the third potential to the sustain electrode during an application period of the pulse voltage in order to reduce wall charges of a discharge cell in which a sustain discharge has been performed.
In this case, the weak erase discharges can cause the large amount of wall charges to remain on the scan electrode and sustain electrode at the end of the sustain period preceding the setup period. Accordingly, the write discharges are weakened in the write period following the setup period, resulting in prevention of crosstalk to be generated between adjacent discharge cells.
(7) The scan electrode driving circuit may apply a ramp pulse voltage having a seventh potential to the scan electrode at an end of a sustain period preceding the setup period in order to reduce wall charges of a discharge cell in which a sustain discharge has been performed, a leading edge of the ramp pulse voltage may change more gradually than a trailing edge, and the sustain electrode driving circuit may cause the sustain electrode to be held at the third potential during a period of application of the ramp pulse voltage.
In this case, since the leading edge of the ramp pulse voltage gradually changes, the weak erase discharges can cause the large amount of wall charges to remain on the scan electrode and the sustain electrode at the end of the sustain period preceding the setup period. Accordingly, the write discharges are weakened in the write period after the setup period, resulting in prevention of the crosstalk generated between the adjacent discharge cells.
(8) According to another aspect of the present invention, a method of driving a plasma display device that drives a plasma display panel including a plurality of discharge cells at intersections of a scan electrode and a sustain electrode with a plurality of data electrodes by a sub-field method in which one field period includes a plurality of sub-fields includes the steps of driving the scan electrode, driving the sustain electrode, and driving the data electrodes, wherein at least one sub-field of the plurality of sub-fields includes a setup period in which wall charges of the plurality of discharge cells are adjusted such that write discharges can be performed, the step of driving the scan electrode includes applying a ramp voltage that changes from a first potential to a second potential to the scan electrode for setup discharges in the setup period, the step of driving the sustain electrode includes applying a voltage that changes from a third potential to a fourth potential to the sustain electrode so that a potential difference between the scan electrode and the sustain electrode is increased before a time point when a potential of the scan electrode starts changing to the first potential, and the step of driving the data electrodes includes applying a voltage that changes from a fifth potential to a sixth potential to each of the data electrodes so that a potential difference between the scan electrode and each of the data electrodes is reduced in synchronization with change in a voltage of the sustain electrode before the time point when the potential of the scan electrode starts changing to the first potential.
In this method of driving the plasma display device, the at least one sub-field of the plurality of sub-fields includes the setup period in which the wall charges of the plurality of discharge cells are adjusted so that the write discharges can be performed. In this setup period, the ramp voltage changing from the first potential to the second potential is applied to the scan electrode.
Meanwhile, the voltage changing from the third potential to the fourth potential is applied to the sustain electrode so that the potential difference between the scan electrode and the sustain electrode is increased before the time point when the potential of the scan electrode starts changing to the first potential in the setup period. In addition, the voltage changing from the fifth potential to the sixth potential is applied to the data electrodes before the time point when the potential of the scan electrode starts changing to the first potential in the setup period so that the potential difference between the scan electrode and each of the data electrodes is reduced in synchronization with the change in the voltage applied to the sustain electrode.
As described above, a potential difference between the sustain electrode and each of the data electrodes is increased before the time point when the potential of the scan electrode starts changing to the first potential, generating the discharge between the sustain electrode and each of the data electrodes. As a result, the wall charges on the sustain electrode and each of the data electrodes are erased or reduced.
In addition, when weak erase discharges are performed at an end of a preceding sustain period for prevention of crosstalk, a large amount of wall charges is stored on the sustain electrode before start of the setup period. Since the wall charges are erased or reduced by the discharges between the sustain electrode and each of the data electrodes even in such a case, generation of strong discharges between the scan electrode and the sustain electrode is prevented at the time point when the potential of the scan electrode starts changing to the first potential. In this case, the wall charges remain on the scan electrode and the sustain electrode.
After that, the voltage between the scan electrode and the sustain electrode can be reliably made higher than a discharge start voltage during a period in which the ramp voltage applied to the scan electrode changes from the first potential to the second potential as described above. This generates a weak setup discharges between the scan electrode and the sustain electrode. As a result, the wall charges of the plurality of discharge cells can be reliably adjusted to an amount necessary for the write discharges.
Since the voltage of each of the data electrodes attains the fifth potential so that the potential difference between the scan electrode and each of the data electrodes is reduced, generation of strong discharges between the scan electrode and each of the data electrodes and generation of the strong discharges between the scan electrode and the sustain electrode are prevented.
As a result, the wall charges on the scan electrode, the sustain electrode and each of the data electrodes are not erased by the strong discharges, and the wall charges of the plurality of discharge cells can be adjusted to a value suitable for the write discharges.
According to the present invention, crosstalk generated between adjacent discharge cells is prevented, and a desired amount of wall charges can be formed in a plurality of electrodes constituting discharge cells.
The embodiments of the present invention will be described in detail referring to the drawings. The embodiments below describe a plasma display device and a method of driving the same.
The plasma display panel (hereinafter abbreviated as the panel) 10 includes a front substrate 21 and a back substrate 31 that are made of glasses and arranged so as to face each other. A discharge space is formed between the front substrate 21 and the back substrate 31. A plurality of pairs of scan electrodes 22 and sustain electrodes 23 are formed in parallel with one another on the front substrate 21. Each pair of scan electrode 22 and sustain electrode 23 constitutes a display electrode.
A dielectric layer 24 is formed so as to cover the scan electrodes 22 and the sustain electrodes 23, and a protective layer 25 is formed on the dielectric layer 24.
A plurality of data electrodes 32 covered with an insulator layer 33 are provided on the back substrate 31, and barrier ribs 34 are provided in a shape of a number sign on the insulator layer 33. Phosphor layers 35 are provided on a surface of the insulator layer 33 and side surfaces of the barrier ribs 34. Then, the front substrate 21 and the back substrate 31 are arranged to face each other such that the plurality of pairs of scan electrodes 22 and sustain electrodes 23 vertically intersect with the plurality of data electrodes 32, and the discharge space is formed between the front substrate 21 and the back substrate 31. The discharge space is filled with a mixed gas of neon and xenon, for example, as a discharge gas. Note that the configuration of the panel is not limited to the configuration described in the foregoing. A configuration including the barrier ribs in a striped shape may be employed, for example.
This plasma display device includes the panel 10, an image signal processing circuit 51, a data electrode driving circuit 52, a scan electrode driving circuit 53, a sustain electrode driving circuit 54, a timing generating circuit 55 and a power supply circuit (not shown).
The image signal processing circuit 51 converts an image signal sig into image data corresponding to the number of pixels of the panel 10, divides the image data on each pixel into a plurality of bits corresponding to a plurality of sub-fields, and outputs them to the data electrode driving circuit 52.
The data electrode driving circuit 52 converts the image data for each sub-field into signals corresponding to the data electrodes D1 to Dm, respectively, and drives the data electrodes D1 to Dm based on the respective signals.
The timing generating circuit 55 generates timing signals based on a horizontal synchronizing signal H and a vertical synchronizing signal V, and supplies the timing signals to each of the driving circuit blocks (the image signal processing circuit 51, the data electrode driving circuit 52, the scan electrode driving circuit 53 and the sustain electrode driving circuit 54).
The scan electrode driving circuit 53 supplies driving waveforms to the scan electrodes SC1 to SCn based on the timing signals, and the sustain electrode driving circuit 54 supplies driving waveforms to the sustain electrodes SU1 to SUn based on the timing signals.
A method of driving the panel in the present embodiment will be described.
In the present embodiment, each field is divided into a plurality of sub-fields. In the present embodiment, one field is divided into ten sub-fields (hereinafter abbreviated as a first SF, a second SF, . . . and a tenth SF) on a time base. In addition, a pseudo-sub-field (hereinafter abbreviated as a pseudo-SF) is provided in a period sandwiched between the tenth SF of each field and the next field.
In the following description, a voltage caused by wall charges stored on the dielectric layer, the phosphor layer or the like covering the electrode is referred to as a wall voltage on the electrode.
As shown in
As described above, the phase difference TR is set small, so that the erase discharge between the scan electrode SCi and the sustain electrode SUi is weakened. This causes a large amount of positive wall charges to remain on the scan electrode SCi, and causes a large amount of negative wall charges to remain on the sustain electrode SUi. At this time, positive wall charges are stored on the data electrode Dj.
The sustain electrode SUi is held at the voltage Ve1, the data electrode Dj is held at a ground potential (reference voltage), and a ramp voltage is applied to the scan electrode SCi in the first half of the pseudo-SF. This ramp voltage gradually drops from a positive voltage V15 that is slightly higher than the ground potential toward a negative voltage V14 that is not more than a discharge start voltage.
Thus, weak discharges are generated between the scan electrode SCi and the data electrode Dj and between the scan electrode SCi and the sustain electrode SUi. As a result, the positive wall charges on the scan electrode SCi slightly increases, and the negative wall charges on the sustain electrode SUi slightly increases. The positive wall charges are stored on the data electrode Dj. In this manner, the wall charges in all the discharge cells DC are substantially uniformly adjusted.
In the second half of the pseudo-SF, the scan electrode SCi is held at the ground potential.
In this manner, a great amount of positive wall charges is stored on the scan electrode SCi and a great amount of negative wall charges is stored on the sustain electrode SUi at the end of the pseudo-SF.
Then, the voltage of the sustain electrode SUi is lowered from Ve1 to the ground potential at a time point t1 immediately before the first SF of the next field, as shown in
A great amount of negative wall charges is stored on the sustain electrode SUi and the positive wall charges are stored on the data electrode Dj immediately before the time point t2. When the voltage of the data electrode Dj rises to Vd, the voltage between the sustain electrode SUi and the data electrode Dj attains a value obtained by adding the wall voltage on the data electrode Dj and the wall voltage on the sustain electrode SUi to the voltage Vd. This causes the voltage between the sustain electrode SUi and the data electrode Dj to exceed the discharge start voltage, resulting in generation of a strong discharge between the sustain electrode SUi and the data electrode Dj.
This strong discharge causes the negative wall charges on the sustain electrode SUi to be erased and zero or a small amount of positive wall charges to be stored on the sustain electrode SUi. Moreover, the wall charges on the data electrode Dj is erased and zero or a small amount of negative wall charges is stored on the data electrode Dj. Here, also the positive wall charges on the scan electrode SCi are slightly erased.
After that, the voltage of the scan electrode SCi is raised at a time point t3, and the scan electrode SCi is held at a positive voltage Vi1 at a time point t4. In addition, the voltage of the data electrode Dj is raised to Vd at the time point t4. At this time, since zero or a small amount of positive wall voltage is stored on the sustain electrode SUi, the strong discharge is not generated between the scan electrode SCi and the sustain electrode SUi.
At the time point t4, a ramp voltage is applied to the scan electrode SCi. This ramp voltage gradually rises from the positive voltage Vi1 that is not more than the discharge start voltage toward a positive voltage Vi2 that exceeds the discharge start voltage in a period from a time point t5 to a time point t6. Here, since the data electrode Dj is held at the voltage Vd, generation of the strong discharge between the scan electrode SCi and the data electrode Dj is prevented. The sustain electrode SUi is held at the ground potential.
When the voltage between the scan electrode SCi and the sustain electrode SUi exceeds the discharge start voltage with the rise of the ramp voltage, weak setup discharges are induced between the scan electrode SCi and the sustain electrode SUi in all the discharge cells DC.
Accordingly, the positive wall charges stored on the scan electrode SCi are gradually erased, and the negative wall charges are stored on the scan electrode SCi. Meanwhile, the positive wall charges are stored on the sustain electrode SUi.
The voltage of the scan electrode SCi is lowered at a time point t7, and is held at a voltage V13 at a time point t8. At this time, the positive voltage Ve1 is applied to the sustain electrode SUi.
A negative ramp voltage is applied to the scan electrode SCi at a time point t9. This ramp voltage drops from the positive voltage Vi3 to a negative voltage Vi4 in a period from the time point t9 to a time point t10. In addition, the voltage of the data electrode Dj is lowered and held at the ground potential at the time point t9.
The voltage of the sustain electrode SUi is held at the positive voltage Ve1 in the period from the time point t9 to the time point t10. When the voltage between the scan electrode SCi and the sustain electrode SUi exceeds the discharge start voltage with the drop of the ramp voltage, the weak setup discharges are induced in all the discharge cells DC.
Thus, the negative wall charges stored on the scan electrode SCi are gradually erased in the period from the time point t9 to the time point t10, and a small amount of negative wall charges remains on the scan electrode SCi at the time point t10. Meanwhile, the positive wall charges stored on the sustain electrode SUi are gradually erased in the period from the time point t9 to the time point t10, and the negative wall charges are stored on the sustain electrode SUi at the time point t10. Furthermore, the positive wall charges are stored on the data electrode Dj in the period from the time point t9 to the time point t10.
The voltage of the scan electrode SCi is raised to the ground potential at the time point t10. Thus, the setup period is finished, and the wall voltage on the scan electrode SCi, the wall voltage on the sustain electrode SUi and the wall voltage on the data electrode Dj are adjusted to respective values suitable for a write operation. Specifically, a small amount of negative wall charges is stored on the scan electrode SCi, the negative wall charges are stored on the sustain electrode SUi, and the positive wall charges are stored on the data electrode Dj.
As described above, a setup operation for all the cells in which the setup discharges are generated in all the discharge cells DC is performed in the setup period of the first SF.
Returning to
Then, a voltage at an intersection of the data electrode Dk and the scan electrode SC1 attains a value obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to an externally applied voltage (Vd-Va), exceeding the discharge start voltage. This generates write discharges between the data electrode Dk and the scan electrode SC1 and between the sustain electrode SU1 and the scan electrode SC1.
As described above, the negative wall charges are stored on the scan electrode SCi and the sustain electrode SUi and the positive wall charges are stored on the data electrode Dj when the write period is started in the present embodiment. Therefore, the write discharge between the sustain electrode SU1 and the scan electrode SC1 is weakened.
Accordingly, generation of crosstalk between the adjacent discharge cells DC is prevented even when distances between the adjacent discharge cells are set small in the panel of
The foregoing write discharge causes the positive wall charges to be stored on the scan electrode SC1, the negative wall charges to be stored on the sustain electrode SU1 and the negative wall charges to be stored on the data electrode Dk in the discharge cell DC.
In this manner, the write operation in which the write discharge is generated in the discharge cell DC that should emit light on the first line to cause the wall charges to be stored on each electrode is performed. On the other hand, since a voltage of a discharge cell DC at an intersection of a data electrode Dh (h≠k) to which the write pulse has not been applied and the scan electrode SC1 does not exceed the discharge start voltage, the write discharge is not generated.
The above-described write operation is sequentially performed in the discharge cells DC on the first line to the n-th line, and the write period is then finished.
In a subsequent sustain period, the sustain electrode SUi is returned to the ground potential, and a sustain pulse voltage Vs having the voltage Vs is applied to the scan electrode SCi. At this time, the voltage between the scan electrode SCi and the sustain electrode SUi attains a value obtained by adding the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi to the voltage Vs of the sustain pulse, exceeding the discharge start voltage in the discharge cell DC in which the write discharge has been generated in the write period.
This induces a sustain discharge between the scan electrode SCi and the sustain electrode SUi, causing the discharge cell DC to emit light. As a result, the negative wall charges are stored on the scan electrode SCi, the positive wall charges are stored on the sustain electrode SUi, and the positive wall charges are stored on the data electrode Dk. In the discharge cell DC in which the write discharge has not been generated in the write period, the sustain discharge is not induced and the wall charges are held in a state at the end of the setup period.
Then, the scan electrode SCi is returned to the ground potential, and the sustain pulse having the voltage Vs is applied to the sustain electrode SUi. Since the voltage between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage in the discharge cell DC in which the sustain discharge has been induced, the sustain discharge is again induced between the sustain electrode SUi and the scan electrode SCi, causing the negative wall charges to be stored on the sustain electrode SUi and the positive wall charges to be stored on the scan electrode SCi.
Similarly to this, a predetermined number of sustain pulses are alternately applied to the scan electrode SCi and the sustain electrode SUi, so that the sustain discharges are continuously performed in the discharge cell DC in which the write discharge has been generated in the write period.
Before the sustain period is finished, the voltage applied to the sustain electrode SUi is raised to Ve1 after the predetermined period of time (the phase difference TR) since the voltage applied to the scan electrode SCi has been raised to Vs. This induces a weak erase discharge between the scan electrode SCi and the sustain electrode SUi, similarly to the case at the end of the tenth SF described referring to
In a setup period of the second SF, the voltage of the sustain electrode SUi is held at Ve1, the data electrode Dj is held at the ground potential, and a ramp voltage gradually dropping from the positive voltage Vi5 toward the negative voltage Vi4 is applied to the scan electrode SCi, similarly to the pseudo-SF described referring to
This weakens the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi, and the wall voltage on the data electrode Dk is adjusted to a value suitable for the write operation.
Meanwhile, the discharge is not generated and the wall charges are kept constant in the state at the end of the setup period of the preceding sub-field in the discharge cell DC in which the write discharge and the sustain discharge have not been induced in the preceding sub-field.
As described above, a selective setup operation in which the setup discharges are selectively generated in the discharge cells DC in which the sustain discharges have been induced in the immediately preceding sub-field is performed in the setup period of the second SF.
In a write period of the second SF, the write operation is sequentially performed in the discharge cells on the first line to the n-th line similarly to the write period of the first SF, and the write period is then finished. Since an operation in the subsequent sustain period is the same as the operation in the sustain period of the first SF except for the number of the sustain pulses, explanation is omitted.
In setup periods of the subsequent third to tenth SFs, the selective setup operations are performed similarly to the setup period of the second SF. In write periods of the third to tenth SFs, the voltage Ve2 is applied to the sustain electrode SUi similarly to the second SF to perform the write operations. In sustain periods of the third to tenth SFs, the same sustain operations as that in the sustain period of the first SF except for the number of the sustain pulses are performed.
The wall charges on the scan electrode SCi and the sustain electrode SUi may be adjusted before the start of the pseudo-SF by applying driving waveforms described below to the respective electrodes.
In this example, the ramp voltage is applied to the scan electrode SCi at the end of the tenth SF of the preceding field while the sustain electrode SUi and the data electrode Dj are held at the ground potential in order to perform the weak erase discharge before the selective setup as shown in
Here, the positive wall charges are stored on the scan electrode SCi and the negative wall charges are stored on the sustain electrode SUi in the discharge cell DC in which the sustain discharge has been induced. Thus, as described above, when the ramp voltage is applied to the scan electrode SCi, the voltage between the scan electrode SCi and the sustain electrode SUi exceeds the discharge start voltage in the discharge cell DC in which the sustain discharge has been induced, thus again generating the weak erase discharge between the sustain electrode SUi and the scan electrode SCi.
As a result, the positive wall charges stored on the scan electrode SCi and the negative wall charges stored on the sustain electrode SUi are slightly reduced, a large amount of positive wall charges remains on the scan electrode SCi, and a large amount of negative wall charges remains on the sustain electrode SUi. At this time, the positive wall charges are stored on the data electrode Dj.
Thus, similarly to the example of
In the example of
The driving waveforms shown in
That is, the first SF does not have the setup period, and the other sub-fields have the respective setup periods. The setup operation for all the cells is performed in the setup period of the second SF after an erase operation has been performed in the first SF.
In the write period of the first SF, the scan pulse having the negative voltage Va is applied to the sustain electrode SUi and the write pulse having the positive voltage Vd is applied to the data electrode Dk, similarly to the write period described referring to
This generates the write discharges between the data electrode Dk and the scan electrode SC1 and between the sustain electrode SU1 and the scan electrode SC1. This write operation is sequentially performed in the discharge cells on the first line to the n-th line, and the write period is then finished.
In the subsequent sustain period, the sustain electrode SUi is returned to the ground potential, and the sustain pulse having the voltage Vs is applied to the scan electrode SCi, similarly to the sustain period described referring to
This induces the sustain discharge between the scan electrode SCi and the sustain electrode SUi in the discharge cell DC in which the write discharge has been generated in the write period, causing the discharge cell DC to emit light. Similarly to this, a predetermined number of sustain pulses are alternately applied to the scan electrode SCi and the sustain electrode SUi, so that the sustain discharges are continuously performed in the discharge cell in which the write discharge has been generated in the write period.
Here, in this first SF, an erase period following the sustain period is provided before the start of the second SF as shown in
In the erase period, the voltage of the sustain electrode SUi is raised to Ve1 after the predetermined period of time (the phase difference TR), which is set small, since the voltage of the scan electrode SCi is raised to Vs, similarly to the end of the sustain period of the tenth SF of the preceding field described referring to
Thus, the weak erase discharge is generated between the scan electrode SCi and the sustain electrode SUi. This allows a large amount of positive wall charges to remain on the scan electrode SCi and a large amount of negative wall charges to remain on the sustain electrode SUi. The first SF is finished in this state.
After that, as shown in
Although the third to tenth SF following the second SF have the setup periods, the write periods and the sustain periods, respectively, the selective setup operations are performed in those setup periods.
As described above, the setup period in which the setup operation for all the cells is performed may be provided between predetermined sub-fields in a field in the plasma display device according to the present embodiment.
The scan electrode driving circuit 53 shown in
The transistor Q13 of the scan electrode driving circuit 53 is connected between the power supply terminal V11 and a node N13, and a control signal S13 is input to a gate. The voltage Vi1 is applied to the power supply terminal V11. The transistor Q14 is connected between the node N13 and a ground terminal, and a control signal S14 is input to a gate.
The recovery capacitor C11 is connected between a node N11 and a ground terminal. The transistor Q11 and the diode DD11 are connected in series between the node N11 and a node N12a. The diode DD12 and the transistor Q12 are connected in series between a node N12b and the node N11. A control signal S11 is input to a gate of the transistor Q11, and a control signal S12 is input to a gate of the transistor Q12. The recovery coil L11 is connected between the node N12a and the node N13. The recovery coil L12 is connected between the node N12b and the node N13.
The capacitor C12 is connected between a node N14 and the node N13. The diode DD13 is connected between a power supply terminal V12 and the node N14. A voltage Vr is applied to the power supply terminal V12.
The transistor Q15 is connected between the node N14 and a node N15, and a control signal S15 is input to a gate. The capacitor C13 is connected between the node N14 and the gate of the transistor Q15. The transistor Q16 is connected between the node N15 and the node N13, and a control signal S16 is input to a gate.
The transistor Q17 is connected between the node N15 and a node N16, and a control signal S17 is input to a gate. The transistor Q18 is connected between the node N16 and a power supply terminal V13, and a control signal S18 is input to a gate. The voltage V14 is applied to the power supply terminal V13. The capacitor C14 is connected between the node N16 and the gate of the transistor Q18.
The capacitor C15 is connected between the node N16 and a node N17. The diode DD14 is connected between a power supply terminal V14 and the node N17. The voltage Vs is applied to the power supply terminal V14.
The transistor Q19 is connected between the node N17 and a node N18, and a control signal S19 is input to a gate. The transistor Q20 is connected between the node N18 and the node N16, and a control signal S20 is input to a gate.
The transistor Q21 is connected between the node N18 and the scan electrode SCi, and a control signal S21 is input to a gate. The transistor Q22 is connected between the node N16 and the scan electrode 12, and a control signal S22 is input to a gate.
The foregoing control signals S11 to S22 are supplied from the timing generating circuit 55 of
At the starting time point t2 of the first SF, the control signals S11, S12, S13, S15, S18, S19, S21 are at a low level. Thus, the transistors Q11, Q12, Q13, Q15, Q18, Q19, Q21 are turned off.
The control signals S14, S16, S17, S20, S22 are at a high level. Thus, the transistors Q14, Q16, Q17, Q20, Q22 are turned on. In this case, the voltage of the scan electrode SCi is at the ground potential.
At the time point t3, the control signal S11 attains a high level and the control signal S14 attains a low level. Thus, the transistor Q11 is turned on and the transistor Q14 is turned off. This causes a current to flow from the recovery capacitor C11 to the scan electrode SCi, causing the voltage of the scan electrode SCi to rise.
In addition, the control signal S11 attains a low level immediately after the time point t3. This causes the transistor Q11 to be turned off. At the same time, the control signal S13 attains a high level. This causes the transistor Q13 to be turned on.
In this case, the current flowing from the recovery capacitor C11 to the scan electrode SCi is shut off, and the current flows from the power supply terminal V11 to the scan electrode SCi. This causes the voltage of the scan electrode SCi to rise and reach Vi1 at the time point t4.
Next, the control signal S15 attains a high level and the control signal S16 attains a low level at the time point t5. This causes the transistor Q15 to be turned on and the transistor Q16 to be turned off.
In this case, the current flows from the power supply terminal V12 to the scan electrode SCi while the current flowing from the power supply terminal V11 to the scan electrode SCi is shut off. At this time, since the voltage at the node N15 is held at Vi1, the voltage of the scan electrode SCi gradually rises to reach Vi2, that is, (Vi1+Vr) at the time point t6.
Then, the control signal S15 attains a low level and the control signal S16 attains a high level at the time point t7. This causes the transistor Q15 to be turned off and the transistor Q16 to be turned on. Thus, the voltage of the scan electrode SCi drops to attain the voltage V11 (the foregoing voltage Vi3) of the power supply terminal V11 at the time point t8.
Next, the control signal S13 attains a low level, the control signal S17 attains a low level, and the control signal S18 attains a high level at the time point t9. This causes the transistor Q13 to be turned off, the transistor Q17 to be turned off, and the transistor Q18 to be turned on. In this case, the voltage of the scan electrode SCi gradually drops to attain the voltage Vi4 of the power supply terminal V13 at the time point t10.
At the time point t10, the control signal S19 attains a high level, causing the transistor Q19 to be turned on. This causes the voltage Vs of the power supply terminal V14 to be applied to the scan electrode SCi, so that the voltage of the scan electrode SCi attains an approximate ground potential.
In the foregoing configuration, a ramp waveform (not shown) changing in a curve may be supplied to the scan electrode SCi by adjusting the capacitance of the capacitor C13, for example.
The sustain electrode driving circuit 54 of
The sustain driver 540 of
The voltage raising circuit 541 includes n-channel FETs (Field-Effect Transistors; hereinafter abbreviated as transistors) Q105a, Q107, Q108, p-channel FETs (Field-Effect Transistors; hereinafter abbreviated as transistors) Q105b, a diode DD25 and a capacitor C102.
The transistor Q101 of the sustain driver 540 is connected between a power supply terminal V101 and a node N101, and a control signal S101 is input to a gate. The voltage Vs is applied to the power supply terminal V1.
The transistor Q102 is connected between the node N101 and a ground terminal, and a control signal S102 is input to a gate. The node N101 is connected to the sustain electrode SUi of
The recovery capacitor C101 is connected between a node N103 and a ground terminal. The transistor Q103 and the diode DD21 are connected in series between the node N103 and a node N102. The diode DD22 and the transistor Q104 tare connected in series between the node N102 and the node N103.
A control signal 5103 is input to a gate of the transistor Q103, and a control signal S104 is input to a gate of the transistor Q104. The recovery coil L101 is connected between the node N101 and the node N102. The diode DD23 is connected between the node N102 and a power supply terminal V101, and the diode DD24 is connected between a ground terminal and the node N102.
The diode DD25 of the voltage raising circuit 541 is connected between a power supply terminal V111 and a node N104, and the voltage Ve1 is applied to the power supply terminal V111.
The transistor Q105a and the transistor Q105b are connected in series between the node N104 and the node N101. A control signal S105a and a control signal S105b are input to gates of the transistor Q105a and the transistor Q105b, respectively. The capacitor C102 is connected between the node N104 and a node N105.
The transistor Q107 is connected between the node N105 and a ground terminal, and a control signal S107 is input to a gate. The transistor Q108 is connected between a power supply terminal V103 and the node N105, and a control signal S108 is input to a gate. A voltage VE2 is applied to the power supply terminal V103. Note that the voltage VE2 satisfies a relation of VE2=Ve2−Ve1, such as VE2=5 [V], for example.
The above-mentioned control signals S101 to S104, S105a, S105b, S107, S108 are supplied from the timing generating circuit 55 of
First, the control signals S101, S102, S103, S104, S105b, S108 attain a low level at a time point t0 in the pseudo-SF of the preceding field. This causes the transistors Q101, Q102, Q103, Q104, Q108 to be turned off, and the transistor Q105b to be turned on. The control signals S105a, S107 attain a high level. This causes the transistors Q105a, Q107 to be turned on.
In this case, a current flows from the power supply terminal V111 to the sustain electrode SUi through the node N104. Thus, the voltage of the sustain electrode SUi is held at Ve1.
Next, the control signal S104 attains a high level, the control signal S105a attains a low level, and the control signal S105b attains a high level at the time point t1 immediately before the end of the pseudo-SF, that is, at the time point t1 immediately before the first SF of the next field.
Accordingly, the transistor Q104 is turned on, and the transistors Q105a, Q105b are turned off. This causes the current to flow from the sustain electrode SUi (the node N101) to the recovery capacitor C101 through the recovery coil L101, the diode DD22 and the transistor Q104. At this time, charges in a panel capacitance are recovered to the recovery capacitor C101. As a result, the voltage of the sustain electrode SUi (the node N101) drops.
In addition, the control signal S104 attains a low level, and the control signal S102 attains a high level immediately after the time point t1. This causes the transistor Q104 to be turned off and the transistor Q102 to be turned on. Accordingly, the node N101 is grounded, and the sustain electrode SUi attains the ground potential.
The control signal S102 is in a high level in a period from the starting time point t2 of the first SF of the next field to the time point t8 when the voltage of the scan electrode SCi starts dropping from the voltage Vi3 to the voltage Vi4. Accordingly, the sustain electrode SUi (the node N101) is held at the ground potential.
Here, the control signal S102 attains a low level, the control signal S105a attains a high level, and the control signal S105b attains a low level at the time point t8. This causes the transistor Q102 to be turned off, and the transistors Q105a, Q105b to be turned on. Thus, the current flows again from the power supply terminal V111 to the sustain electrode SUi through the node N104. Accordingly, the voltage of the sustain electrode SUi is held at Ve1.
The setup period is finished, and then the control signal S107 attains a low level, and the control signal S108 attains a high level at a time point t11 immediately after the start of the write period. This causes the transistor Q107 to be turned off and the transistor Q108 to be turned on. Thus, the current flows from the power supply terminal V103 to the node N105 through the transistor Q108. As a result, the voltage at the node N105 rises to VE2. In this case, the voltage VE2 is added to the voltage Ve1 of the sustain electrode SUi. Accordingly, the voltage of the sustain electrode SUi (the node N101) rises to Ve2.
The data electrode driving circuit 52 of
A power supply terminal V201 is connected to a node N201. The voltage Vd is applied to the power supply terminal V201.
The transistors Q211 to Q21m are connected between the node N201 and nodes ND1 to NDm, respectively. The transistors Q221 to Q22m are connected between the nodes ND1 to NDm and ground terminals, respectively. The nodes ND1 to NDm are connected to the data electrodes Dj of
Control signals S201 to S20m are input to gates of the plurality of transistors Q211 to Q21m, respectively. Also, the control signals S201 to S20m are input to gates of the transistors Q221 to Q22m, respectively.
The foregoing control signals S201 to S20m are supplied from the timing generating circuit 55 of
As shown in
In this case, the nodes ND1 to NDm are connected to the ground terminals through the transistors Q221 to Q22m. Accordingly, the data electrodes Dj attain the ground potential.
Next, the control signals S201 to S20m attain a low level at the starting time point t2 of the first SF. This causes the transistors Q211 to Q21m to be turned on and the transistors Q221 to 22m to be turned off.
In this case, the nodes ND1 to NDm are connected the node N201 through the transistors Q211 to Q21m. This causes the current to flow from the power supply terminal V201 to the data electrodes Dj through the node N201 and the transistors Q211 to Q21m. Thus, the voltage of the data electrode Dj is held at Vd.
In a period from the time point t2 to the time point t3, the control signals S201 to S20m attain a high level after a predetermined period of time has elapsed since the time point t2. In this case, the data electrodes Dj attain the ground potential as described above.
After that, the control signals S201 to S20m again attains a low level at the time point t4. The control signals S201 to S20m are held at a low level in a period from the time point t4 to the time point t9. This causes the voltage of the data electrodes Dj to be held at Vd.
At the time point t9, the control signals S201 to S20m attain a high level. The control signals S201 to S20m are held at a high level from the time point t9 to the end of the setup period. This causes the data electrodes Dj to be held at the ground potential.
In the present embodiment, the scan electrode driving circuit 53 having the following configuration may be employed.
The scan electrode driving circuit 53 of this example is different from the configuration of the scan electrode driving circuit 53 of
As shown in
Moreover, the transistor Q14 is connected between the node N15 and the ground terminal, and the control signal S14 is input to the gate. The recovery coil L12 is connected between the node N15 and the node N12b.
The control signals S11 to S22 supplied to the scan electrode driving circuit 53 of
According to the example of
The control signal S20 attains a low level at the time point t4. This causes the transistor Q20 to be turned off. In addition, the control signals S15, S21 attain a high level, and the control signals S16, S22 attain a low level at the time point t5. This causes the transistors Q15, Q21 to be turned on and the transistors Q16, Q22 to be turned off.
In this case, the current flows from the power supply terminal V12 to the scan electrode SCi while the current flowing from the power supply terminal V11 to the scan electrode SCi is shut off. At this time, since the voltage at the node N16 is held at Vi1, the voltage of the scan electrode SCi gradually rises to attain Vi2, that is, (Vi1+Vr) at the time point t6.
Next, the control signal S15 attains a low level, and the control signals S16, S19 attain a high level at the time point t7. This causes the transistor Q15 to be turned off and the transistors Q16, Q19 to be turned on. In this case, the current flows from the power supply terminal V14 to the scan electrode SCi while the current flowing from the power supply terminal V12 to the scan electrode SCi is shut off. Accordingly, the voltage of the scan electrode SCi drops. At this time, since the voltage at the node N16 is held at Vi1, the voltage of the scan electrode SCi is held at (Vi1+Vs) at a time point t7a.
Next, the control signals S19, S21 attain a low level, and the control signals S20, S22 attain a high level at a time point t7b. This causes the transistors Q19, Q21 to be turned off and the transistors Q20, Q22 to be turned on. In this case, the current flows from the power supply terminal V11 to the scan electrode SCi while the current flowing from the power supply terminal V14 to the scan electrode SCi is shut off. Thus, the voltage of the scan electrode SCi drops to V11 at the time point t8.
Next, the control signals S13, S17 attain a low level, and the control signal S18 attains a high level at the time point t9. This causes the transistors Q13, Q17 to be turned off and the transistor Q18 to be turned on. In this case, the voltage of the scan electrode SCi gradually drops to attain the voltage V14 of the power supply terminal V13 at the time point t10.
At the time point t10, the control signals S19, S21 attain a high level, and the control signals S20, S22 attain a low level. This causes the transistors Q19, Q21 to be turned on and the transistors Q20, Q22 to be turned off. Thus, the voltage of the scan electrode SCi attains the approximate ground potential.
As shown in
Moreover, the transistor Q21 is connected between the node N17 and the scan electrode SCi, and the control signal S21 is input to the gate. The transistor Q22 is connected between the node N16 and the scan electrode SCi, and the control signal S22 is input to the gate.
The recovery coil L12 is connected between the node N15 and the node N12b. A voltage Vr' instead of the voltage Vr is applied to the power supply terminal V12. Note that the voltage Vr' is obtained by adding a voltage (Vi1−Vs) to the voltage Vr.
As shown in
According to the driving waveforms of
Then, a ramp voltage gradually rising from the voltage Vs by the voltage Vr' is applied to the scan electrode SCi in a period from the time point t5 to the time point t6. Then, the voltage applied to the scan electrode SCi is held at (Vs+Vr') in a period from the time point t6 to the time point t7.
The voltage applied to the scan electrode SCi drops by the voltage Vr' in a period from the time point t7 to the time point t7a to be held at (Vs+Vi1). After that, the voltage applied to the scan electrode SCi drops by the voltage Vs in a period from the time point t7b to the time point t8 to be held at Vi1.
Next, a ramp voltage dropping from the voltage Vi1 to the negative voltage V14 is applied to the scan electrode SCi in a period from the time point t9 to the time point t10. Finally, the voltage of the scan electrode SCi is raised from Vi4 so as to attain the approximate ground potential at the time point t10 to be held. The setup period is finished in this state.
As described above, the following control signals S11 to S18, S21, S22 are applied to the scan electrode driving circuit 53 of
At the starting time point t2 of the first SF, the control signals S11, S12, S13, S15, S18, S19, S21 attain a low level. This causes the transistors Q11, Q12, Q13, Q15, Q18, Q21 to be turned off.
The control signals S14, S16, S17, S22 attain a high level. This causes the transistors Q14, Q16, Q17, Q22 to be turned on. In this case, the scan electrode SCi is held at the ground potential.
At the time point t3, the control signal S21 attains a high level, and the control signals S14, S22 attain a low level. This causes the transistor Q21 to be turned on and the transistors Q14, Q22 to be turned off. Thus, the voltage of the scan electrode SCi rises to Vs.
At the time point t5, the control signal S15 attains a high level and the control signal S16 attains a low level. This causes the transistor Q15 to be turned on and the transistor Q16 to be turned off. Thus, the voltage of the scan electrode SCi gradually rises from Vs by the voltage Vr' to attain (Vs+Vr') at the time point t6. Moreover, the control signal S13 attains a high level at the time point t6. This causes the transistor Q13 to be turned on. The voltage of the scan electrode SCi is held at (Vs+Vr') in a period from the time point t5 to the time point t6.
Next, the control signal S15 attains a low level and the control signal S16 attains a high level at the time point t7. This causes the transistor Q15 to be turned off and the transistor Q16 to be turned on. Accordingly, the voltage of the scan electrode SCi drops by Vr' to attain (Vs+Vi1) at the time point t7a. The voltage of the scan electrode SCi is held at (Vs+Vi1) in a period from the time point t7a to the time point t7b.
The control signal S21 attains a low level and the control signal S22 attains a high level at the time point t7b. This causes the transistor Q21 to be turned off and the transistor Q22 to be turned on. In this case, the voltage of the scan electrode SCi drops by Vs to attain Vi1 at the time point t8. The voltage of the scan electrode SCi is held at Vi1 in a period from the time point t8 to the time point t9.
At the time point t9, the control signals S13, S17 attain a low level, and the control signal S18 attains a high level. This causes the transistors Q13, Q17 to be turned off, and the transistor Q18 to be turned on. In this case, the voltage of the scan electrode SCi gradually drops to attain the voltage Vi4 of the power supply terminal V13 at the time point t10.
At the time point t10, the control signal S21 attains a high level, causing the transistor Q21 to be turned on. The voltage Vs of the power supply terminal V14 is applied to the scan electrode SCi, so that the voltage of the scan electrode SCi attains the approximate ground potential.
In the above-described configuration, a ramp waveform (not shown) changing in a curve may be supplied to the scan electrode SCi by adjusting the capacitance of the capacitor C13, for example.
In the plasma display device according to the present embodiment, the positive voltage Vd is applied to the data electrode Dj before the time point t3 (
Therefore, generation of the strong discharge between the scan electrode SCi and the sustain electrode SUi is prevented during application of the ramp waveform to the scan electrode SCi even when the weak erase discharge induced before the setup for all the cells causes a large amount of negative wall charges to remain on the sustain electrode SUi.
Since an appropriate amount of wall charges remains on the scan electrode SCi, the voltage between the scan electrode SCi and the sustain electrode SUi reliably exceeds the discharge start voltage with the rise of the ramp voltage. As a result, the weak setup discharge is generated between the scan electrode SCi and the sustain electrode SUi in the setup period, so that the wall charges on each of the electrodes SCi, SUi are reliably adjusted to respective desired amounts.
Also, generation of the strong discharge between the scan electrode SCi and the data electrode Dj is prevented since the data electrode Dj is held at the voltage Vd during the period in which the ramp voltage gradually rises.
Furthermore, the weak erase discharge between the scan electrode SCi and the sustain electrode SUi reduces the wall charges on the scan electrode SCi and the wall charges on the sustain electrode SUi before the start of the setup period. Thus, a large amount of positive wall charges can remain on the scan electrode SCi and a large amount of negative wall charges can remain on the sustain electrode SUi. This weakens the write discharges between the scan electrode SCi and the data electrode Di and between the sustain electrode SUi and the scan electrode SCi in the write period following the setup period. As a result, generation of the crosstalk between the adjacent discharge cells DC can be prevented even when the distances between the adjacent discharge cells DC are small.
As shown in
Thus, the positive voltage Vd applied to the data electrode Dj may not be pulsed in the case of high breakdown voltage of the IC (Integrated Circuit), which is a constituent of the plasma display device. That is, the positive voltage Vd may be continuously applied to the data electrode Dj during application of the ramp voltage to the scan electrode SCi (a period from the time point t2 to the time point t9, for example).
While the n-channel FETs and the p-channel FETs are employed as switching devices in the data electrode driving circuit 52, the scan electrode driving circuit 53 and the sustain electrode driving circuit 54 in the above-described embodiment, the switching devices are not limited to the foregoing examples.
For example, a p-channel FET, an IGBT (Insulated Gate Bipolar Transistor) or the like may be employed instead of the n-channel FET, and an n-channel FET, an IGBT (Insulated Gate Bipolar Transistor) or the like may be employed instead of the p-channel FET in the above-described circuits.
In the following paragraphs, non-limiting examples of correspondences between various elements recited in the claims below and those described above with respect to various preferred embodiments of the present invention are explained.
The voltage Vs of
The present invention is applicable to display devices that display various images.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-327802 | Dec 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2007/073408 | 12/4/2007 | WO | 00 | 5/4/2009 |
