Patent Application
20110018852
The present invention relates to a plasma display device using a plasma display panel as a display device.
Since a plasma display panel (hereinafter, referred to as a “PDP”) can realize high definition and a large screen, 65-inch class televisions are commercialized. Recently, PDPs have been applied to high-definition television in which the number of scan lines is twice or more than that of a conventional NTSC method. Meanwhile, from the viewpoint of environmental problems, PDPs without containing a lead component have been demanded.
A PDP basically includes a front panel and a rear panel. The front panel includes a glass substrate of sodium borosilicate glass produced by a float process, display electrodes each composed of stripe-shaped transparent electrode and bus electrode formed on one principal surface of the glass substrate, a dielectric layer covering the display electrodes and functioning as a capacitor, and a protective layer made of magnesium oxide (MgO) formed on the dielectric layer. The rear panel includes a glass substrate, stripe-shaped data electrodes formed on one principal surface of the glass substrate, a base dielectric layer covering the data electrodes, barrier ribs formed on the base dielectric layer, and phosphor layers formed between the barrier ribs and emitting red, green and blue light, respectively.
Furthermore, a plasma display device using this PDP is produced as follows. The PDP is held at the front surface side of a chassis member made of a metal plate, and a drive circuit block for driving the PDP is disposed at the rear surface side of the chassis member, thus configuring a PDP module. This PDP module is accommodated in a case (see Patent document 1).
Recently, televisions have achieved higher definition. In the market, high-definition (1920×1080 pixels: progressive display) PDPs with a low cost, low power consumption and high brightness have been demanded.
[Patent document 1] Japanese Patent Unexamined Publication No. 2007-121829
A plasma display device of the present invention includes a plasma display panel, a chassis member, a drive circuit board, and a plurality of data drivers.
The plasma display panel includes a front panel having a plurality of display electrodes provided with electrode terminal portions at both opposite end portions, and a rear panel having a plurality of data electrodes arranged in a direction intersecting the display electrodes and provided with an electrode terminal portion at one end portion. The front panel and the rear panel are disposed facing each other so that discharge space is formed.
The chassis member holds this plasma display panel. The drive circuit board is disposed on the chassis member and coupled to the electrode terminal portion of the display electrode of the plasma display panel via a wiring board so as to apply a driving voltage to the display electrode of the plasma display panel.
The plurality of data drivers are disposed on one end portion that is brought into close contact with the electrode terminal portion of the data electrode of the plasma display panel on the chassis member, and coupled to the electrode terminal portion of the data electrode of the plasma display panel via the wiring board so as to apply a driving voltage to the data electrode.
The plasma display panel is configured by forming a base film on the dielectric layer covering the display electrode and attaching a plurality of crystal particles made of metal oxide to the base film so as to be distributed over an entire surface of the base film.
With such a configuration, performance of a PDP having excellent electron emission performance and high electric charge retention performance can be exhibited sufficiently. Thereby, it is possible to realize a plasma display device having high-definition and high-brightness display performance with low electric power consumption at low cost.
Hereinafter, a plasma display device in accordance with an exemplary embodiment of the present invention is described with reference to drawings.
On the front glass substrate of front panel 1, a plurality of display electrodes 6 each composed of a pair of band-like scan electrode 4 and sustain electrode 5 and black stripes (light blocking layers) 7 are disposed in parallel to each other. On the front glass substrate, dielectric layer 8 functioning as a capacitor is formed so as to cover display electrodes 6 and blocking layers 7. Furthermore, protective layer 9 made of, for example, magnesium oxide (MgO) is formed on the surface of dielectric layer 8.
Furthermore, on the rear glass substrate of rear panel 2, a plurality of band-like data electrodes 10 are disposed in parallel to each other in the direction intersecting scan electrodes 4 and sustain electrodes 5 of front panel 1. Base dielectric layer 11 covers data electrodes 10. In addition, barrier ribs 12 with a predetermined height for partitioning discharge space 3 are formed between data electrodes 10 on base dielectric layer 11. In grooves between barrier ribs 12, every data electrode 10, phosphor layers 13 emitting red, green and blue light by ultraviolet rays are formed sequentially by coating. A discharge cell is formed in a position in which scan electrode 4 and sustain electrode 5 intersect data electrode 10. The discharge cells having red, green and blue phosphor layers 13 arranged in the direction of display electrode 6 function as pixels for color display.
Image signal processing circuit 15 converts image signal sig into image data for every subfield. Data electrode drive circuit 16 converts the image data for every subfield into a signal corresponding to each of data electrodes D1 to Dm to drive each of data electrodes D1 to Dm. Timing generating circuit 19 generates various timing signals based on horizontal synchronizing signal H and vertical synchronizing signal V and supplies them to the drive circuit blocks. Scan electrode drive circuit 17 supplies a drive voltage waveform to scan electrodes SC1 to SCn based on the timing signal, and sustain electrode drive circuit 18 supplies a drive voltage waveform to sustain electrodes SU1 to SUn based on the timing signal.
Next, a drive voltage waveform for driving PDP 14 and an operation thereof are described with reference to
In the plasma display device in accordance with this exemplary embodiment, one field is divided into a plurality of subfields (SF). Each subfield has an initializing period, an address period and a sustain period.
In the initializing period of the first subfield, data electrodes D1 to Dm and sustain electrodes SU1 to SUn are kept at 0 (V). A ramp voltage, gradually increasing from voltage Vi1 (V) that is not more than a discharge starting voltage to voltage Vi2 (V) that is more than the discharge starting voltage, is applied to scan electrodes SC1 to SCn. Then, first weak initialization discharge is generated in all the discharge cells. As a result, a negative wall voltage is accumulated on scan electrodes SC1 to SCn, and a positive wall voltage is accumulated on sustain electrodes SU1 to SUn and data electrodes D1 to Dm. Herein, the wall voltage on the electrode denotes a voltage generated by wall charges accumulated on the dielectric layer, the phosphor layer, and the like, covering the electrodes.
Then, sustain electrodes SU1 to SUn are kept at positive voltage Vh (V). Then, a ramp voltage, gradually reducing from voltage Vi3 (V) to voltage Vi4 (V), is applied to scan electrodes SC1 to SCn. Then, second weak initializing discharge is generated in all the discharge cells. As a result, a wall voltage on between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn is weakened. The wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the address operation.
In the subsequent address period, scan electrodes SC1 to SCn are kept at Vc (V) once. Next, negative scan pulse voltage Va (V) is applied to scan electrode SC1 in the first row, and at the same time, positive address pulse voltage Vd (V) is applied to data electrode Dk (k=1 to m) of the discharge cell to be displayed in the first row among data electrodes D1 to Dm. At this time, a voltage on the part in which data electrode Dk intersects scan electrode SC1 is a voltage obtained by adding the wall voltage on data electrode Dk and the wall voltage on scan electrode SC1 to external applied voltage (Vd−Va) (V). As a result, a voltage in the part in which data electrode Dk intersects scan electrode SC1 exceeds the discharge starting voltage. Then, address discharge is generated between data electrode Dk and scan electrode SC1 as well as between sustain electrode SU1 and scan electrode SC1. Then, in this discharge cell, a positive wall voltage is accumulated on the scan electrode SC1 and a negative wall voltage is accumulated on sustain electrode SU1. A negative wall voltage is accumulated also on data electrode Dk.
Thus, an address operation is carried out by generating an address discharge in a discharge cell to be displayed in the first row so as to accumulate a wall voltage on each electrode. On the other hand, since a voltage in a part, in which data electrodes D1 to Dm to which address pulse voltage Vd has not been applied intersect scan electrode SC1, does not exceed the discharge starting voltage, an address discharge is not generated. The above-mentioned address operation is carried out until discharge cells in the n-th row. Thus, the address period is completed.
In the subsequent sustain period, positive sustain pulse voltage Vs (V) as a first voltage is applied to scan electrodes SC1 to SCn and a ground potential as a second voltage, that is, 0 (V) is applied to sustain electrodes SU1 to SUn, respectively. At this time, in the discharge cell in which an address discharge has been carried out, a voltage on between scan electrode SCi and sustain electrode SUi is a voltage obtained by adding the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi to sustain pulse voltage Vs (V). As a result, the voltage on between scan electrode SCi and sustain electrode SUi exceeds the discharge starting voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. With an ultraviolet ray generated at this time, phosphor layer 13 emits light. Then, a negative wall voltage is accumulated on scan electrode SCi and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on data electrode Dk.
In the discharge cell in which an address discharge has not been generated during the address period, a sustain discharge is not generated and the wall voltage at the time when the initialization period ends is maintained. Subsequently, 0 (V) as the second voltage is applied to scan electrodes SC1 to SCn. Furthermore, sustain pulse voltage Vs (V) as the first voltage is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has been generated, a voltage between a voltage on sustain electrode SUi and a voltage on scan electrode SCi exceeds the discharge starting voltage. As a result, a sustain discharge is generated again between sustain electrode SUi and scan electrode SCi, and a negative wall voltage is accumulated on sustain electrode SUi and a positive wall voltage is accumulated on scan electrode SCi.
Hereinafter, similarly, sustain pulses in the number corresponding to the brightness weight are applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, alternately. Thereby, a sustain discharge is continuously carried out in the discharge cell in which an address discharge is generated in the address period. Thus, a sustain operation in the sustain period is completed.
Since operations in the initializing period, address period and sustain period in the subsequent subfield are substantially the same as those in the first subfield, description thereof is omitted.
In
As shown in
Next, a panel portion of PDP 14 and a PDP module are described in detail with reference to
Firstly, as shown in
As shown in
On the other hand, on the lower end portion of PDP 14, as shown in
Control circuit board 31 converts image data into an image data signal corresponding to the number of pixels of PDP 14 and supplies the image data signal to drive circuit board 30 of data electrode drive circuit 16 based on a video signal transmitted from input signal circuit block 32 provided with an input terminal portion to which a connection cable to be connected to an external equipment such as television tuner is detachably connected. Furthermore, control circuit board 31 generates a discharge control timing signal, and supplies it to drive circuit board 26 of scan electrode drive circuit 17 and drive circuit board 27 of sustain electrode drive circuit 18, respectively, thus carrying out display driving control such as gradation control. Control circuit board 31 is disposed in substantially the central portion of chassis member 20.
Power supply block 33 supplies a voltage to each circuit block. Similar to control circuit board 31, power supply block 33 is disposed in substantially the central portion of chassis member 20. The commercial power supply voltage is supplied to power supply block 33 through a connector to which a power supply cable (not shown) is placed. Furthermore, in the vicinity of drive circuit boards 26 and 27, a cooling fan (not shown) is disposed in a state in which it is held at an angle. Wind sent from this cooling fan cools drive circuit boards 26 and 27.
Next, a configuration of PDP 14 used in the present invention is described in more detail.
Dielectric layer 8 includes at least two layers, that is, first dielectric layer 81 and second dielectric layer 82. First dielectric layer 81 is provided to cover transparent electrodes 4a and 5a, metal bus electrodes 4b and 5b and light blocking layers 7 formed on the front glass substrate. Second dielectric layer 82 is formed on first dielectric layer 81. In addition, protective layer 9 is formed on second dielectric layer 82. Protective layer 9 includes base film 91 formed on dielectric layer 8 and aggregated particles 92 attached to base film 91.
Herein, first dielectric layer 81 and second dielectric layer 82 forming dielectric layer 8 of front panel 1 are described in detail.
Firstly, a dielectric material of first dielectric layer 81 includes the following material compositions: 20 wt. % to 40 wt. % of bismuth oxide (Bi2O3); 0.5 wt. % to 12 wt. % of at least one selected from calcium oxide (CaO), strontium oxide (SrO) and barium oxide (BaO); and 0.1 wt. % to 7 wt. % of at least one selected from molybdenum oxide (MoO3), tungsten oxide (WO3), cerium oxide (CeO2), and manganese oxide (MnO2).
Instead of molybdenum oxide (MoO3), tungsten oxide (WO3), cerium oxide (CeO2) and manganese oxide (MnO2), 0.1 wt. % to 7 wt. % of at least one selected from copper oxide (CuO), chromium oxide (Cr2O3), cobalt oxide (CO2O3), vanadium oxide (V2O7) and antimony oxide (Sb2O3) may be included.
Furthermore, as components other than the above-mentioned components, material compositions that do not include a lead component, for example, 0 wt. % to 40 wt. % of zinc oxide (ZnO), 0 wt. % to 35 wt. % of boron oxide (B2O3), 0 wt. % to 15 wt. % of silicon oxide (SiO2) and 0 wt. % to 10 wt. % of aluminum oxide (Al2O3) may be included. The contents of these material compositions are not particularly limited.
The dielectric materials including these composition components are ground to an average particle diameter of 0.5 μm to 2.5 μm by using a wet jet mill or a ball mill to form dielectric material powder. Then, 55 wt % to 70 wt % of the dielectric material powders and 30 wt % to 45 wt % of binder components are well kneaded by using a three-roller to form a paste for the first dielectric layer to be used in die coating or printing.
The binder component is ethyl cellulose, or terpineol containing 1 wt % to 20 wt % of acrylic resin, or butyl carbitol acetate. Furthermore, in the paste, if necessary, at least one or more of dioctyl phthalate, dibutyl phthalate, triphenyl phosphate and tributyl phosphate may be added as a plasticizer; and at least one or more of glycerol monooleate, sorbitan sesquioleate, Homogenol (Kao Corporation), and an alkylallyl phosphate may be added as a dispersing agent, so that the printing property may be improved.
This first dielectric layer paste is printed on a front glass substrate so as to cover display electrodes 6 by a die coating method or a screen printing method and dried, followed by firing at a temperature of 575° C. to 590° C., that is, a slightly higher temperature than the softening point of the dielectric material.
Next, second dielectric layer 82 is described. A dielectric material of second dielectric layer 82 includes the following material compositions: 11 wt. % to 20 wt. % of bismuth oxide (Bi2O3); 1.6 wt. % to 21 wt. % of at least one selected from calcium oxide (CaO), strontium oxide (SrO) and barium oxide (BaO); and 0.1 wt. % to 7 wt. % of at least one selected from molybdenum oxide (MoO3), tungsten oxide (WO3), and cerium oxide (CeO2).
Instead of molybdenum oxide (MoO3), tungsten oxide (WO3), cerium oxide (CeO2), 0.1 wt. % to 7 wt. % of at least one selected from copper oxide (CuO), chromium oxide (Cr2O3), cobalt oxide (CO2O3), vanadium oxide (V2O7), antimony oxide (Sb2O3) and manganese oxide (MnO2) may be included.
Furthermore, as components other than the above-mentioned components, material compositions that do not include a lead component, for example, 0 wt. % to 40 wt. % of zinc oxide (ZnO), 0 wt. % to 35 wt. % of boron oxide (B2O3), 0 wt. % to 15 wt. % of silicon oxide (SiO2) and 0 wt. % to 10 wt. % of aluminum oxide (Al2O3) may be included. The contents of these material compositions are not particularly limited.
The dielectric materials including these composition components are ground to an average particle diameter of 0.5 μm to 2.5 μm by using a wet jet mill or a ball mill to form dielectric material powder. Then, 55 wt % to 70 wt % of the dielectric material powders and 30 wt % to 45 wt % of binder components are well kneaded by using a three-roller to form a paste for the second dielectric layer to be used in die coating or printing. The binder component is ethyl cellulose, or terpineol containing 1 wt % to 20 wt % of acrylic resin, or butyl carbitol acetate. Furthermore, in the paste, if necessary, dioctyl phthalate, dibutyl phthalate, triphenyl phosphate and tributyl phosphate may be added as a plasticizer; and at least one or more of glycerol monooleate, sorbitan sesquioleate, Homogenol (Kao Corporation), and an alkylallyl phosphate may be added as a dispersing agent, so that the printing property may be improved.
This second dielectric layer paste is printed on first dielectric layer 81 by a screen printing method or die coating method and dried, followed by firing at a temperature of 550° C. to 590° C., that is, a slightly higher temperature than the softening point of the dielectric material.
Note here that it is preferable that the film thickness of dielectric layer 8 in total of first dielectric layer 81 and second dielectric layer 82 is not more than 41 μm in order to secure the visible light transmittance. In first dielectric layer 81, in order to suppress the reaction between metal bus electrodes 4b and 5b and silver (Ag), the content of bismuth oxide (Bi2O3) is set to be 20 wt % to 40 wt %, which is higher than the content of bismuth oxide in second dielectric layer 82. Therefore, since the visible light transmittance of first dielectric layer 81 becomes lower than that of second dielectric layer 82, the film thickness of first dielectric layer 81 is set to be thinner than that of second dielectric layer 82.
In second dielectric layer 82, it is not preferable that the content of bismuth oxide (Bi2O3) is not more than 11 wt % because bubbles tend to be generated in second dielectric layer 82 although coloring does not easily occur. Furthermore, it is not preferable that the content is more than 40 wt % for the purpose of increasing the transmittance because coloring tends to occur.
As the film thickness of dielectric layer 8 is smaller, the effect of improving the panel brightness and reducing the discharge voltage is more remarkable. Therefore, it is desirable that the film thickness is set to be as small as possible within a range in which withstand voltage is not lowered. From such a viewpoint, in the exemplary embodiment of the present invention, the film thickness of dielectric layer 8 is set to be not more than 41 μm, that of first dielectric layer 81 is set to be 5 μm to 15 μm, and that of second dielectric layer 82 is set to be 20 μm to 36 μm.
In the thus manufactured PDP 14, even when a silver (Ag) material is used for display electrode 6, a coloring phenomenon (yellowing) in the front glass substrate is suppressed and bubbles are not generated in dielectric layer 8. Therefore, dielectric layer 8 having excellent withstand voltage performance can be realized.
That is to say, in dielectric layer 8 of PDP 14 of the present invention, the generation of yellowing phenomenon and bubbles is suppressed in first dielectric layer 81 that is in contact with metal bus electrodes 4b and 5b made of a silver (Ag) material. Furthermore, in dielectric layer 8, high light-transmittance is realized by second dielectric layer 82 formed on first dielectric layer 81. As a result, it is possible to realize PDP 14 in which generation of bubbles and yellowing is extremely small and transmittance is high in dielectric layer 8 as a whole.
Next, a configuration and a manufacturing method of protective layer 9 of PDP 14 in accordance with the exemplary embodiment of the present invention are described.
PDP 14 in accordance with this exemplary embodiment of the present invention includes protective layer 9 as shown in
Herein, aggregated particle 92 is in a state in which crystal particles 92a having a predetermined primary particle diameter are aggregated or necked as shown in
Furthermore, the primary particle diameter of crystal particle 92a of MgO can be controlled by the production condition of crystal particle 92a. For example, when crystal particle 92a of MgO is produced by firing an MgO precursor such as magnesium carbonate or magnesium hydroxide, the particle diameter can be controlled by controlling the firing temperature or firing atmosphere. In general, the firing temperature can be selected in the range from about 700° C. to about 1500° C. When the firing temperature is set to be a relatively high temperature such as not less than 1000° C., the primary particle diameter can be controlled to be about 0.3 μm to 2 μm. Furthermore, when crystal particle 92a is obtained by heating an MgO precursor, it is possible to obtain aggregated particles 92 in which a plurality of primary particles are combined by aggregation or a phenomenon called necking during production process.
Furthermore, in
Furthermore, the electric charge retention performance is represented by using, as its index, a value of a voltage applied to a scan electrode (hereinafter, referred to as “Vscn lighting voltage”) necessary to suppress the phenomenon of releasing electric charge when a PDP is produced. That is to say, it is shown that the lower the Vscn lighting voltage is, the higher the electric charge retention performance is. This is advantageous in designing of a panel of the PDP because driving at a low voltage is possible. That is to say, as a power supply block or electrical components of the PDP, components having a withstand voltage and a small capacity can be used. In current products, as a semiconductor switching element such as MOSFET for applying a scanning voltage to a panel sequentially, an element having a withstand voltage of about 150 V is used. Therefore, it is desirable that the Vscn lighting voltage is reduced to not more than 120 V with considering the fluctuation due to temperatures.
As is apparent from
In this way, according to PDP 14 of the present invention, the electron emission property of not less than 6 and Vscn lighting voltage as the electric charge retention performance of not more than 120 V can be realized. Thus, even if the number of scan lines is increased with high definition and the cell size is reduced, it is possible to accumulate sufficient wall voltage in each discharge cell in a predetermined address period. Therefore, as shown in
Herein, the particle diameter of crystal particle 92a is described. In the description below, the particle diameter denotes an average particle diameter, i.e., a volume cumulative mean diameter (D50).
In order to increase the number of emitted electrons in the discharge cell, it is desirable that the number of crystal particles per unit area on the base layer is large. According to the experiment carried out by the present inventors, when crystal particles exist in a portion corresponding to the top portion of the barrier rib of the rear panel that is in close contact with the protective layer of the front panel, the top portion of the barrier rib may be damaged. As a result, it is shown that the material may be put on a phosphor, causing a phenomenon that the corresponding cell is not normally lighted. The phenomenon that the barrier rib is damaged does not easily occur when crystal particles do not exist on a portion corresponding to the top portion of the barrier rib. Therefore, as the number of crystal particles to be attached increases, the rate of occurrence of the damage of the barrier rib increases.
As is apparent from
Based on the above-mentioned results, it is thought to be desirable that crystal particles of PDP 14 in accordance with the exemplary embodiment have a particle diameter of not less than 0.9 μm and not more than 2.5 μm. However, in actual mass production of PDPs, variation of crystal particles in manufacturing or variation in manufacturing a protective layer needs to be considered. In order to consider the factors of variation in manufacturing and the like, an experiment using crystal particles having different particle size distributions is carried out.
In the above description, as a protective layer, MgO is used as an example. However, performance required by the base is high sputter resistance performance for protecting a dielectric layer from ion bombardment, and electron emission performance may not be so high. In most of conventional PDPs, a protective layer containing MgO as a main component is formed in order to obtain predetermined level or more of electron emission performance and sputter resistance performance. However, for achieving a configuration in which the electron emission performance is mainly controlled by single-crystal particles of metal oxide, MgO is not necessarily used. Other materials such as Al2O3 having an excellent shock resistance property may be used.
In this exemplary embodiment, MgO particles are used as single-crystal particles, but the other single-crystal particles may be used. The same effect can be obtained when other single-crystal particles of oxide of metal such as Sr, Ca, Ba, and Al having high electron emission performance similar to MgO are used. Therefore, the kind of particle is not limited to MgO.
As described above, the plasma display device in accordance with the exemplary embodiment includes PDP 14 in which base film 91 is formed on dielectric layer 8 covering display electrode 6, plurality of aggregated particles 92 made of metal oxide are attached to base film 91 so as to be distributed to the entire surface. The plasma display device includes chassis member 20 holding PDP 14, drive circuit boards 26 and 27 disposed on chassis member 20, connected to electrode terminal portions 14a and 14b of PDP 14 via flexible wiring board 25 so as to apply a driving voltage to display electrode 6 of PDP 14, a plurality of data drivers 29 disposed on one end in the vicinity of electrode terminal portion 14c of data electrode 10 of PDP 14 in chassis member 20, connected to electrode terminal portion 14c of data electrode 10 of PDP 14 via flexible wiring board 28 electrode terminal portion 14c and applying a driving voltage data electrode 10.
With such a configuration, even when the number of scan lines is increased with high definition and the cell size is reduced, in the predetermined address period, a sufficient wall voltage can be accumulated in each discharge cell. Therefore, a drive circuit can be configured in which data drivers for applying a driving voltage to a data electrode are disposed only on the side of lower end portion and the number of the data drivers can be reduced. Therefore, the entire electric power consumption can be reduced and the cost can be reduced.
As mentioned above, the present invention is useful for realizing a plasma display device having a display performance with high brightness and low electric power consumption.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-056103 | Mar 2008 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2009/000825 | 2/25/2009 | WO | 00 | 8/11/2009 |
