Patent Application
20100026733
The present invention relates to a plasma display device which is an image display device using a plasma display panel.
In an image display device that performs display of gradation using subfields, such as a plasma display device using a plasma display panel (hereinafter, simply referred to as “panel”), quality deterioration of noisy image, called a dynamic false contour, may be observed in a motion image region. The dynamic false contour is a phenomenon that occurs when the pattern of subfields for causing discharge cells to emit light discontinuously changes with respect to a continuous change of gradation values. As well known in the art, if the number of subfields increases, the dynamic false contour is improved. However, if the number of subfields increases, a time which can be used for light emission is shortened, and necessary luminance is not obtained.
For this reason, there is an attempt to suppress the dynamic false contour by limiting a combination of subfields in a region where there is a movement, without increasing the number of subfields too much. This attempt is disclosed in, for example, Patent Document 1. Such an image display device limits gradations to be used for display so as to display an image by a combination of gradations, at which a dynamic false contour is difficult to occur, and adds pseudo gradations using dithering, thereby compensating image quality deterioration due to a decrease in the number of gradations.
However, if the gradations are further limited in order to increase a dynamic false contour suppression effect, a pattern for dithering is easily noticeable, and the number of gradations to be actually expressed decreases.
In order to solve this problem, for example, the following method is disclosed. In this method, a region where the gradations have a gradient and there is a movement is detected from image signals. Then, one of a plurality of corrected gradations set for the gradations of the image signals is selected in accordance with the magnitude or direction of the movement of the region and the magnitude or direction of the gradient of the gradations and substituted for original gradation. In this way, an intermediate non-lighting subfield (a non-lighting subfield having a luminance weight smaller than a lighting subfield having a maximum luminance weight), which causes a dynamic false contour, is dispersed, thereby suppressing the dynamic false contour. Such a method is disclosed in, for example, Patent Document 2.
Meanwhile, in order to display an image using the panel, a plurality of data electrodes need to be independently driven on the basis of image signals. Then, in order to drive the data electrodes, stray capacitance between a data electrode and a scan electrode, between a data electrode and a sustain electrode, or between adjacent data electrodes needs to be charged and discharged which consumes power.
If the image processing described in Patent Document 2 is performed, the dynamic false contour can be suppressed to the extent that it is almost unrecognizable, but the number of subfields in which a light-emitting pixel and a non-light-emitting pixel are likely to be close to each other increases. For this reason, power required for driving the data electrodes increases. In recent years, with advancement of high definition and large screen of the panel, inter-electrode stray capacitance increases. As a result, there is an urgent need to suppress power required for driving the data electrodes.
[Patent Document 1] Japanese Patent Unexamined Publication No. 2000-276100
[Patent Document 2] Japanese Patent Unexamined Publication No. 2004-4782
The invention has been made in consideration of the above-described problems, and it is an object of the invention to provide a plasma display device that can suppress an increase in power consumption and can effectively suppress a dynamic false contour.
A plasma display device includes a plasma display panel having a plurality of discharge cells each having a data electrode, a data electrode driving circuit for driving the data electrodes, and an image signal processing circuit for performing a signal processing on an image signal and supplying the processed image signal to the data electrode driving circuit. The image signal processing circuit performs a first signal processing on an image signal to be displayed in a central region of an image region of the plasma display panel, and performs a second signal processing on an image signal to be displayed in a peripheral region of the image region. The second signal processing outputs the image signal which needs lower power consumption of the data electrode driving circuit than the image signal output by the first signal processing.
Hereinafter, an embodiment of the invention will be described with reference to the drawings.
Front substrate 21 and rear substrate 31 are arranged to be opposite each other with a minute discharge space such that display electrode pairs 24 and data electrodes 32 intersect each other. Front substrate 21 and rear substrate 31 are bonded to each other at the outer circumferences thereof by a sealing material, such as glass frit or the like. The discharge space is filled with, for example, mixed gas of neon and xenon as discharge gas. The discharge space is divided into a plurality of sections by barrier rib 34, and discharge cells are formed at the intersections of display electrode pairs 24 and data electrodes 32. The discharge cells are discharged and emit light, thereby displaying an image.
The structure of panel 10 is not limited to the above structure, and it may have a stripe-shaped barrier rib, for example.
Inter-electrode capacitance exists between the electrodes arranged in such a manner.
Next, a method of driving panel 10 will be described. In this embodiment, a so-called subfield process is used for displaying gradation. The subfield process divides a field into a plurality of subfields and controls lighting or non-lighting of each discharge cell for each subfield, thereby performing display of gradation. The details regarding the number of subfields and the luminance weights of subfields in this embodiment will be described later.
Each subfield has an initializing period, an address period, and a sustain period.
During the initializing period of subfield SF1, 0 (V) is applied to data electrodes D1 to Dm and sustain electrodes SU1 to SUn, and a ramp voltage, which gradually rises from voltage Vi1 toward Vi2, is applied to scan electrodes SC1 to SCn. Thereafter, voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a ramp voltage, which gradually falls from voltage Vi3 toward Vi4, is applied to scan electrodes SC1 to SCn. Then, weak initializing discharge occurs in each discharge cell, and wall charges required for an address operation are formed on the electrodes. With respect to the operation of the initializing period, like the initializing period of subfield SF2 in
Subsequently, during the address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, voltage Vc is applied to scan electrodes SC1 to SCn, and 0 (V) is applied to data electrodes D1 to Dm. Next, scan pulse voltage Va is applied to scan electrode SC1 of a first line, and address pulse voltage Vd is applied to data electrodes Dk (where k=1 to m) corresponding to discharge cells to emit light. Then, address discharge occurs in the discharge cells of the first line, to which scan pulse voltage Va and address pulse voltage Vd are applied simultaneously, and an address operation to accumulate wall charges on scan electrode SC1 and sustain electrode SU1 is performed.
The same address operation is performed for the discharge cells of the second line to the n-th line. In this way, address discharge selectively occurs for the discharge cells to emit light, and wall charges are formed.
As shown in
During the subsequent sustain period, 0 (V) is applied to sustain electrode SU1 to SUn, and sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. Then, sustain discharge occurs in the discharge cells where address discharge occurred, and causes the discharge cells to emit light.
Next, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, sustain discharge occurs again in the discharge cells where sustain discharge occurred, and causes the discharge cells to emit light. Thereafter, sustain pulses are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn on the basis of a luminance weight, such that the discharge cells emit light. Thereafter, sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn and voltage Ve1 is applied to sustain electrodes SU1 to SUn so as to perform a so-called wall charge erasure, and the sustain period ends.
Subsequently, in subfield SF2, the same operation as that in the above-described subfield is repeatedly performed so as to cause the discharge cells to emit light. Thus, an image is displayed.
Next, the subfield structure will be described. In this embodiment, it is assumed that one field is divided into 12 subfields (SF1, SF2, . . . , and SF12), and the subfields have luminance weights (1, 2, 4, 8, 12, 20, 24, 28, 32, 36, 40, and 48), respectively.
In order to express the gradation values from “0” to “255”, for example, eight subfields having luminance weights of power of “2” may be used. As well known in the art, however, if such a subfield structure is used, an extremely strong dynamic false contour is generated. Therefore, in this embodiment, the number of the subfields is increased to 12, and a dynamic false contour is suppressed by using coding which ensures little change in the pattern of subfields where discharge cells are caused to emit light.
Arrow A in
Image signal processing circuit 41 performs a dynamic false contour prevention processing on an image signal, and outputs image data corresponding to “1” and “0” of each bit of a digital signal which indicates lighting or non-lighting of each subfield.
Data electrode driving circuit 42 includes m switch circuits SW1 to SWm for applying address pulse voltage Vd or 0 (V) to m data electrodes D1 to Dm, respectively. Data electrode driving circuit 42 converts image data output from image signal processing circuit 41 into address pulse voltage Vd corresponding to respective data electrodes D1 to Dm, and applies address pulse voltage Vd to respective data electrodes D1 to Dm.
Timing generation circuit 45 generates various timing signals for controlling the operations of the circuits on the basis of a horizontal synchronization signal and a vertical synchronization signal, and supplies the timing signals to the circuits. Scan electrode driving circuit 43 drives scan electrodes SC1 to SCn on the basis of the timing signals. Sustain electrode driving circuit 44 drives sustain electrodes SU1 to SUn on the basis of the timing signals.
Selection signal generation circuit 55 has image region signal generation section 61, random number generation section 63, binarization section 64, and binarization selection section 65. Image region signal generation section 61 divides the image region into frame-shaped concentric regions, and outputs signals representing the respective regions.
In this embodiment, random number generation section 63 generates a random number equal to or more than “0” and less than “4” for each pixel clock generated by timing generation circuit 45.
In this embodiment, binarization section 64 has three comparators 64a, 64b, and 64c. Comparator 64a compares the random number generated by random number generation section 63 with “1”, and when the random number is less than “1”, it outputs “0”, and when the random number is equal to or more than “1”, it outputs “1”. Comparator 64b compares the random number generated by random number generation section 63 with “2”, and when the random number is less than “2”, it outputs “0”, and when the random number is equal to or more than “2”, it outputs “1”. Comparator 64c compares the random number generated by random number generation section 63 with “3”, and when the random number is less than “3”, it outputs “0”, and when the random number is equal to or more than “3”, it outputs “1”.
Binarization selection section 65 selects one of the outputs of the three comparators 64a, 64b, and 64c, “0”, and “1” on the basis of the image region signal output from image region signal generation section 61. Specifically, binarization selection section 65 selects “1” when the image region signal represents central region 81, and selects the output of comparator 64a when the image region signal represents first transition region 82. Binarization selection section 65 selects the output of comparator 64b when the image region signal represents second transition region 83, and selects the output of comparator 64c when the image region signal represents third transition region 84. Binarization selection section 65 selects “0” when the image region signal represents peripheral region 85. Therefore, the selection signal output from binarization selection section 65 is constantly “1” when the image region signal represents central region 81, and is “1” with a probability of ¾ when the image region signal represents first transition region 82. The selection signal output from binarization selection section 65 is “1” with a probability of ½ when the image region signal represents second transition region 83, is “1” with a probability of ¼ when the image region signal represents third transition region 84, and is constantly “0” when the image region signal represents peripheral region 85.
Image signal selection circuit 56 selects an image signal output from first false contour suppression circuit 51 when the selection signal output from binarization selection section 65 is “1”, and selects an image signal output from second false contour suppression circuit 52 when the selection signal is “0”. Therefore, the first signal processing is performed on an image signal to be displayed in central region 81 of the image region of panel 10. With respect to an image signal to be displayed in first transition region 82, the first signal processing is performed with a probability of ¾, and the second signal processing is performed with a probability of ¼. With respect to an image signal to be displayed in second transition region 83, the first signal processing is performed with a probability of ½, and the second signal processing is performed with a probability of ½. With respect to an image signal to be displayed in third transition region 84, the first signal processing is performed with a probability of ¼, and the second signal processing is performed with a probability of ¾. With respect to an image signal to be displayed in peripheral region 85, the second signal processing is performed.
For first false contour suppression circuit 51 and second false contour suppression circuit 52, various circuits may be used. In this embodiment, since a dynamic false contour is somehow suppressed by using coding, which ensures little change in the pattern of subfields where discharge cells are caused to emit light, it is assumed that, for second false contour suppression circuit 52, a circuit which outputs an input image signal unchanged is used. In addition, it is assumed that, for first false contour suppression circuit 51, for example, a circuit which selects one of a plurality of corrected gradations set for the gradations of an image signal and substitutes the selected corrected gradation for an original gradation is used.
Correction value generation section 72 generates two correction values “−m” and “+m” for each gradation of the image signal. Correction value switching section 73 switches the two correction values in a pixel unit, alternately in a line unit, or randomly. Addition section 74 adds the output of correction value switching section 73 and the image signal to convert a predetermined signal of the image signal into a corrected gradation, and outputs the corrected gradation as a corrected image signal. Since the correction values have the values “−m” and “+m”, the average value of corrected gradations obtained by adding the correction values is equal to the gradation before correction. In addition, since correction value switching section 73 switches the correction values in a pixel unit, alternately in a line unit, or randomly, the average value of the corrected image signal is not changed by correction.
Subtraction section 75 calculates a difference between the image signal before correction and the corrected image signal to generate a difference signal. The difference signal is delayed by predetermined delay section 76, and is added to an input signal by using addition section 77. If such a feedback circuit structure is used as a gradation correction section, the average gradation value including peripheral pixels can approximate to the gradation value before correction, an error in the gradation associated with gradation correction can be corrected in a pseudo manner.
Next, the operation of first false contour suppression circuit 51 will be described. In this embodiment, a gradation based on coding shown in
As described above, it is known that when the line of sight moves at a speed following the intermediate non-lighting subfield in the gradient gradation region, a strong dynamic false contour occurs. In the above example, if the line of sight moves at such a speed that subfields SF6 to SF11 pass while the gradation value increases from “164” to “184”, the human being continuously recognizes the maximum intermediate non-lighting subfield, and a dark line appears as a dynamic false contour.
Table 123 shows an average lighting probability of subfields for gradations of an image display device according to the embodiment of the invention. The numerical value of each column is a lighting probability after correction. Here, “1” and “½” represent lighting probabilities 1 and ½, respectively, and a blank represents a lighting probability 0. For example, with respect to the signal of gradation “168”, the maximum intermediate non-lighting subfield before correction is subfield SF10, and the lighting probability of subfield SF10 is 0. Meanwhile, the intermediate non-lighting subfield after correction is dispersed to subfields SF9 and SF11, and the lighting probabilities of subfields SF9 and SF11 become ½. For this reason, the dynamic false contour in the corrected region is dispersed, and as a result, image display quality is improved.
However, if such correction is performed, the number of subfields in which a light-emitting pixel and a non-light-emitting pixel are close to each other increases, and accordingly power for driving the data electrodes also increases. For example, with respect to the signal of gradation “168”, it is assumed that the gradation “168” is converted into two corrected gradations of a gradation “164” and a gradation “172”, and the corrected gradations are switched alternately in pixel unit and in a line unit to output a pattern in which the corrected gradations are arranged checkerwise.
In this case, with focusing on the current IDj+3 flowing in the data electrode Dj+3, current flows to charge/discharge inter-electrode capacitance Cs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and data electrodes Dj+3. In addition, a current flows to charge/discharge inter-electrode capacitance Cd against the address pulse to be applied in opposite phase to data electrode Dj+2 adjacent to data electrode Dj+3. For this reason, during the address period of subfield SF9, power consumption of data electrode driving circuit 42 increases. The same is applied to the address period of subfield SF11.
As described above, according to first false contour suppression circuit 51, a dynamic false contour can be effectively suppressed, but the number of subfields where a checked pattern is displayed increases. For this reason, power consumption of data electrode driving circuit 42 becomes high.
In this embodiment, the image signal processing with high power consumption of data electrode driving circuit 42 is performed only in central region 81 where a dynamic false contour is easily noticeable. Meanwhile, in this embodiment, in peripheral region 85 where a dynamic false contour is difficult to be noticeable, power consumption is preferentially suppressed. In this way, a dynamic false contour can be effectively suppressed while power consumption can be suppressed. If a transition region is provided between central region 81 and peripheral region 85, and a selection ratio of an image signal in the transition region gradually changes, display images of central region 81 and peripheral region 85 can be smoothly connected to each other.
In this embodiment, as first false contour suppression circuit 51, a circuit that disperses an intermediate non-lighting subfield to suppress a dynamic false contour is used, and as second false contour suppression circuit 52, a circuit that outputs an input image signal unchanged is used. However, the invention is not limited thereto, and various circuits may be used. For example, as first false contour suppression circuit 51 and second false contour suppression circuit 52, circuits that disperse an intermediate non-lighting subfield to suppress a dynamic false contour may be used. In this case, first false contour suppression circuit 51 may disperse the maximum intermediate non-lighting subfield in a wider range than second false contour suppression circuit 52, and the subfields may have a high lighting probability. As first false contour suppression circuit 51, a circuit that performs dithering to make the number of gradations to be displayed larger than the number of gradations in second false contour suppression circuit 52 may be used. With respect to other circuits, a circuit that performs an image signal processing to output an image signal with good image display quality while increasing power consumption of data electrode driving circuit 42 to some extent, and a circuit that performs an image signal processing to output an image signal with power consumption of data electrode driving circuit 42 preferentially suppressed may be applied to the invention as first false contour suppression circuit 51 and as second false contour suppression circuit 52, respectively.
The number of subfields, the luminance weight, and other specific numerical values used in this embodiment are just for illustrative purposes, and preferably, optimum values are appropriately set depending on the characteristics of the panel or the specification of the plasma display device.
As will be apparent from the above description, according to the invention, it is possible to provide a plasma display device that can effectively suppress a dynamic false contour while suppressing an increase in power consumption.
The invention is useful for a plasma display device which can effectively suppress a dynamic false contour while suppressing an increase in power consumption, and in particular, a large-screen plasma display device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-286983 | Nov 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/003090 | 10/29/2008 | WO | 00 | 5/20/2009 |
