1. Field of the Invention
This invention relates to the configuration of a plasma display panel and a drive method for a plasma display panel.
2. Description of the Related Art
Nowadays, as thin-screen display devices, plasma display panels (hereinbelow, abbreviated to the “PDPs”) of AC type (AC discharge type) have been put into commercial production. In the PDP, two substrates, namely, a front transparent substrate and a rear substrate, are arranged in opposition through a predetermined spacing. A plurality of row electrode pairs in which row electrodes forming the respective pairs extend in the lateral direction of a screen are formed on that inner surface of the front transparent substrate (a surface opposing to the rear substrate) which is a display surface. Further, a dielectric layer which covers the respective row electrode pairs are formed on such an inner surface of the front transparent substrate. On the other hand, a plurality of column electrodes which extend in the vertical direction of the screen so as to intersect the row electrode pairs are formed on the rear substrate. In a case where the PDP is viewed from the side of the display surface, pixel cells corresponding to pixels are formed at the intersection parts between the row electrode pairs and the column electrodes.
In a prior-art AC type plasma display panel (“PDP”) of surface discharge scheme, a magnesium oxide layer which contains magnesium oxide crystals that have the characteristic of presenting cathode-luminescence emission (hereinbelow, termed the “CL emission”) having a peak within a wavelength region of 200-300 nm, by excitation based on an electron beam, is formed as a protective layer on the surface of a dielectric layer covering row electrodes as confront discharge cells, whereby discharge characteristics such as the discharge delay time of a discharge generated within the discharge cell are improved by the characteristic of the magnesium oxide crystals contained in the magnesium oxide layer. For example, Japanese Patent Kokai No. 2006-59779 (Patent Document 1) discloses the above-described PDP.
Besides, in a prior-art PDP, a magnesium oxide layer which contains magnesium oxide crystals that present photoluminescence emission (hereinbelow, termed the “PL emission”) radiating ultraviolet radiation with a peak wavelength at 230-250 nm, when excited by ultraviolet radiation radiated from a discharge gas, is formed at, at least, a part confronting each discharge cell, between a front substrate and a rear substrate, and a fluorophor layer fluoresces when excited by the ultraviolet radiation which is radiated by the PL emission of the magnesium oxide crystals contained in the magnesium oxide layer, and the ultraviolet radiation which is radiated from the discharge gas, whereby an intensity can be enhanced. For example, Japanese Patent Kokai No. 2006-59786 (Patent Document 2) discloses the PDP mentioned above.
Further betterments in the discharge characteristics and further enhancement in the intensity are required of such prior-art PDPs. It is also required to prevent the lowering of a dark contrast attributed to reset discharges (discharges for initializing all the discharge cells) which are performed within the discharge cells during the drive of the PDP.
Such a PDP is subjected to a gradation drive employing a subfield method, in order to obtain a display intensity of halftone corresponding to an input video signal.
In the gradation drive based on the subfield method, a display drive for the video signal for one field is performed in a plurality of subfields to which the numbers of times (or periods) for performing light emissions are respectively allotted. In each subfield, an address step and a sustain step are successively executed. In the address step, selective discharges are caused between the row electrodes and the column electrodes within the respective pixel cells in accordance with the input video signal, thereby to form (or erase) predetermined quantities of wall charges. In the sustain step, only the pixel cells formed with the predetermined quantities of wall charges are repeatedly discharged, thereby to sustain light emission states induced by the discharges. Further, in at least the head subfield, a reset step is executed in advance of the address step. In such a reset step, the reset discharges are caused between the paired row electrodes within all the pixel cells, thereby to initialize the quantities of the wall charges remaining within all the pixel cells.
Here, the reset discharges are comparatively strong discharges and are not pertinent to the contents of an image to-be-displayed at all. Therefore, the PDPs have had the problem that the light emissions induced by the discharges lower the contrast of the image.
In this regard, there have been proposed a PDP and a drive method therefor wherein magnesium oxide crystals which present cathode-luminescence emission having a wavelength peak within 200-300 nm, when excited by electron beam irradiation, are stuck on the surface of a dielectric layer covering row electrode pairs, thereby to shorten a discharge delay time. For example, Japanese Patent Kokai No. 2006-54160 (Patent Document 3) discloses this PDP. According to such a PDP, a priming effect after a discharge continues for a comparatively long time, and hence, a weak discharge can be caused stably. Therefore, a reset pulse in a pulse waveform whose voltage value arrives at a peak voltage value gradually with the lapse of time is impressed on the row electrodes of the PDP as stated above, whereby a weak reset discharge is caused between the row electrodes adjacent to each other. Owing to the weak reset discharge, a light emission intensity attendant upon the discharge becomes low, so that the contrast of the image can be heightened.
Even with such a drive method, however, the so-called “dark contrast” in the case of displaying a dark image cannot be satisfactorily heightened, and this has posed the problem that the dark image cannot be offered in a state of high quality.
This invention has for one of its objects to meet the requirements for the prior-art PDPs as stated above.
A PDP according to a first aspect of this invention for accomplishing the object consists in a plasma display panel including a pair of substrates which oppose to each other through a discharge space, a plurality of row electrode pairs which are disposed on one of the pair of substrates, a plurality of column electrodes which are disposed on the other substrate so as to extend in a direction intersecting the row electrode pairs and which form unit light emission regions in the discharge space at their respective parts intersecting the row electrode pairs, and fluorophor layers which are disposed at positions confronting the unit light emission regions between the column electrodes and the row electrode pairs, wherein a discharge gas is enclosed in the discharge space. In the plasma display panel, a secondary electron emission material is contained in the fluorophor layers; and the secondary electron emission material is magnesium oxide which contains magnesium oxide crystals that have a characteristic of presenting a cathode luminescence light emission having a peak within a wavelength region of 200-300 nm, when excited by an electron beam.
A drive method for a PDP according to a second aspect for accomplishing the object consists in a drive method for a plasma display panel including a pair of substrates which oppose to each other through a discharge space, a plurality of row electrode pairs which are disposed on one of the pair of substrates, a plurality of column electrodes which are disposed on the other substrate so as to extend in a direction intersecting the row electrode pairs and which form unit light emission regions in the discharge space at their respective parts intersecting the row electrode pairs, and fluorophor layers which are disposed at positions confronting the unit light emission regions between the column electrodes and the row electrode pairs and which contain a secondary electron emission material, wherein a discharge gas is enclosed in the discharge space. The drive method has, in the drive step, a step of impressing a voltage pulse on row electrodes on one side, which constitute the row electrode pairs, and setting a potential of the column electrodes on a cathode side relatively to the row electrodes on one side, which have been impressed with the voltage pulse, whereby opposed discharges are generated between the column electrodes and the row electrodes on one side, through the fluorophor layers.
The PDP according to this invention includes the pair of substrates which oppose to each other through the discharge space, the plurality of row electrode pairs which are disposed on the side of one of the pair of substrates, the plurality of column electrodes which are disposed on the side of the other substrate so as to extend in the direction intersecting the row electrode pairs and which form the unit light emission regions in the discharge space at their respective parts intersecting the row electrode pairs, and the fluorophor layers which are disposed at the positions confronting the unit light emission regions between the column electrodes and the row electrode pairs, wherein the discharge gas is enclosed in the discharge space, the secondary electron emission material is contained in the fluorophor layers, and the secondary electron emission material is the magnesium oxide which contains the magnesium oxide crystals that have the characteristic of presenting the cathode luminescence light emission having the peak within the wavelength region of 200-300 nm, when excited by the electron beam.
In addition, the drive method for the above PDP according to this invention includes as the drive step, the step of impressing the voltage pulse on the row electrodes on one side, which constitute the row electrode pairs, and setting the potential of the column electrodes on the cathode side relatively to the row electrodes on one side, which have been impressed with the voltage pulse, whereby the opposed discharges are generated between the column electrodes and the row electrodes on one side, through the fluorophor layers.
In the PDP which is driven by the drive method, the fluorophor layers which are formed at the positions confronting the unit light emission regions contain the secondary electron emission material, and the opposed discharges are generated between the row electrodes on one side, in the row electrode pairs, and the column electrodes as are located with the fluorophor layers interposed therebetween, whereby at the generations of the discharges, cations produced from the discharge gas within the unit light emission regions collide against the secondary electron emission material contained in the fluorophor layers, and secondary electrons are emitted from the secondary electron emission material into the unit light emission regions.
Thus, discharges which proceed subsequently to the opposed discharges between the row electrodes on one side and the column electrodes become liable to be generated, by the secondary electrons existing within the unit light emission regions, and the discharge initiation voltage of the subsequent discharges is lowered.
Besides, in a case where the opposed discharges between the row electrodes on one side and the column electrodes are reset discharges for initializing all the unit light emission regions at the drive of the PDP, these opposed discharges are performed at substantially the central parts of the unit light emission regions spaced from that substrate of the pair of substrates which forms the panel face of the PDP. Therefore, light emissions based on the reset discharges as are recognized at the panel face become less than in a case where the reset discharges are performed by the surface discharges between the row electrodes at positions near the panel face. Accordingly, a dark contrast is prevented from lowering due to the light emissions which are based on the reset discharges and which have no relation to the gradation display of an image, and enhancement in the dark contrast of the PDP can be attained.
In addition, according to the drive method for the PDP described above, the opposed discharges between the row electrodes on one side and the column electrodes are generated in such a way that the voltage pulse is impressed on the row electrodes on one side, and that the potential of the column electrodes is set on the negative electrode side relatively to the row electrodes on one side, impressed with the voltage pulse. Thus, the cations produced from the discharge gas by the opposed discharges advance toward the column electrodes serving as the negative electrode side and collide against the secondary electron emission material contained in the fluorophor layers. Therefore, the secondary electrons are efficiently emitted from the secondary electron emission material into the unit light emission regions.
In the PDP and the drive method therefor, the secondary electron emission material should preferably be located at those parts in the fluorophor layers which confront the unit light emission regions.
Thus, the secondary electron emission material contained in the fluorophor layers collides against the cations efficiently, and the secondary electrons can be emitted into the unit light emission regions more efficiently.
In the PDP and the drive method therefor, aspects in which the secondary electron material is contained in the fluorophor layers include an aspect in which the secondary electron material is mixed with fluorescent materials constituting the fluorophor layers, an aspect in which the secondary electron material forms layers and are stacked on layers formed of the fluorescent materials constituting the fluorophor layers, and so forth.
In the PDP and the drive method therefor, magnesium oxide should preferably be used as the secondary electron emission material. Thus, the secondary electrons can be efficiently emitted from the fluorophor layers into the unit light emission regions.
Further, in the PDP and the drive method therefor, as the secondary electron material, it is favorable to use magnesium oxide which contains magnesium oxide crystals that have the characteristic of presenting a cathode luminescence light emission having a peak within a wavelength region of 200-300 nm, further within 230 nm-250 nm, when excited by an electron beam, especially magnesium oxide single crystals that have been produced by vapor phase oxidation.
Thus, the discharge strength and discharge delay of the opposed discharges between the row electrodes on one side and the column electrodes can be decreased, and the intensity of the PDP can be enhanced.
In the drive method for the PDP, the opposed discharges between the row electrodes on one side and the column electrodes should preferably be employed for the reset discharges for initializing the unit light emission regions.
Thus, the reset discharges are performed at substantially the central parts of the unit light emission regions spaced from that substrate of the pair of substrates which forms the panel face of the PDP.
Therefore, light emissions based on the reset discharges as are recognized at the panel face become less than in a case where the reset discharges are performed by the surface discharges between the row electrodes at positions near the panel face. Accordingly, a dark contrast is prevented from lowering due to the light emissions which are based on the reset discharges and which have no relation to the gradation display of an image, and enhancement in the dark contrast of the PDP can be attained. In the drive method for the PDP, it is favorable to impress a voltage pulse of positive polarity on the row electrodes on one side, and to impress a voltage pulse of negative polarity on the column electrodes or to hold the column electrodes at a ground potential.
Thus, so-called “cathode column electrode discharges” in which cations produced from the discharge gas by the discharges advance toward the column electrodes serving as the negative electrodes are generated between the row electrodes on one side and the column electrodes.
Besides, in the drive method for the PDP, it is favorable that simultaneously with the impression of the voltage pulse on the row electrodes on one side, a voltage pulse which is identical in polarity to the voltage pulse that is impressed on the row electrodes on one side and whose potential does not generate any potential that induces discharges between the row electrodes on one side and the row electrodes on the other side, constituting the row electrode pairs, is impressed on the row electrodes on the other side.
Thus, the discharges are prevented from being generated between the row electrodes of the row electrode pairs, and the opposed discharges can be reliably generated between the row electrodes on one side and the column electrodes.
Further, in the drive method for the PDP, the voltage pulse should preferably be impressed on the row electrodes on one side, in an aspect in which a voltage enlarges at a required increase rate since start of the impression.
Thus, the opposed discharges are generated in a state where the voltage at the rise of the voltage pulse is not considerably large, so that the discharge strength of the opposed discharges can be lowered.
This invention has for another object to provide a drive method for a plasma display panel as can heighten the representation capability of an intensity gradation in the case of displaying a dark image.
A drive method for a plasma display panel according to a third aspect of this invention consists in a drive method for a plasma display panel wherein a first substrate and a second substrate are arranged in opposition through a discharge space in which a discharge gas is enclosed, and pixel cells which contain fluorophor materials and a secondary electron emission material are formed at respective intersection parts between a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate, the plasma display panel being driven in accordance with pixel data of respective pixels based on a video signal. The method comprises a reset step of subjecting the pixel cells to reset discharges, thereby to initialize the pixel cells into states of one of a light-up mode and a light-off mode, and an address step of subjecting the pixel cells to address discharges selectively in accordance with the pixel data, thereby to shift the pixel cells into states of the other of the light-up mode and the light-off mode, the reset step and the address step being successively executed in each of at least a head subfield and a second subfield immediately after the head subfield in a case where a one-field display period in the video signal is divided into a plurality of subfields; wherein in the reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the reset discharges between the row electrodes on one side and the column electrodes.
Besides, a drive method for a plasma display panel according to a fourth aspect of this invention consists in a drive method for a plasma display panel wherein a first substrate and a second substrate are arranged in opposition through a discharge space in which a discharge gas is enclosed, and pixel cells are formed at respective intersection parts between a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate, the plasma display panel being driven in accordance with pixel data of respective pixels based on a video signal. The drive method comprises a first reset step of subjecting the pixel cells to reset discharges, thereby to initialize the pixel cells into states of a light-off mode, a first address step of subjecting the pixel cells to address discharges selectively in accordance with the pixel data, thereby to shift the pixel cells into states of a light-up mode, and a minute light emission step of subjecting the pixel cells being in the states of the light-up mode, to minute light emission discharges, the first reset step, the first address step and the minute light emission step being successively executed in a head subfield in a case where a one-field display period in the video signal is divided into a plurality of subfields; wherein in the first reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the reset discharges between the row electrodes on one side and the column electrodes; and in the minute light emission step, a voltage with the row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the minute light emission discharges between the column electrodes and the row electrodes on one side, within the pixel cells being in the states of the light-up mode.
Besides, a drive method for a plasma display panel according to a fifth aspect of this invention consists in a drive method for a plasma display panel wherein a first substrate and a second substrate are arranged in opposition through a discharge space in which a discharge gas is enclosed, and pixel cells are formed at respective intersection parts between a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate, the plasma display panel being driven in accordance with pixel data of respective pixels based on a video signal. The drive method comprises a reset step of subjecting the pixel cells to reset discharges, thereby to initialize the pixel cells into states of a light-off mode, and an address step of subjecting the pixel cells to address discharges selectively in accordance with the pixel data, thereby to shift the pixel cells into states of a light-up mode, the reset step and the address step being successively executed in each of at least a head subfield and a second subfield immediately after the head subfield, in a case where a one-field display period in the video signal is divided into a plurality of subfields; wherein in the reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the reset discharges between the row electrodes on one side and the column electrodes; and a potential which is applied to the row electrodes on one side in order to induce the reset discharges, in the reset step of the head subfield, is lower than a potential which is applied to the row electrodes on one side in order to induce the reset discharges, in the reset step of the second subfield.
Besides, a drive method for a plasma display panel according to a sixth aspect of this invention consists in a drive method for a plasma display panel wherein a first substrate and a second substrate are arranged in opposition through a discharge space in which a discharge gas is enclosed, and pixel cells are formed at respective intersection parts between a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate, the plasma display panel being driven in accordance with pixel data of respective pixels based on a video signal. The drive method comprises a reset step of subjecting the pixel cells to reset discharges, thereby to initialize the pixel cells into states of a light-off mode, and an address step of subjecting the pixel cells to address discharges selectively in accordance with the pixel data, thereby to shift the pixel cells into states of a light-up mode, the reset step and the address step being successively executed in each of at least a head subfield and a second subfield immediately after the head subfield, in a case where a one-field display period in the video signal is divided into a plurality of subfields; wherein in the reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the reset discharges between the row electrodes on one side and the column electrodes; and a potential which is applied to the row electrodes on the other side in the row electrode pairs, in the address step of the head subfield, is lower than a potential which is applied to the row electrodes on the other side, in the address step of the second subfield.
A plasma display panel in which pixel cells that contain fluorophor materials and a secondary electron emission material are formed at respective intersection parts between a plurality of column electrodes and a plurality of row electrode pairs, is driven as follows: A reset step in which all the pixel cells are caused to perform reset discharges, thereby to initialize the individual pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, thereby to shift the individual pixel cells into states of the other of the light-up mode and the light-off mode, are successively executed in each of a head subfield and a second subfield within a one-field display period. In each reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrode, whereby the reset discharges are induced between both the electrodes.
According to such a drive, at the reset discharges, cations within the discharge gas collide against the secondary electron emission material in advancing toward the side of the column electrodes, and they emit secondary electrons into the discharge space. The discharge initiation voltage of the pixel cells becomes low owing to a priming action based on such secondary electrons, and hence, comparatively weak reset discharges can be induced. Consequently, owing to the weak reset discharges, a light emission intensity involved in the discharges lowers, so that a display in which a dark contrast is enhanced can be presented. Further, the reset discharges are induced between the row electrodes on one side, formed on the side of the front transparent substrate and the column electrodes formed on the side of the rear substrate.
Therefore, discharge light which is externally emitted from the side of the front transparent substrate becomes less than in a case where the reset discharges are induced between the row electrodes both of which are formed on the side of the front transparent substrate, so that further enhancement in the dark contrast can be attained. Besides, immediately after the address step of the head subfield as stated above, a voltage with the row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between both the electrodes, thereby to induce minute light emission discharges between the column electrodes and the row electrodes on one side within the pixel cells being in the states of the light-up mode. Since the minute light emission discharges are generated between the row electrodes on one side, in the row electrode pairs formed on the side of the front transparent substrate and the column electrodes formed on the side of the rear substrate, a light emission intensity involved in the discharges is lower than in sustain discharges which are generated between the row electrodes formed on the side of the front transparent substrate. In other words, it is permitted to represent an intensity level which is lower than an intensity level that is visually recognized in a case where the sustain discharges are induced only once. Therefore, the intensity difference between gradations representing low intensities becomes smaller, so that a gradation representation capability in the case of representing a dark image is heightened.
A drive method for a plasma display panel according to a seventh aspect of this invention consists in a drive method for a plasma display panel wherein a first substrate and a second substrate are arranged in opposition through a discharge space in which a discharge gas is enclosed, and pixel cells which contain fluorophor materials and a secondary electron emission material are formed at respective intersection parts between a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate, the plasma display panel being driven in accordance with pixel data of respective pixels based on a video signal. The drive method comprises a reset step of subjecting the pixel cells to reset discharges, thereby to initialize the pixel cells into a light-off mode, and an address step of subjecting the pixel cells to address discharges selectively in accordance with the pixel data, thereby to set the pixel cells into a light-up mode, the reset step and the address step being executed in a head subfield in a case where a one-field display period in the video signal is divided into a plurality of subfields; wherein in the reset step, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, thereby to induce the reset discharges between the row electrodes on one side and the column electrodes.
A plasma display panel in which pixel cells that contain fluorophor materials and a secondary electron emission material are formed at respective intersection parts between a plurality of column electrodes and a plurality of row electrode pairs, is driven as follows: In a head subfield within a one-field display period, a voltage with row electrodes on one side, in the row electrode pairs set as an anode side and the column electrodes set as a cathode side is applied between the row electrodes on one side and the column electrodes, whereby reset discharges for initializing all the pixel cells into a light-off mode are induced between the column electrodes and the row electrodes within all the pixel cells.
According to such a drive, at the reset discharges, cations within the discharge gas collide against the secondary electron emission material in advancing toward the side of the column electrodes, and they emit secondary electrons into the discharge space. The discharge initiation voltage of the pixel cells becomes low owing to a priming action based on such secondary electrons, and comparatively weak reset discharges can be induced. Consequently, owing to the weak reset discharges, a light emission intensity involved in the discharges lowers, so that a display in which a dark contrast is enhanced can be presented. Further, the reset discharges are induced between the row electrodes on one side, formed on the side of the front transparent substrate and the column electrodes formed on the side of the rear substrate. Therefore, discharge light which is externally emitted from the side of the front transparent substrate becomes less than in a case where the reset discharges are induced between the row electrodes both of which are formed on the side of the front transparent substrate. Accordingly, further enhancement in the dark contrast can be attained.
As shown in
The PDP 50 is formed with column electrodes D1-Dm which are respectively extended and arrayed in the vertical direction of a two-dimensional display screen, and row electrodes X1-Xn and row electrodes Y1-Yn which are respectively extended and arrayed in the lateral direction (horizontal direction). In this case, row electrode pairs in which the row electrodes adjacent to each other are paired; (Y1, X1), (Y2, X2), (Y3, X3), . . . , and (Yn, Xn) bear a first display line—an n th display line in the PDP 50, respectively. Pixel cells PCs bearing pixels are formed at the intersection parts between the respective display lines and the column electrodes D1-Dm (regions enclosed with dot-and-dash lines in
As shown in
A magnesium oxide layer 13 is formed on the surface of the dielectric layer 12 including the raised dielectric layers 12A. Incidentally, the magnesium oxide layer 13 contains magnesium oxide crystals being a secondary electron emission material which presents CL (cathode-luminescence) emission having a wavelength peak within 200-300 nm, especially within 230-250 nm, when excited by irradiation with an electron beam (hereinbelow, the crystals shall be termed the “CL emission MgO crystals”).
The CL emission MgO crystals are obtained in such a way that magnesium vapor generated by heating magnesium is subjected to vapor-phase oxidation as will be stated later. These CL emission MgO crystals have, for example, a multiple crystal structure in which cubic crystals are fitted into one another, or a cubic single-crystal structure. The mean grain diameter of the CL emission MgO crystals is at least 2000 angstroms (as a measured result based on the BET method).
In a case where the vapor-phase magnesium oxide single crystals of large grain diameters, having the mean grain diameter of at least 2000 angstroms are to be formed, a heating temperature in the case of generating the magnesium vapor needs to be heightened. Therefore, flames in which the magnesium and oxygen react become long, and the difference between the temperatures of the flames and the surroundings becomes large. Thus, as the vapor-phase magnesium oxide single crystals have larger grain diameters, more crystals whose energy levels correspond to the peak wavelength of the CL emission as mentioned above (for example, near 235 nm or within 230-250 nm) are formed.
Besides, the vapor-phase magnesium oxide single crystals which are produced in such a way that the quantity of the magnesium to be vaporized per unit time is increased more than in a general vapor-phase oxidation method so as to more enlarge the reaction region between the magnesium and the oxygen and to react the magnesium with more oxygen, come to have the energy levels which correspond to the peak wavelength of the CL emission as mentioned above. Such CL emission MgO crystals are stuck onto the surface of the dielectric layer 12 by spraying, electrostatic coating, or the like, whereby the magnesium oxide layer 13 is formed. Incidentally, the magnesium oxide layer 13 may well be formed in such a way that a thin-film magnesium oxide layer is formed on the surface of the dielectric layer 12 by evaporation or sputtering, and that the CL emission MgO crystals are stuck thereonto.
On the other hand, on a rear substrate 14 which is arranged in parallel with the front transparent substrate 10, the respective column electrodes D are formed extending in a direction orthogonal to the row electrode pairs (X, Y), at positions which oppose to the transparent electrodes Xa and Ya in the respective row electrode pairs (X, Y). A column electrode protective layer 15 in white as covers the column electrodes D, are further formed on the rear substrate 14. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 is formed in a ladder shape, out of lateral walls 16A which are respectively extended in the lateral direction of the two-dimensional display screen at positions corresponding to the bus electrodes Xb and Yb of the row electrode pairs (X, Y), and vertical walls 16B which are respectively extended in the vertical direction of the two-dimensional display screen at the intermediate positions between the row electrodes D adjacent to each other. Further, the ladder-shaped partition wall 16 as shown in
Here, the interspace between the discharge space S of each pixel cell PC and the spacing SL is closed in such a way that, as shown in
In addition, the discharge spaces S between the front glass substrate 10 and the rear glass substrate 14 are partitioned into squares in the respective parts where the transparent electrodes Xa and Ya paired in the row electrode pairs (X, Y), by the ladder-shaped partition wall 16, whereby discharge cells C are respectively formed. The side surfaces of the lateral wall 16A and vertical wall 16B of the partition wall 16 and the surface of the column electrode protective layer 15 as confront the discharge cell C are formed with the fluorophor layer 17 so that all the five surfaces may be covered therewith. The fluorophor layers 17 are arrayed so that the three primary colors of red, green and blue may be successively presented in the row direction for the respective discharge cells C.
Referring to
In
Besides, the MgO crystals 17B may be in any form as long as they have the characteristic of emitting secondary electrons. These MgO crystals 17B, however, should preferably contain CL emission MgO crystals which have the characteristic of presenting CL emission with a peak within a wavelength region of 200-300 nm, when excited by an electron beam, and which are similar to the CL emission MgO crystals forming the magnesium oxide layer 13 stated before.
The CL emission MgO crystals contain the single crystals of magnesium obtained, for example, in such a way that magnesium vapor generated by heating the magnesium is subjected to vapor-phase oxidation (hereinbelow, the single crystals of the magnesium shall be termed the “vapor-phase magnesium oxide single crystals”). The vapor-phase magnesium oxide single crystals include, for example, magnesium oxide single crystals having a cubic single-crystal structure, as shown by a SEM photographic image in
As will be described later, the vapor-phase magnesium oxide single crystals contribute to the betterments of discharge characteristics, such as the decrease of the discharge delay of the PDP.
In addition, when compared with magnesium oxide produced by another method, the vapor-phase magnesium oxide single crystals have the features that a high purity is attained, that fine grains are obtained, and that the aggregation of the grains is little.
In this embodiment, the vapor-phase magnesium oxide single crystals whose mean grain diameter measured by the BET method is at least 2000 angstroms are employed. The vapor-phase magnesium oxide single crystals of the large grain diameters exhibit characteristics in which, in addition to CL emission having a peak within a wavelength region of 300-400 nm, CL emission having a peak within a wavelength region of 200-300 nm (especially, near 235 nm or within 230-250 nm) is excited.
As shown in
Besides, as seen in
Incidentally, the grain diameter (DBET) of the vapor-phase magnesium oxide single crystal is calculated in such a way that a BET specific surface area (s) is measured by the nitrogen adsorption method, and that the value of the specific surface area is processed in conformity with the following formula:
DBET=A/s×ρ
A: shape coefficient (A=6)
ρ: true density of magnesium
It is seen from
It is understood from the foregoing that, when the vapor-phase magnesium oxide single crystals having the mean grain diameter of at least 2000 angstroms as the measured value based on the BET method are used for the part confronting the discharge cell of the PDP, they can contribute to the betterments of the discharge characteristics such as the discharge probability and discharge delay of the PDP (to the decrease of the discharge delay and the enhancement of the discharge probability).
Further,
Incidentally,
It is seen from
It is seen from
The reason why, as described above, the vapor-phase magnesium oxide single crystals which present the CL emission having the peak within the wavelength region of 200-300 nm (especially, near 235 nm or within 230-250 nm) contribute to the betterments of the discharge characteristics of the PDP, is conjectured to be the fact that the vapor-phase magnesium oxide single crystals have energy levels corresponding to the peak wavelength, that electrons can be trapped for a long time (several msec or longer) by the energy levels, and that the electrons are taken out by an electric field, whereby initial electrons necessary for discharge initiation are obtained.
In addition, the reason why the betterment effects of the discharge characteristics by the vapor-phase magnesium oxide single crystals becomes greater with the intensity of the CL emission having the peak within the wavelength region of 200-300 nm (especially, near 235 nm or within 230-250 nm), is that the correlation (refer to
More specifically, in the case where the vapor-phase magnesium oxide single crystals of large grain diameters are to be formed, the heating temperature at the step of generating the magnesium vapor needs to be heightened. Therefore, the flames in which the magnesium and the oxygen react become long, and the difference between the temperatures of the flames and the surroundings become large, whereby the energy levels corresponding to the peak wavelength of the CL emission as stated above (for example, near 235 nm or within 230-250 nm) are formed in larger numbers in the vapor-phase magnesium oxide single crystals of larger grain diameters.
Besides, the vapor-phase magnesium oxide single crystals produced by the method in which the vaporization quantity of the Mg per unit time is increased more than in the general vapor-phase oxidation method, thereby to more enlarge the reaction region between the Mg and the O2 and to react the Mg with more O2, are formed with the energy levels corresponding to the peak wavelength of the CL emission as stated before.
Besides, the vapor-phase magnesium oxide single crystals of the cubic multiple crystal structure contain a large number of crystal face defects. The existence of the energy levels of the face defects is conjectured to contribute to the betterment of the discharge probability. Next, a drive method for the PDP shown in
The PDP is driven by the subfield method. Each of a plurality of subfields into which the display period of one field is divided is configured of a reset discharge period in which a reset discharge for simultaneously discharging all the discharge cells is performed, an address discharge period in which an address discharge for selecting the discharge cell C to emit light is performed, and a sustain discharge period in which a sustain discharge for emitting the light for image formation is performed. Besides, in the PDP, the reset discharge which is performed in the first reset discharge period of each subfield is carried out by opposed discharges between row electrodes Y and column electrodes D.
Referring to
Owing to the impressions of the column electrode reset pulse Rd of the negative polarity and the row electrode reset pulse Ry of the positive polarity, discharges in a direction from the row electrodes Y to the address electrodes D (electrons flow in a direction from the column electrodes D to the row electrodes Y) are generated between the column electrodes D serving as cathodes and the row electrodes Y serving as anodes (hereinbelow, the discharges which are generated with the column electrodes D set as the cathodes and the row electrodes Y set as the anodes shall be generally termed the “cathode column electrode discharge”). Incidentally, “SP” in
In the PDP, the reset discharge is performed by the cathode column electrode discharge between the row electrodes Y and the column electrodes D which oppose with the discharge cells C interposed therebetween. Thus, cations within the discharge cells C as are produced from the discharge gas by the discharges proceed onto the sides of the column electrodes D being the cathodes, at the time of the reset discharge, and they collide against the MgO crystals 17B being the secondary electron emission material as are mixed within the fluorophor layer 17 located on the sides of the column electrodes D, whereby secondary electrons are emitted from the MgO crystals 17B into the discharge cells C.
In this way, the address discharge which is performed in the address discharge period succeeding to the reset discharge period becomes liable to occur owing to the secondary electrons existent within the discharge cells C, and the discharge initiation voltage of the address discharge can be lowered.
The MgO crystals 17B are exposed on the surface of the fluorophor layer 17, thereby to efficiently collide against the cations and to emit the secondary electrons into the discharge cells C more efficiently, so that the discharge initiation voltage of the succeeding address discharge can be lowered.
Further, in general, in a PDP, also reset discharge incurs light emissions. The light emissions ascribable to the reset discharge have no relation to the gradation display of an image. Therefore, when the light emissions ascribable to the reset discharge are recognized at a panel face in case of displaying an image of intensity “0”, or the like, the dark contrast of the image lowers. In contrast, in the PDP of the embodiment, the reset discharge is performed by the opposed discharges between the row electrodes Y and the column electrodes D, and the opposed discharges occur at the central parts of the discharge cells C spaced from the panel face (the surface of the front glass substrate 10). Accordingly, when the PDP of the embodiment is compared with the case where the reset discharge is performed by the surface discharges between row electrodes at positions near the panel face, the light emissions ascribable to the reset discharge as are recognized at the panel face become less, so that the dark contrast of the image to be displayed can be enhanced.
In the above, the example (
In the ensuing description, the cathode column electrode discharge shall cover all the cases where the column electrodes D have its potential set as the cathode sides relatively to the row electrodes Y on the occasion of the reset discharge, such as the case where the column electrodes D are set at the ground (GND) potential, and the case where the positive-polarity voltage pulse which is lower in potential than the row electrode reset pulse Ry is impressed on the column electrodes D.
Besides, on the occasion of the reset discharge, the row electrodes X which form the row electrode pairs with the row electrodes Y may well hold the ground (GND) potential during the reset discharge period. As shown in
Thus, while the reset discharge proceeds, the potential difference which generates the discharges between the row electrodes X and Y forming the row electrode pairs is prevented from appearing, and the reset discharge can be reliably performed as only the opposed discharges between the row electrodes Y and the column electrodes D. Accordingly, the dark contrast of the display image can be further enhanced.
In the PDP, in a case where the MgO crystals 17B mixed in the fluorophor layer 17 contain the CL emission MgO crystals of the characteristic which presents the CL emission having the peak within the wavelength region of 200-300 nm, when excited by the electron beam, as stated before, the discharge delay time is shortened more by the characteristics of the CL emission MgO crystals as have been explained in conjunction with
Further, with the PDP, in the case where the CL emission MgO crystals are contained in the MgO crystals 17B and are mixed in the fluorophor layer 17, initial electrons are emitted from the CL emission MgO crystals within the fluorophor layer 17 into the discharge cells C by the reset discharge, and the discharge delay of the reset discharge is more shortened by the initial electrons. Also, the priming effect is continued for long, so that the address discharge which is generated subsequently to the reset discharge is further quickened.
In addition, with the PDP, as shown in
Incidentally, regarding the axes of abscissas (times) in
When
The reason why the discharge strength lowers in
The axis of abscissas in
Here, numerical values which indicate the discharge delay on the axis of ordinates in
It is seen from
As described above, it is understood from
Incidentally, a similar measurement was performed for a PDP in which only the ordinary MgO crystals not being the CL emission MgO crystals were mixed into a fluorophor layer in the state of
The reason therefor is conjectured as follows: The ordinary MgO crystals not being the CL emission MgO crystals have the function of emitting secondary electrons, but they do not have the energy levels corresponding to the peak wavelength region of 230 to 250 nm as in the CL emission MgO crystals. Therefore, the ordinary MgO crystals will be incapable of trapping the electrons for a long time, and hence, they will be incapable of obtaining sufficient initial electrons which are taken out into a discharge space at the impression of a voltage pulse.
Since the PDP shown in
More specifically, in the sustain discharge period of each subfield, sustain discharges based on surface discharges are generated between the row electrodes X and Y of the row electrode pairs, within the discharge cells C selected by the address discharges performed by the preceding address discharge period. Vacuum ultraviolet radiations of 146 nm and 172 nm are generated from xenon in the discharge gas by the sustain discharges, and the CL emission MgO crystals in the fluorophor layer 17 are excited by the vacuum ultraviolet radiations, to present the PL emission (photoluminescence emission), whereby the ultraviolet radiation having its peak within 230-250 nm (hereinbelow, termed the “PL ultraviolet radiation”) is generated.
In addition, the fluorescent materials 17A in the fluorophor layer 17 are further excited by the PL ultraviolet radiation, so that the intensity of the PDP is enhanced more than in the case where only the ordinary MgO crystals are mixed in the fluorophor layer.
The intensity enhancement effect of the PDP as stated above is demonstrated in the case where the CL emission MgO crystals are contained as the MgO crystals 17B and are mixed in the fluorophor layer 17, for reasons described below.
In general, MgO crystals have the characteristic of absorbing the vacuum ultraviolet radiations generated from the xenon in the discharge gas by the discharge, without transmitting them. Therefore, in the case where, for example, only the ordinary MgO crystals not being the CL emission MgO crystals are mixed in the fluorophor layer, these MgO crystals absorb the vacuum ultraviolet radiations generated from the xenon of the discharge gas, and the quantities of the vacuum ultraviolet radiations to irradiate fluorophor grains around the MgO crystals decrease, so that the intensity of the PDP becomes lower than in a case where the fluorophor layer 17 is formed of only the fluorescent materials.
In contrast, in the case where the CL emission MgO crystals are contained as the MgO crystals 17B and are mixed in the fluorophor layer 17, the CL emission MgO crystals absorb the vacuum ultraviolet radiations generated from the xenon in the discharge gas and thereafter present the PL emission by the vacuum ultraviolet radiations, thereby to radiate the PL ultraviolet radiation having its peak wavelength within the wavelengths of 230-250 nm.
In addition, the PL ultraviolet radiation excites the fluorescent materials 17A in the fluorophor layer 17 so as to fluoresce. Therefore, it is not apprehended that, as stated above, the intensity will be lowered by mixing only the ordinary MgO crystals in the fluorophor layer 17. Besides, the fluorescent materials 17A of the fluorophor layer 17 are excited, not only by the vacuum ultraviolet radiations generated from the xenon of the discharge gas, but also by the PL ultraviolet radiation generated from the CL emission MgO crystals. Therefore, the quantity of visible light generated from the fluorophor layer 17 increases the intensity of the PDP sharply as compared with that in the case where the mixed MgO crystals 17B consist only of the ordinary MgO crystals other than the CL emission MgO crystals.
Further, the CL emission MgO crystals are mixed with the fluorescent materials 17A within the fluorophor layer 17 and are located near by the fluorophor grains. Therefore, the fluorescent materials 17A are efficiently irradiated with the PL ultraviolet radiation generated from the CL emission MgO crystals, and the intensity of the PDP is further increased.
In the above, there has been described the example in which the row electrode reset pulse which is impressed on the row electrodes Y at the reset discharge is the voltage pulse in the aspect in which the pulse voltage thereof is smoothly increased while changing the gradient of the rise thereof, as shown in
Also in this case, it is possible to attain substantially the same effect of the enhancement of the dark contrast as in the case where the row electrode reset pulse is set as the voltage pulse in the aspect as shown in
Besides, in a case where, as in the case of
Thus, the reset discharge can be reliably generated only between the row electrodes Y and the column electrodes D.
In the above, the configuration in which the reset discharge proceeds between the row electrodes Y and the column electrodes D has been described by mentioning the examples. The PDP, however, may well be so configured that a row electrode reset pulse is impressed on the row electrodes X, and that the reset discharge proceeds between the row electrodes X and the column electrodes D.
The fluorophor layer of the PDP of the first embodiment described before is formed by mixing the fluorescent materials and the MgO crystals which are the secondary electron emission material. In contrast, the PDP in the second embodiment is such that a fluorophor layer 17 has a configuration in which an MgO crystal layer 17B that is formed of MgO crystals being a secondary electron emission material is stacked on a fluorescent material layer 17A that is formed of a fluorescent material, and in which the MgO crystal layer 17B is exposed to a discharge cell C.
The MgO crystal layer 17B may be formed so as to spread the MgO crystals all over the fluorescent material layer 17A. Alternatively, a thin film based on the MgO crystals may well be formed so as to be stacked on the fluorescent material layer 17A.
In a case where CL emission MgO crystals are employed and contained as the secondary electron emission material forming the MgO crystal layer 17B, this MgO crystal layer 17B is formed in such a way that the CL emission MgO crystals are spread all over the fluorescent material layer 17A.
The configurations of the other portions of the PDP are substantially the same as in the case of the first embodiment, and numerals and signs identical to those in the case of the first embodiment are assigned to the same constituent portions.
The PDP is driven by a method similar to that in the case of the first embodiment.
More specifically, a reset discharge proceeds in such a way that the row electrode reset pulse in the aspect as shown in
Thus, as in the case of the first embodiment, the effect of enhancing the dark contrast of the PDP is demonstrated by the opposed discharges of the reset discharge, and the effect of lowering the discharge initiation voltage of an address discharge to succeed to the reset discharge is demonstrated by secondary electrons which are emitted from the MgO crystal layer 17B into the discharge cells C by the reset discharge.
Besides, in the case where the MgO crystal layer 17B is formed containing the CL emission MgO crystals, the dark contrast can be further enhanced by the shortening of a discharge delay and the decrease of a discharge strength as in the case of the first embodiment. Simultaneously, the CL emission MgO crystals present PL emission (photoluminescence emission) by vacuum ultraviolet radiations which are generated from xenon in a discharge gas, thereby to generate PL ultraviolet radiation, and this PL ultraviolet radiation further excites the fluorescent material layer 17A of the fluorophor layer 17 so as to fluoresce, so that the intensity of the PDP can be increased.
The PDP in each of the embodiments has as its high-level concept, a PDP including a pair of substrates which oppose through a discharge space, a plurality of row electrode pairs which are disposed on the side of one of the pair of substrates, a plurality of column electrodes which are disposed on the side of the other substrate so as to extend in a direction intersecting the row electrode pairs and which form unit light emission regions at the parts of the discharge space intersecting the row electrode pairs, respectively, and fluorophor layers which are disposed at positions confronting the unit light emission regions between the column electrodes and the row electrode pairs, wherein a discharge gas is enclosed within the discharge space, a secondary electron emission material is contained in each of the fluorophor layers, and the secondary electron emission material is magnesium oxide which contains magnesium oxide crystals having the characteristic of being excited by an electron beam and presenting cathode-luminescence emission with a peak within a wavelength region of 200-300 nm. The drive method for a PDP in each of the embodiments has as its high-level concept, a drive method for the PDP, in which a drive step includes a step that impresses a voltage pulse on either-side row electrodes constituting the row electrode pairs, and that sets a potential of the column electrodes onto a negative polarity side relatively to the either-side row electrodes impressed with the voltage pulse, whereby opposed discharges are generated with the fluorophor layers interposed between the column electrodes and the either-side row electrodes.
According to the PDP in this embodiment, the fluorophor layer formed at the position confronting the corresponding unit light emission region contains the secondary electron emission material, and the opposed discharge is generated between either row electrode of the pair of row electrodes located with the fluorophor layer interposed therebetween and the corresponding column electrode, whereby cations produced from the discharge gas within the unit light emission region at the generation of the discharge collide against the secondary electron emission material contained in the fluorophor layer, and secondary electrons are emitted from the secondary electron emission material into the unit light emission region.
Thus, a discharge which is performed subsequently to the opposed discharge between the either row electrode and the column electrode becomes liable to occur owing to the secondary electrons existing within the unit light emission region, and the discharge initiation voltage of the subsequent discharge is lowered.
Besides, in a case where the opposed discharges proceeding between the either-side row electrodes and the column electrodes serves as a reset discharge for initializing all the unit light emission regions at the drive of the PDP, these opposed discharges are performed at substantially the central parts of the unit light emission regions spaced from that substrate of the pair of substrates which forms the panel face of the PDP. Therefore, light emissions based on the reset discharge as are recognized at the panel face become less than in a case where the reset discharge is performed by the surface discharges between the row electrodes at positions near the panel face. Accordingly, a dark contrast is prevented from lowering due to the light emissions which are based on the reset discharge and which have no relation to the gradation display of an image, and enhancement in the dark contrast of the PDP can be attained.
In addition, according to the drive method for the PDP in the embodiment, the opposed discharges between the either-side row electrodes and the column electrodes are generated in such a way that the voltage pulse is impressed on the either-side row electrodes, and that the potential of the column electrodes is set on the negative electrode side relatively to the either-side row electrodes impressed with the voltage pulse. Thus, the cations produced from the discharge gas by the opposed discharges advance toward the column electrodes serving as the negative electrode side and collide against the secondary electron emission material contained in the fluorophor layers. Therefore, the secondary electrons are efficiently emitted from the secondary electron emission material into the unit light emission regions.
Other embodiments of this invention will be further described with reference to the drawings. Referring to
Further, the drive control circuit 56 feeds various control signals for driving the PDP 50 of the above structure in accordance with a light emission drive sequence as shown in
The panel driver, namely, the X-electrode driver 51, Y-electrode driver 53 and address driver 55 generate(s) various drive pulses as shown in
In
First of all, in the first half part of the first reset step R1 of the subfield SF1, the Y-electrode driver 53 impresses on all the row electrodes Y1-Yn, a reset pulse RP1Y1 of positive polarity in a waveform in which a potential transition at a leading edge with the lapse of time is gentler than in a sustain pulse to be stated later. Incidentally, the peak potential of the reset pulse RP1Y1 is higher than that of the sustain pulse, and it is lower than that of a reset pulse RP2Y1 to be stated later. Besides, meantime, the address driver 55 sets the column electrodes D1-Dm in the state of ground potential (0 volt). Further, meantime, the X-electrode driver 51 impresses on all the row electrodes X1-Xn, a reset pulse RP1X which is identical in polarity to such a reset pulse RP1Y1 and whose peak potential capable of preventing surface discharges between the row electrodes X and Y as are induced by the impression of the reset pulse RP1Y1. Incidentally, meantime, insofar as the surface discharges are not generated between the row electrodes X and Y, the X-electrode driver 51 may well set all the row electrodes X1-Xn at the ground potential (0 volt), instead of the impression of the reset pulse RP1X. Here, in the first half part of the first reset step R1, first reset discharges being weak are induced between the row electrodes Y and the column electrodes D within all the pixel cells PC, in accordance with the impression of the reset pulse RP1Y1 as stated above. That is, in the first half part of the first reset step R1, a voltage is applied between the row electrodes Y and the column electrodes D with the former electrodes Y held as an anode side and the latter electrodes D held as a cathode side, whereby discharges in which currents flow from the row electrodes Y toward the column electrodes D (hereinbelow, the “column side cathode discharges”) are induced as the first reset discharges. In accordance with such first reset discharges, wall charges of negative polarity and wall charges of positive polarity are respectively formed in the vicinities of the row electrodes Y and in the vicinities of the column electrodes D within all the pixel cells PC.
Subsequently, in the latter half part of the first reset step R1 of the subfield SF1, the Y-electrode driver 53 generates a reset pulse RP1Y2 of negative polarity in which a potential transition at a leading edge with the lapse of time is gentle, and it impresses the reset pulse RP1Y2 on all the row electrodes Y1-Yn. Incidentally, a negative peak potential in the reset pulse RP1Y2 is set at a potential which is higher than the peak potential of a write scan pulse SPW of negative polarity to be stated later, that is, at a potential which is near 0 volt. The reason therefor is that, when the peak potential of the reset pulse RP1Y2 is made lower than that of the write scan pulse SPW, strong discharges are induced between the row electrodes Y and the column electrodes D, to sharply erase the wall charges having been formed in the vicinities of the column electrodes D, so address discharges in a first selective write address step W1W become unstable. Meantime, the X-electrode driver 51 sets all the row electrodes X1-Xn at the ground potential (0 volt). Incidentally, the peak potential of the reset pulse RP1Y2 is the lowest potential which can reliably induce second reset discharges between the row electrodes X and Y, in consideration of the wall charges which have been formed in the vicinities of the row electrodes X and Y in accordance with the first reset discharges. Here, in the latter half part of the first reset step R1, the second reset discharges are induced between the row electrodes X and Y within all the pixel cells PC, in accordance with the impression of the reset pulse RP1Y2 as stated above. Owing to the second reset discharges, the wall charges having been formed in the vicinities of the row electrodes X and Y within the respective pixel cells PC are erased, whereby all the pixel cells PC are initialized into a light-off mode. Further, weak discharges are induced also between the row electrodes Y and the column electrodes D within all the pixel cells PC, in accordance with the impression of the reset pulse RP1Y2. Owing to the weak discharges, some of the wall charges of positive polarity having been formed in the vicinities of the column electrodes D are erased, and the wall charges are adjusted into quantities in which selective write address discharges can be properly induced in the first selective write address step W1W to be stated later.
Subsequently, in the first selective write address step W1W of the subfield SF1, the Y-electrode driver 53 impresses the write scan pulse SPW having the peak potential of negative polarity, on the row electrodes Y1-Yn successively and selectively, while impressing a base pulse BP− which has a predetermined base potential of negative polarity as shown in
Subsequently, in the minute light emission step LL of the subfield SF1, the Y-electrode driver 53 impresses a minute light emission pulse LP having a predetermined peak potential of positive polarity as shown in
Incidentally, after the minute light emission discharges, wall charges of negative polarity and wall charges of positive polarity are respectively formed in the vicinities of the row electrodes Y and in the vicinities of the column electrodes D.
Subsequently, in the first half part of the second reset step R2 of the subfield SF2, the Y-electrode driver 53 impresses on all the row electrodes Y1-Yn, the reset pulse RP2Y1 of positive polarity in a waveform in which a potential transition at a leading edge with the lapse of time is gentler than in the sustain pulse to be stated later. Incidentally, the peak potential of the reset pulse RP2Y1 is higher than that of the reset pulse RP1Y1. Besides, meantime, the address driver 55 sets the column electrodes D1-Dm, into states of ground potential (0 volt), and the X-electrode driver 51 impresses on all the row electrodes X1-Xn, a reset pulse RP2X of positive polarity which has a peak potential capable of preventing surface discharges between the row electrodes X and Y as are generated by the impression of the reset pulse RP2Y1. Incidentally, insofar as the surface discharges are not generated between the row electrodes X and Y, the X-electrode driver 51 may well set all the row electrodes X1-Xn at the ground potential (0 volt), instead of impressing the reset pulse RP2X. In accordance with the impression of the reset pulse RP2Y1, the first reset discharge weaker than the column side cathode discharge in the minute light emission step LL is induced between the row electrode Y and the column electrode D within each of the pixel cells PC in which the column side cathode discharges have not been induced in such a minute light emission step LL. That is, in the first half part of the second reset step R2, a voltage is applied between the row electrodes Y and the column electrodes D with the former electrodes Y held as an anode side and the latter electrodes D held as a cathode side, whereby column side cathode discharges in which currents flow from the row electrodes Y toward the column electrodes D are induced as the first reset discharges. On the other hand, discharges are not induced in spite of the impression of the reset pulse RP2Y1, within the pixel cells PC in which the minute light emission discharges have already been induced in the minute light emission step LL. Accordingly, immediately after the end of the first half part of the second reset step R2, there is established a state where wall charges of negative polarity and wall charges of positive polarity are respectively formed in the vicinities of the row electrodes Y and in the vicinities of the column electrodes D within all the pixel cells PC. Subsequently, in the latter half part of the second reset step R2 of the subfield SF2, the Y-electrode driver 53 impresses on the row electrodes Y1-Yn, a reset pulse RP2Y2 of negative polarity in which a potential transition at a leading edge with the lapse of time is gentle. Further, in the latter half part of the second reset step R2, the X-electrode driver 51 impresses a base pulse BP+ having a predetermined base potential of positive polarity, on the respective row electrodes X1-Xn. In this process, in accordance with the impressions of the reset pulse RP2Y2 of the negative polarity and the base pulse BP+ of the positive polarity, second reset discharges are induced between the row electrodes X and Y within all the pixel cells PC. Incidentally, the peak potential of each of the reset pulse RP2Y2 and the base pulse BP+ is the lowest potential which can reliably induce the second reset discharges between the row electrodes X and Y, in consideration of the wall charges which have been formed in the vicinities of the row electrodes X and Y in accordance with the first reset discharges. Besides, a negative peak potential in the reset pulse RP2Y2 is set at a potential which is higher than the peak potential of the write scan pulse SPW of negative polarity, that is, at a potential which is near 0 volt. The reason therefor is that, when the peak potential of the reset pulse RP2Y2 is made lower than that of the write scan pulse SPW, strong discharges are induced between the row electrodes Y and the column electrodes D, to sharply erase the wall charges having been formed in the vicinities of the column electrodes D, so address discharges in a second selective write address step W2W become unstable. Here, owing to the second reset discharges induced in the latter half part of the second reset step R2, the wall charges having been formed in the vicinities of the row electrodes X and Y within the respective pixel cells PC are erased, whereby all the pixel cells PC are initialized into the light-off mode. Further, weak discharges are induced also between the row electrodes Y and the column electrodes D within all the pixel cells PC, in accordance with the impression of the reset pulse RP2Y2. Owing to such discharges, some of the wall charges of positive polarity having been formed in the vicinities of the column electrodes D are erased, and the wall charges are adjusted into quantities in which selective write address discharges can be properly induced in the second selective write address step W2W.
Subsequently, in the second selective write address step W2W of the subfield SF2, the Y-electrode driver 53 impresses the write scan pulse SPW having the peak potential of negative polarity, on the row electrodes Y1-Yn successively and selectively, while impressing the base pulse BP− which has the predetermined base potential of negative polarity as shown in
Subsequently, in the sustain step I of the subfield SF2, the Y-electrode driver 53 generates one pulse of the sustain pulse IP having a peak potential of positive polarity, and it impresses the pulse on the row electrodes Y1-Yn simultaneously. Meantime, the X-electrode driver 51 sets the row electrodes X1-Xn into states of ground potential (0 volt), and the address driver 55 sets the column electrodes D1-Dm into states of the ground potential (0 volt). In accordance with the impression of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y within the pixel cell PC set in the light-up mode as stated above. Light radiated from the fluorophor layer 17 simultaneously with such a sustain discharge is radiated outside the display panel device through the front transparent substrate 10, whereby one time of display light emission corresponding to the intensity weight of the subfield SF1 is done. Besides, in accordance with the impression of such a sustain pulse IP, a discharge is generated also between the row electrode Y and the column electrode D within the pixel cell PC set in the light-up mode. Owing to such a discharge and the sustain discharge, wall charges of negative polarity are formed in the vicinity of the row electrode Y within the pixel cell PC, and wall charges of positive polarity are respectively formed in the vicinities of the row electrode X and the column electrode D. In addition, after the impression of such a sustain pulse IP, the Y-electrode driver 53 impresses on the row electrodes Y1-Yn, a wall-charge adjustment pulse CP which has a peak potential of negative polarity and in which a potential transition at a leading edge with the lapse of time is gentle as shown in
Subsequently, in the sustain step I of each of the subfields SF3-SF14, the X-electrode driver 51 and the Y-electrode driver 53 impress a sustain pulse IP having a peak potential of positive polarity, on the row electrodes X1-Xn and Y1-Yn, alternately on the row electrodes X and Y and repeatedly the number of times (even number of times) corresponding to the intensity weight of the pertinent subfield, as shown in
In addition, after the end of the sustain step I of the final subfield SF14, the Y-electrode driver 53 impresses an erase pulse EP having a peak potential of negative polarity, on all the row electrodes Y1-Yn. In accordance with the impression of such an erase pulse EP, an erase discharge is induced only in the pixel cell PC being in the light-up mode state. Owing to such an erase discharge, the pixel cell PC having been in the light-up mode state is shifted into the state of the light-off mode.
The drive as described above is executed on the basis of the sixteen sorts of pixel drive data GD as shown in
First of all, at a second gradation which represents an intensity that is one intensity level higher than a first gradation representing a black display (intensity level 0), the selective write address discharge for setting the pixel cell PC into the light-up mode is induced only in the subfield SF1 among the subfields SF1-SF14 as shown in
Subsequently, at a third gradation which represents an intensity that is one intensity level higher than such a second gradation, the selective write address discharge for setting the pixel cell PC into the light-up mode is induced only in the subfield SF2 among the subfields SF1-SF14 (indicated by a double circle), and the selective erase address discharge for shifting the pixel cell PC into the light-off mode is induced in the next subfield SF3 (indicated by a black circle). At the third gradation, therefore, a light emission generated by one time of sustain discharge is done only in the sustain step I of the subfield SF2 among the subfields SF1-SF14, and the intensity corresponding to the intensity level “1” is represented.
Subsequently, at a fourth gradation which represents an intensity that is one intensity level higher than such a third gradation, in the first subfield SF1, the selective write address discharge for setting the pixel cell PC into the light-up mode is induced, and the pixel cell PC set in the light-up mode is caused to generate the minute light emission discharge (indicated by the square). Further, at such a fourth gradation, the selective write address discharge for setting the pixel cell PC into the light-up mode is induced in only the subfield SF2 among the subfields SF1-SF14 (indicated by the double circle), and the selective erase address discharge for shifting the pixel cell PC into the light-off mode is induced in the next subfield SF3 (indicated by the black circle). At the fourth gradation, therefore, a light emission at the intensity level “α” is done in the subfield SF1, and the sustain discharge involving a light emission at the intensity level “1” is performed one time in the subfield SF2, so that the intensity corresponding to the intensity levels “α” and “1” is represented.
Besides, at each of the fifth gradation—sixteenth gradation, in the subfield SF1, the selective write address discharge for setting the pixel cell PC into the light-up mode is induced, and the pixel cell PC set in the light-up mode is caused to generate the minute light emission discharge (indicated by the square). In addition, the selective erase address discharge for shifting the pixel cell PC into the light-off mode is induced in only one subfield corresponding to the pertinent gradation (indicated by the black circle). At each of the fifth gradation—sixteenth gradation, therefore, the minute light emission discharge is induced in the subfield SF1, and one time of sustain discharge is induced in the subfield SF2, whereupon the sustain discharges in the number of times allotted to the subfields are induced in the subfields (indicated by white circles) continuous in the number of times corresponding to the pertinent gradation. Thus, an intensity which corresponds to the intensity level “α”+“the total number of the sustain discharges induced within the one-field (or one-frame) display period” is visually recognized in each of the fifth gradation—sixteenth gradation.
After all, according to the drive as shown in
According to such a drive, regions where light emission patterns (light-up state and extinction state) are inverted from each other within the one-field display period do not coexist within one screen, so that a pseudo contour appearing in such states is prevented.
Here, according to the drive shown in
Further, according to the drive shown in
Besides, in the drive shown in
Besides, in the drive shown in
Besides, in the drive shown in
Besides, in the drive shown in
Now, functional effects based on the adoption of such a configuration will be described with reference to
Incidentally,
On the other hand,
As shown in
Accordingly, when the column side cathode discharge is induced by impressing the row electrode Y of the PDP 50 with the reset pulse RP1Y1 or RP2Y1 in the waveform in which the potential transition in the rise section is gentle as shown in
That is, the reset pulse RP1Y1 or RP2Y1 as shown in
Incidentally, the waveform at the rise in the reset pulse RP1Y1 or RP2Y1 is not restricted to one of constant gradient as shown in
Besides, in the embodiment, the PDP 50 is driven in accordance with the light emission drive sequence adopting the selective erase address method as shown in
More specifically, the drive control circuit 56 feeds the panel driver with various control signals for successively performing drives which conform to a first reset step R1, a first selective write address step W1W and a minute light emission step LL, respectively, in the head subfield SF1 of a one-field (-frame) display period as shown in
The panel driver, namely, the X-electrode driver 51, Y-electrode driver 53 and address driver 55 generate(s) various drive pulses as shown in
In
First of all, in the second selective write address step W2W of each of the subfields SF2-SF14, the Y-electrode driver 53 impresses a write scan pulse SPW having a peak potential of negative polarity, on the row electrodes Y1-Yn successively and selectively, while impressing a base pulse BP− which has a predetermined base potential of negative polarity, on the row electrodes Y1-Yn simultaneously. Meantime, the X-electrode driver 51 impresses a base pulse BP+ which has a predetermined base potential of positive polarity, on the respective row electrodes X1-Xn. Incidentally, the potential of each of the base pulses BP− and BP+ is set at a potential with which the voltage between the row electrodes X and Y during the non-impression period of the write scan pulse SPW becomes lower than the discharge initiation voltage of the pixel cells PC. Further, in the second selective address step W2W, the address driver 55 first converts a pixel drive data bit corresponding to each of the subfields (SF2-SF14), into a pixel data pulse DP whose pulse voltage corresponds to the logic level of the data bit. By way of example, in a case where the address driver 55 has been fed with the pixel drive data bit of logic level “1” for setting the pixel cell PC into the light-up mode, it converts the data bit into the pixel data pulse DP having a peak potential of positive polarity. On the other hand, the pixel drive data bit of logic level “0” for setting the pixel cell PC into the light-off mode is converted into the pixel data pulse DP of low voltage (0 volt). In addition, the address driver 55 impresses such pixel data pulses DP on the column electrodes D1-Dm in synchronism with the impression timing of each write scan pulse SPW every display line (numbering m pulses). Simultaneously with the write scan pulse SPW, a selective write address discharge is induced between the column electrode D and the row electrode Y within the pixel cell PC which has been impressed with the pixel data pulse DP of high voltage and which is to be set into the light-up mode. Further, immediately after such a selective write address discharge, a weak discharge is induced also between the row electrodes X and Y within the pixel cell PC. More specifically, after the write scan pulse SPW has been impressed, voltages corresponding to the base pulses BP− and BP+ are applied between the row electrodes X and Y. Since, however, the voltages are set to be lower than the discharge initiation voltage of each pixel cell PC, any discharge is not generated within the pixel cell PC merely by the applications of such voltages. In contrast, when the selective write address discharge is generated, a discharge is generated between the row electrodes X and Y merely by the voltage applications based on the base pulses BP− and BP+, by being induced by the selective write address discharge. Such a discharge is not generated in the first selective write address step W1W in which the base pulse BP+ is not impressed on the row electrode X. Owing to such a discharge and the selective write address discharge, the pixel cell PC is set into a state where wall charges of positive polarity, wall charges of negative polarity and wall charges of negative polarity are respectively formed in the vicinity of the row electrode Y, in the vicinity of the row electrode X and in the vicinity of the column electrode D, that is, into the light-up mode. On the other hand, the selective write address discharge as stated above is not generated between the column electrode D and the row electrode Y within the pixel cell PC on which the pixel data pulse DP of low voltage (0 volt) for setting the light-off mode has been impressed simultaneously with the write scan pulse SPW. Therefore, any discharge is not generated even between the row electrodes X and Y. Consequently, the pixel cell PC keeps its state immediately before (light-off mode or light-up mode).
Subsequently, in the sustain step I of the subfield SF2, the Y-electrode driver 53 generates one pulse of the sustain pulse IP having a peak potential of positive polarity, and it impresses the pulse on the row electrodes Y1-Yn simultaneously. Meantime, the X-electrode driver 51 sets the row electrodes X1-Xn into states of ground potential (0 volt), and the address driver 55 sets the column electrodes D1-Dm into states of the ground potential (0 volt). In accordance with the impression of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y within the pixel cell PC set in the light-up mode. Light radiated from the fluorophor layer 17 simultaneously with such a sustain discharge is radiated outside the display panel device through the front transparent substrate 10, whereby one time of display light emission corresponding to the intensity weight of the subfield SF2 is done. Besides, in accordance with the impression of such a sustain pulse IP, a discharge is generated also between the row electrode Y and the column electrode D within the pixel cell PC set in the light-up mode. Owing to such a discharge and the sustain discharge, wall charges of negative polarity are formed in the vicinity of the row electrode Y within the pixel cell PC, and wall charges of positive polarity are respectively formed in the vicinities of the row electrode X and the column electrode D.
Subsequently, in the erase step E of each of the subfields SF2-SF14, the Y-electrode driver 53 impresses on the row electrodes Y1-Yn, an erase pulse EP of negative polarity which has the same waveform as that of a reset pulse RP2Y2 impressed in the latter half part of the first reset step R1 or the second reset step R2. Meantime, the X-electrode driver 51 impresses the base pulse BP+ having the predetermined base potential of the positive polarity, on all the row electrodes X1-Xn in the same manner as in the latter half part of the second reset step R2. In accordance with the erase pulse EP and the base pulse BP+ as stated above, a weak erase discharge is generated within the pixel cell PC in which the sustain discharge as stated above has been induced. Owing to such an erase discharge, some of the wall charges having been formed within the pixel cell PC are erased, and the pixel cell PC is shifted into a light-off mode state. Further, in accordance with the impression of the erase pulse EP, a weak discharge is generated also between the column electrode D and the row electrode Y within the pixel cell PC. Owing to such a discharge, some of the wall charges of positive polarity having been formed in the vicinity of the column electrode D are erased, and the wall charges are adjusted into a quantity in which a selective write address discharge can be properly induced in the second selective write address step W2W. In each of the subfields SF3-SF14, the second selective write address step W2W is performed instead of the selective erase address step WD.
Subsequently, in the sustain step I of each of the subfields SF3-SF14, the X-electrode driver 51 and the Y-electrode driver 53 impress a sustain pulse IP having a peak potential of positive polarity, on the row electrodes Y1-Yn and X1-Xn, alternately on the row electrodes Y and X and repeatedly the number of times (even number of times) corresponding to the intensity weight of the pertinent subfield, as shown in
Here, on the basis of the drive shown in
According to such a drive, intermediate intensity displays for (N+1) gradations (N: the number of subfields within the one-field display period) are permitted in the same manner as in
On the other hand, intermediate intensities for 2N gradations (N: the number of subfields within the one-field display period) can also be represented on the basis of the drive shown in
According to the drive shown in
Therefore, in the case where the drive as shown in
In the embodiment shown in
Besides, in the embodiments shown in
Besides, in the foregoing embodiments, the reset steps (R1 and R2) and the selective write address steps (W1W and W2W) are successively executed in only the head subfield SF1 and the second subfield SF2, but these series of operations may well be similarly executed in the third subfield, et seq.
Besides, in the foregoing embodiments, only in the head subfield SF1, the minute light emission step LL is performed instead of the sustain step I, as the step for generating the light emission pertinent to the display image. However, the minute light emission step(s) LL may well be executed instead of the sustain step I, in any subfield other than the head subfield, or in a plurality of subfields including the head subfield.
Besides, in the reset step R shown in
In another embodiment, a drive control circuit 56 converts the upper 4 bits of dither addition pixel data, into multi-gradation pixel data PDs of 4 bits as represent any intensity level by 15 gradations as shown in
Further, the drive control circuit 56 feeds various control signals for driving the PDP 50 of the above structure in accordance with a light emission drive sequence as shown in
The panel driver, namely, the X-electrode driver 51, Y-electrode driver 53 and address driver 55 generate(s) various drive pulses as shown in
In
First of all, in the first half part of the reset step R of the subfield SF1, the Y-electrode driver 53 impresses on all the row electrodes Y1-Yn, a reset pulse RPY1 of positive polarity in a waveform in which a potential transition at a leading edge with the lapse of time is gentler than in a sustain pulse to be stated later. Incidentally, the peak potential of the reset pulse RPY1 is higher than that of the sustain pulse. Besides, meantime, the address driver 55 sets the column electrodes D1-Dm in the state of ground potential (0 volt). First reset discharges are induced between the row electrodes Y and the column electrodes D within all the pixel cells PC, in accordance with the impression of the reset pulse RPY1. That is, in the first half part of the reset step R, a voltage is applied between the row electrodes Y and the column electrodes D with the former electrodes Y held as an anode side and the latter electrodes D held as a cathode side, whereby discharges in which currents flow from the row electrodes Y toward the column electrodes D (hereinbelow, termed the “column side cathode discharges”) are induced as the first reset discharges. In accordance with such first reset discharges, wall charges of negative polarity and wall charges of positive polarity are respectively formed in the vicinities of the row electrodes Y and in the vicinities of the column electrodes D within all the pixel cells PC.
Besides, in the first half part of the reset step R, the X-electrode driver 51 impresses on all the row electrodes X1-Xn, a reset pulse RPX which is identical in polarity to such a reset pulse RPY1 and which has a peak potential capable of preventing surface charges between the row electrodes X and Y attendant upon the impression of the impression of the reset pulse RPY1.
Subsequently, in the latter half part of the reset step R of the subfield SF1, the Y-electrode driver 53 generates a reset pulse RPY2 of negative polarity in which a potential transition at a leading edge with the lapse of time is gentle, and it impresses the reset pulse RPY2 on all the row electrodes Y1-Yn. Further, in the latter half part of the reset step R, the X-electrode driver 51 impresses a base pulse BP+ which has a predetermined base potential of positive polarity, on all the row electrodes X1-Xn. In accordance with the impressions of the reset pulse RPY2 of the negative polarity and the base pulse BP+ of the positive polarity, second reset discharges are induced between the row electrodes X and Y within all the pixel cells PC. Incidentally, the peak potential of each of the reset pulse RPY2 and the base pulse BP+ is the lowest potential which can reliably induce the second reset discharges between the row electrodes X and Y, in consideration of the wall charges which have been formed in the vicinities of the respective row electrodes X and Y in accordance with the first reset discharges. Besides, a negative peak potential in the reset pulse RPY2 is set at a potential which is higher than the peak potential of a write scan pulse SPW of negative polarity to be stated later, that is, at a potential which is near 0 volt. The reason therefor is that, when the peak potential of the reset pulse RPY2 is made lower than that of the write scan pulse SPW, strong discharges are induced between the row electrodes Y and the column electrodes D, to sharply erase the wall charges having been formed in the vicinities of the column electrodes D, so address discharges in a selective write address step WW become unstable. Owing to the second reset discharges induced in the latter half part of the reset step R, the wall charges having been formed in the vicinities of the row electrodes X and Y within the respective pixel cells PC are erased, whereby all the pixel cells PC are initialized into a light-off mode. Further, weak discharges are induced also between the row electrodes Y and the column electrodes D within all the pixel cells PC, in accordance with the impression of the reset pulse RPY2. Owing to such discharges, some of the wall charges of positive polarity having been formed in the vicinities of the column electrodes D are erased, and the wall charges are adjusted into quantities in which selective write address discharges can be properly induced in the selective write address step WW to be stated later.
Subsequently, in the selective write address step WW of the subfield SF1, the Y-electrode driver 53 impresses the write scan pulse SPW having the peak potential of negative polarity, on the row electrodes Y1-Yn successively and selectively, while impressing a base pulse BP− which has a predetermined base potential of negative polarity as shown in
Further, in the selective write address step WW, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF1, into a pixel data pulse DP whose pulse voltage corresponds to the logic level of the data bit. By way of example, in a case where the address driver 55 has been fed with the pixel drive data bit of logic level “1” for setting the pixel cell PC into the light-up mode, it converts the data bit into the pixel data pulse DP having a peak potential of positive polarity. On the other hand, the pixel drive data bit of logic level “0” for setting the pixel cell PC into the light-off mode is converted into the pixel data pulse DP of low voltage (0 volt). In addition, the address driver 55 impresses such pixel data pulses DP on the column electrodes D1-Dm in synchronism with the impression timing of each write scan pulse SPW every display line (numbering m pulses). Simultaneously with the write scan pulse SPW, a selective write address discharge is induced between the column electrode D and the row electrode Y within the pixel cell PC which has been impressed with the pixel data pulse DP of high voltage and which is to be set into the light-up mode. Further, immediately after such a selective write address discharge, a weak discharge is induced also between the row electrodes X and Y within the pixel cell PC. More specifically, after the write scan pulse SPW has been impressed, voltages corresponding to the base pulses BP− and BP+ are applied between the row electrodes X and Y. Since, however, the voltages are set to be lower than the discharge initiation voltage of each pixel cell PC, any discharge is not generated within the pixel cell PC merely by the applications of such voltages. In contrast, when the selective write address discharge is generated, a discharge is generated between the row electrodes X and Y merely by the voltage applications based on the base pulses BP− and BP+, by being induced by the selective write address discharge. Owing to such a discharge and the selective write address discharge, the pixel cell PC is set into a state where wall charges of positive polarity, wall charges of negative polarity and wall charges of negative polarity are respectively formed in the vicinity of the row electrode Y, in the vicinity of the row electrode X and in the vicinity of the column electrode D, that is, into the light-up mode. On the other hand, the selective write address discharge as stated above is not generated between the column electrode D and the row electrode Y within the pixel cell PC on which the pixel data pulse DP of low voltage (0 volt) for setting the light-off mode has been impressed simultaneously with the write scan pulse SPW. Therefore, any discharge is not generated even between the row electrodes X and Y. Consequently, the pixel cell PC keeps its state immediately before, namely, the state of the light-off mode into which it has been initialized in the reset step R.
Subsequently, in the sustain step I of the subfield SF1, the Y-electrode driver 53 generates one pulse of the sustain pulse IP having a peak potential of positive polarity, and it impresses the pulse on the row electrodes Y1-Yn simultaneously. Meantime, the X-electrode driver 51 sets the row electrodes X1-Xn into states of ground potential (0 volt), and the address driver 55 sets the column electrodes D1-Dm into states of the ground potential (0 volt). In accordance with the impression of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y within the pixel cell PC set in the light-up mode as stated above. Light radiated from a fluorophor layer 17 simultaneously with such a sustain discharge is radiated outside the display panel device through a front transparent substrate 10, whereby one time of display light emission corresponding to the intensity weight of the subfield SF1 is done. Besides, in accordance with the impression of such a sustain pulse IP, a discharge is generated also between the row electrode Y and the column electrode D within the pixel cell PC set in the light-up mode. Owing to such a discharge and the sustain discharge, wall charges of negative polarity are formed in the vicinity of the row electrode Y within the pixel cell PC, and wall charges of positive polarity are respectively formed in the vicinities of the row electrode X and the column electrode D. In addition, after the impression of such a sustain pulse IP, the Y-electrode driver 53 impresses on the row electrodes Y1-Yn, a wall-charge adjustment pulse CP which has a peak potential of negative polarity and in which a potential transition at a leading edge with the lapse of time is gentle as shown in
Subsequently, in the selective erase address step WO of each of the subfields SF2-SF14, the Y-electrode driver 53 impresses an erase scan pulse SPD having a peak potential of negative polarity as shown in
Subsequently, in the sustain step I of each of the subfields SF2-SF14, the X-electrode driver 51 and the Y-electrode driver 53 impress a sustain pulse IP having a peak potential of positive polarity, on the row electrodes X1-Xn and Y1-Yn, alternately on the row electrodes X and Y and repeatedly the number of times (even number of times) corresponding to the intensity weight of the pertinent subfield, as shown in
The drive as described above is executed on the basis of the fifteen sorts of pixel drive data GD as shown in
According to such a drive, regions where light emission patterns (light-up state and extinction state) are inverted from each other within the one-field display period do not coexist within one screen, so that a pseudo contour appearing in such states is prevented.
Here, according to the drive shown in
Further, according to the drive shown in
Besides, in the drive shown in
Besides, in the drive shown in
Besides, in the PDP 50 shown in
Now, functional effects based on the adoption of such a configuration will be described with reference to FIGS. 29 and 30.
Incidentally, the transition of a discharge strength in the column side cathode discharge which was induced in the case where the reset pulse RPY1 as shown in
On the other hand, the transition of a discharge strength in the column side cathode discharge which was induced in the case where the reset pulse RPY1 was impressed on the PDP 50 according to the invention wherein the CL emission MgO crystals were contained in both the magnesium oxide layer 13 and the fluorophor layer 17, is shown in
As shown in
Accordingly, when the column side cathode discharge is induced by impressing the row electrode Y of the PDP 50 with the reset pulse RPY1 in the waveform in which the potential transition in the rise section is gentle as shown in
That is, in the invention, the reset pulse RPY1 as shown in
Incidentally, the waveform at the rise in the reset pulse RPY1 which is impressed on the row electrodes Y in order to induce the reset discharge as the column side cathode discharge is not restricted to one of constant gradient as shown in
Besides, in the embodiment, the PDP 50 is driven in accordance with the light emission drive sequence adopting the selective erase address method as shown in
More specifically, the drive control circuit 56 feeds the panel driver with various control signals for successively performing drives which conform to a selective write address step WW, a sustain step I and an erase step E, respectively, in each of subfields SF1-SF14 as shown in
The panel driver, namely, the X-electrode driver 51, Y-electrode driver 53 and address driver 55 generate(s) various drive pulses as shown in
In
First of all, in the sustain step I of the head subfield SF1, the Y-electrode driver 53 generates one pulse of a sustain pulse IP having a peak potential of positive polarity, and it impresses the pulse on the row electrodes Y1-Yn simultaneously. Meantime, the X-electrode driver 51 sets the row electrodes X1-Xn into states of ground potential (0 volt), and the address driver 55 sets the column electrodes D1-Dm into states of the ground potential (0 volt). In accordance with the impression of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y within the pixel cell PC set in the light-up mode. Light radiated from the fluorophor layer 17 simultaneously with such a sustain discharge is radiated outside the display panel device through the front transparent substrate 10, whereby one time of display light emission corresponding to the intensity weight of the subfield SF1 is done. Besides, in accordance with the impression of such a sustain pulse IP, a discharge is generated also between the row electrode Y and the column electrode D within the pixel cell PC set in the light-up mode. Owing to such a discharge and the sustain discharge, wall charges of negative polarity are formed in the vicinity of the row electrode Y within the pixel cell PC, and wall charges of positive polarity are respectively formed in the vicinities of the row electrode X and the column electrode D.
Subsequently, in the erase step E of each of the subfields SF1-SF14, the Y-electrode driver 53 impresses on the row electrodes Y1-Yn, an erase pulse EP of negative polarity which has the same waveform as that of a reset pulse RPY2 impressed in the latter half part of the reset step R1. Meantime, the X-electrode driver 51 impresses a base pulse BP+ having a predetermined base potential of the positive polarity, on all the row electrodes X1-Xn in the same manner as in the latter half part of the reset step R. In accordance with the erase pulse EP and the base pulse BP+ as stated above, a weak erase discharge is generated within the pixel cell PC in which the sustain discharge as stated above has been induced. Owing to such an erase discharge, some of the wall charges having been formed within the pixel cell PC are erased, and the pixel cell PC is shifted into a light-off mode state. Further, in accordance with the impression of the erase pulse EP, a weak discharge is generated also between the column electrode D and the row electrode Y within the pixel cell PC. Owing to such a discharge, the wall charges of positive polarity having been formed in the vicinity of the column electrode D are adjusted into a quantity in which a selective write address discharge can be properly induced in the next selective write address step WW.
Subsequently, in the sustain step I of each of the subfields SF2-SF14, the X-electrode driver 51 and the Y-electrode driver 53 impress a sustain pulse IP having a peak potential of positive polarity, on the row electrodes Y1-Yn and X1-Xn, alternately on the row electrodes Y and X and repeatedly the number of times corresponding to the intensity weight of the pertinent subfield, as shown in
Here, in performing the drive shown in
According to the drive shown in
Therefore, in the case where the drive based on the selective write address method as shown in
In the embodiment shown in
Besides, in the reset step R shown in
This application is based on Japanese Patent Applications Nos. 2006-243912, 2006-246686 and 2006-246687 which are hereby incorporated by reference.
Number | Date | Country | Kind |
---|---|---|---|
2006-243912 | Sep 2006 | JP | national |
2006-246686 | Sep 2006 | JP | national |
2006-246687 | Sep 2006 | JP | national |
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Number | Date | Country | |
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