1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a plasma display panel that is adaptive for preventing an abnormal discharge occurring from a non-display area to thereby enhance a picture quality and reliability.
2. Description of the Related Art
Generally, a plasma display panel (PDP) excites and radiates a phosphorus material using an ultraviolet ray generated upon discharge of an inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe, to thereby display a picture. Such a PDP is easy to be made into a thin-film and large-dimension type. Also, the PDP is available in the current market and shows a high occupation rate in the large-dimension flat panel market.
Referring to
On the upper substrate 1 provided with the scan electrode Y and the sustain electrode Z, an upper dielectric layer 6 and an MgO protective layer 7 are disposed. A lower dielectric layer 4 are formed on the lower substrate 2 provided with the address electrode X in such a manner to cover the address electrode X. Barrier ribs are formed vertically above the lower dielectric layer 4. A phosphorous material 5 is coated onto the surfaces of the lower dielectric layer 4 and the barrier ribs 3. An inactive mixture gas such as He+Xe, Ne+Xe or He+Ne+Xe is injected into a discharge space provided among the upper substrate 1, the lower substrate 2 and the barrier ribs 3.
Such a PDP makes a time-divisional driving of one frame, which is divided into various sub-fields having a different emission frequency, so as to realize gray levels of a picture. Each sub-field is again divided into an initialization period (or reset period) for initializing the entire field, an address period for selecting a scan line and selecting the cell from the selected scan line and a sustain period for expressing gray levels depending on the discharge frequency. The initialization period is divided into a set-up interval supplied with a rising ramp waveform and a set-down interval supplied with a falling ramp waveform.
For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields SF1 to SF8 as shown in
Referring to
In the initialization period (or the reset period), a rising ramp waveform Ramp-up is applied to all the scan electrodes Y in a set-up interval SU. A discharge is generated within the cells of the full field with the aid of the rising ramp waveform Ramp-up. By this set-up discharge, positive wall charges are accumulated onto the address electrode X and the sustain electrode Z while negative wall charges are accumulated onto the scan electrode Y.
In a set-down interval SD, a falling ramp waveform Ramp-down falling from a positive voltage lower than a peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y after the rising ramp waveform Ramp-up was applied. The falling ramp waveform Ramp-down causes a weak erasure discharge within the cells to erase a portion of excessively formed wall charges. Wall charges enough to generate a stable address discharge are uniformly left within the cells with the aid of the set-down discharge. Herein, such a waveform applied during the initialization period may be referred to as “reset pulse”.
In the address period, a negative scanning pulse scan is sequentially applied to the scan electrodes Y and, at the same time, a positive data pulse data is applied to the address electrodes X in synchronization with the scanning pulse scan. A voltage difference between the scanning pulse scan and the data pulse data is added to a wall voltage generated in the initialization period to thereby generate an address discharge within the cells supplied with the data pulse data. Wall charges enough to cause a discharge when a sustain voltage is applied are formed within the cells selected by the address discharge.
Meanwhile, a positive direct current voltage Zdc is applied to the sustain electrodes Z during the set-down interval and the address period. The direct current voltage Zdc causes a set-down discharge between the sustain electrode Z and the scan electrode Y, and establishes a voltage difference between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X so as not to make a strong discharge between the scan electrode Y and the sustain electrode Z in the address period.
In the sustain period, a sustaining pulse sus is alternately applied to the scan electrodes Y and the sustain electrodes Z. Then, a wall voltage within the cell selected by the address discharge is added to the sustain pulse sus to thereby generate a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied.
Just after the sustain discharge was finished, a ramp waveform ramp-ers having a small pulse width and a low voltage level is applied to the sustain electrode Z to thereby erase wall charges left within the cells of the entire field.
As shown in
However, the conventional PDP has a problem in that a discharge is generated accidentally from the upper non-display area 32 and the lower non-display area 33. Such a discharge is defined by “abnormal discharge”. More specifically, if a discharge, such as an initialization discharge, address discharge or a sustain discharge, etc., occurs upon driving of the PDP, then space charges generated by such a discharge are accumulated onto dielectric layers of the upper non-display area 32 and the lower non-display area 33. For instance, as shown in
In order to overcome the normal discharge, there has been suggested a scheme that applies a reset pulse applied in the initialization period to the dummy electrode upon driving of the PDP to thereby discharge charges flowing into the dummy electrode and erase them continuously. However, such a conventional scheme fails to completely eliminate an abnormal discharge generated at the PDP.
Accordingly, it is an object of the present invention to provide a plasma display panel that is adaptive for preventing an abnormal discharge occurring from a non-display area to thereby enhance a picture quality and a reliability.
In order to achieve these and other objects of the invention, a plasma display panel according to one embodiment of the present invention has an active area on which a picture is displayed and a non-display area positioned at the outside of the active area, wherein dummy electrodes positioned within said non-display area have a different gap between electrodes from sustain electrode pairs positioned within said active area.
In the plasma display panel, the gap between electrodes of said dummy electrodes is narrower than that of said sustain electrode pairs.
In the plasma display panel, said dummy electrodes are formed from a transparent electrode and a metal electrode.
In the plasma display panel, said dummy electrodes have a narrower electrode width than said sustain electrode pairs.
In the plasma display panel, said transparent electrodes are formed from a non-conductive metal electrode.
In the plasma display panel, said transparent electrodes are formed from a conductive metal.
In the plasma display panel, said transparent electrodes are formed from a resin material.
In the plasma display panel, said dummy electrodes have a different electrode width from said sustain electrode pairs.
A plasma display panel has an active area on which a picture is displayed and a non-display area positioned at the outside of the active area, wherein dummy electrodes positioned within said non-display area include metal electrode.
These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:
Referring to
Each of the sustain electrode pair Y and Z, the dummy electrodes UDE1 and UDE2 and lower dummy electrodes BDE1 and BDE2 comprises, as shown in
The PDP according to the first embodiment will be described in conjunction with
The scan electrode Y and the sustain electrode Z of the sustain electrode pair are provided on an upper substrate of the PDP within an active area. The dummy electrodes UDE1, UDE2, BDE1 and BDE2 are provided on the upper substrate of the PDP within a non-display area positioned above and below the active area. Address electrodes (not shown) are provided on a lower substrate of the PDP in such a manner to cross the electrodes UDE1, UDE2, BDE1, BDE2, Y and Z on the upper substrate.
The upper/lower dummy electrodes UDE1, UDE2, BDE1 and BDE2 have a narrower gap g1 between electrodes than a width w2 of the sustain electrode pair Y and Z at the active area so that a discharge between electrodes can be easily generated well. Also, the upper/lower dummy electrodes UDE1, UDE2, BDE1 and BDE2 have a narrower gap g1 between electrodes than a gap g2 between electrodes within the sustain electrode pair Y and Z at the active area 91 so that a discharge can be easily generated well. Furthermore, each dummy electrode UDE1, UDE2, BDE1 and BDE2 has a narrower electrode width w1 than the width w2 of the sustain electrode pair Y and Z at the active area 91 so as to generate a small charge amount at the surface of the electrode.
Accordingly, in the PDP according to the first embodiment, a gap between electrodes of the dummy electrodes provided at the non-display area is formed narrowly and also an electrode width is formed narrowly. Thus, the PDP according to the first embodiment can be more easily and better discharged than the dummy electrodes within the conventional PDP upon discharge caused by a reset pulse applied in the initialization period, and can generate a strong discharge at the dummy electrodes to thereby erase much a lot of accumulated electric charges. As a result, the PDP according to the first embodiment of the present invention can restrain an abnormal discharge at the dummy electrodes provided at the non-display area.
Referring to
The PDP according to the second embodiment will be described in conjunction with
The scan electrode Y and the sustain electrode Z of the sustain electrode pair are provided on an upper substrate of the PDP within an active area. The dummy electrodes UDE3, UDE4, BDE3 and BDE4 are provided on the upper substrate of the PDP within a non-display area positioned above and below the active area. Address electrodes (not shown) are provided on a lower substrate of the PDP in such a manner to cross the electrodes UDE3, UDE4, BDE3, BDE4, Y and Z on the upper substrate.
The upper/lower dummy electrodes UDE3, UDE4, BDE3 and BDE4 have a narrower gap g1 between electrodes than a width w2 of the sustain electrode pair Y and Z at the active area so that a discharge between electrodes can be easily generated well. Also, the upper/lower dummy electrodes UDE3, UDE4, BDE3 and BDE4 have a narrower gap g1 between electrodes than a gap g2 between electrodes within the sustain electrode pair Y and Z at the active area so that a discharge can be easily generated well. Furthermore, each dummy electrode UDE3, UDE4, BDE3 and BDE4 has a narrower electrode width w1 than the width w2 of the sustain electrode pair Y and Z at the active area 91 so as to generate a small charge amount at the surface of the electrode.
Accordingly, in the PDP according to the second embodiment, a gap between electrodes of the dummy electrodes provided at the non-display area is formed narrowly and also an electrode width is formed narrowly. Thus, the PDP according to the second embodiment can be more easily and better discharged than the dummy electrodes within the conventional PDP upon discharge caused by a reset pulse applied in the initialization period, and can generate a strong discharge at the dummy electrodes to thereby erase much a lot of accumulated electric charges. As a result, the PDP according to the first embodiment of the present invention can restrain an abnormal discharge at the dummy electrodes provided at the non-display area.
In addition, the PDP according to the second embodiment of the present invention has the dummy electrodes made of only a metal electrode. This does not allow a light emitted upon plasma discharge to be transmitted into the picture display area when a reset pulse is applied to the dummy electrodes provided within the non-display area to cause a plasma discharge because the dummy electrodes are formed from a material having no light transmission. Accordingly, it becomes possible to improve a picture quality.
As described above, the PDP according to the present invention has a narrower gap between electrodes of the dummy electrodes than the sustain electrode pair within the active area and has a narrow electrode width thereof, so that it can easily generate a discharge between the dummy electrodes well and reduce a generation of electric charges accumulated onto the dummy electrodes. As a result, the PDP according to the present invention can prevent an abnormal discharge to thereby improve a picture quality.
Furthermore, the PDP according to the present invention can restrain an abnormal discharge to thereby prevent a break phenomenon of the address driving circuit and the scan driving circuit caused by a very large current flowing into the dummy electrodes upon abnormal discharge in the conventional PDP. Accordingly, it becomes possible to assure a reliability of the PDP.
Moreover, the PDP according to the present invention forms the dummy electrodes provided within the non-display area from a material having no light transmission, thereby shutting off a light generated upon plasma discharge caused by a reset pulse applied in the initialization period. Accordingly, it becomes possible to improve a picture quality.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
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