Patent Application
20120293065
A technique of the present disclosure relates to a plasma display panel used for a display device.
A plasma display panel (hereinafter referred to as a PDP) has a configuration where a pair of substrates is arranged as opposed to each other such that a discharge space is formed therebetween. The discharge space is partitioned into a plurality of spaces with barrier ribs arranged on the substrate, to constitute a plurality of discharge cells. In order to generate discharge in the discharge space sectioned with the barrier ribs, a display electrode and a data electrode are arranged on the substrate. Phosphors that emit red, green or blue light by discharge are provided on the substrate. The PDP excites the phosphors by means of ultraviolet light generated by discharge, and respectively emits red, green and blue visible light from the discharge cells, to display an image.
In the PDP, the display electrode is configured by superimposition of a wide, band-like transparent electrode and a bus line as a metal electrode, so as to increase light-emitting luminance at the time of image display. Hence an area of the display electrode increases. In order to suppress a discharge current that increases due to this configuration, or to eliminate the transparent electrode for reduction in number of steps, a display electrode divided into a plurality of portions and provided with openings has been used (e.g., refer to Patent Literature 1).
A plasma display panel is provided with a rear plate and a front plate arranged as opposed to the rear plate. The rear plate has a vertical barrier rib and a horizontal barrier rib orthogonal to the vertical barrier rib. The front plate has a first transparent electrode in parallel with the horizontal barrier rib and a plurality of second transparent electrodes in parallel with the vertical barrier rib. The front plate further has a plurality of bus electrodes having the same width and arranged with the same interval. The plurality of bus electrodes includes a first bus electrode electrically connected with the first transparent electrode, and a second bus electrode electrically connected with the plurality of second transparent electrodes. The second bus electrode is formed in a position opposed to the horizontal barrier rib.
First, an overall configuration of PDP 100 according to the present exemplary embodiment will be described with reference to
As shown in
Front plate 1 is made up of substrate 4, display electrodes 7, dielectric layer 8 and protective layer 9. A plurality of conductive display electrodes 7 is arrayed in a row direction on glass-made substrate 4. Display electrode 7 is made up of scan electrode 5 and sustain electrode 6. Scan electrode 5 and sustain electrode 6 are arranged in parallel with each other with a discharge gap provided therebetween. Scan electrode 5 and sustain electrode 6 are formed in an order of scan electrode 5, sustain electrode 6, sustain electrode 6 and scan electrode 5. Dielectric layer 8 made of a glass material is formed so as to cover scan electrode 5 and sustain electrode 6. Protective layer 9 made of magnesium oxide (MgO) is formed on dielectric layer 8.
As shown in
As shown in
Herein, a plurality of first bus electrodes 5b and second bus electrodes 6b has the same width and are arranged with the same interval.
First transparent electrode 5a, second transparent electrode 6c and third transparent electrode 6a are indium tin oxide (ITO) or the like. First bus electrode 5b and second bus electrode 6b each include a black pigment, the glass material and a conductive metal such as silver (Ag). The configurations of scan electrode 5 and sustain electrode 6 will be described in detail later.
As shown in
Herein, as shown in
Then, front plate 1 and rear plate 2 are arranged as opposed to each other such that scan electrode 5 and sustain electrode 6 intersect with data electrode 12. As shown in
Scan electrodes 5 are made up of n-lines of scan electrodes Y1, Y2, Y3 . . . Yn extending in the row direction. Sustain electrodes 6 are made up of n-lines of sustain electrodes X1, X2, X3 . . . Xn extending in the row direction. Data electrodes 12 are made up of m-lines of data electrodes A1 . . . Am extending in the column direction. Discharge cell 15 is formed in an area where scan electrode Yp and sustain electrode Xp in a pair (1≦p≦n) intersect with one line of data electrode Aq (1≦q≦m). m×n pieces of discharge cells 15 are formed inside discharge space 3. Scan electrode 5 and sustain electrode 6 are formed on front plate 1 in a pattern of scan electrode Y1, sustain electrode X1, sustain electrode X2, scan electrode Y2 . . . . Scan electrode 5 and sustain electrode 6 are connected to a terminal of a drive circuit provided outside an image display area formed with discharge cells 15.
Next, an overall configuration and a driving method of plasma display device 200 will be described using foregoing PDP 100.
As shown in
In
Next, drive voltage waveforms for driving PDP 100 and operations thereof will be described with reference to
In PDP 100 according to the present exemplary embodiment, one field is divided into a plurality of subfields, and each of the subfields has an initializing period, an address period and a sustain period.
In the initializing period of a first subfield, data electrodes A1 to Am and sustain electrodes X1 to Xn are held at 0(V). A ramp voltage, which gradually rises from voltage Vi1(V) being not higher than a discharge start voltage toward voltage Vi2(V) exceeding the discharge start voltage, is applied to scan electrodes Y1 to Yn. Then, first weak initializing discharge is generated in all discharge cells 15, and a negative wall voltage is accumulated on a top of each of scan electrodes Y1 to Yn. Further, a positive wall voltage is accumulated on a top of each of sustain electrodes X1 to Xn and data electrodes A1 to Am. Thereby, the wall voltage on the top of the electrode herein is a voltage generated by wall charges accumulated on the dielectric layer, the phosphor layer or the like which covers the electrodes.
Thereafter, sustain electrodes X1 to Xn are held at positive voltage Vh(V), and scan electrodes Y1 to Yn are each applied with a ramp voltage which gradually falls from voltage Vi3(V) toward voltage Vi4(V). Thereupon, second weak initializing discharge is generated in all discharge cells 15. Thereby, the wall voltages between the tops of scan electrodes Y1 to Yn and the tops of sustain electrodes X1 to Xn are weakened, to be adjusted to values appropriate for an address operation. The wall voltages on the tops of data electrodes A1 to Am are also adjusted to values appropriate for the address operation.
In the subsequent address period, scan electrodes Y1 to Yn are temporarily held at Vr(V). Next, negative scan pulse voltage Va(V) is applied to scan electrode Y1 on a first row. Further, positive address pulse voltage Vd(V) is applied to data electrode Ak (k=1 to m) in discharge cell 15 to be displayed on the first row out of data electrodes A1 to Am. At this time, a voltage at an intersecting section of data electrode Ak and scan electrode Y1 is one obtained by adding the wall voltage on the top of data electrode Ak and the wall voltage on the top of scan electrode Y1 to external applied voltage (Vd−Va)(V), and it exceeds the discharge start voltage. Then, address discharge is generated between data electrode Ak and scan electrode Y1, and between sustain electrode X1 and scan electrode Y1. Thereby, the positive wall voltage is accumulated on the top of scan electrode Y1 in this discharge cell 15, and the negative wall voltage is accumulated on the top of sustain electrode X1 therein. At this time, the negative wall voltage is also accumulated on the top of data electrode Ak.
In this manner, the address discharge is generated in discharge cell 15 to be displayed on the first row, and the address operation is performed to accumulate the wall voltage on the top of each electrode. Meanwhile, voltages at the intersecting sections of data electrodes A1 to Am and scan electrode Y1, to which the address pulse voltage Vd(V) has not been applied, do not exceed the discharge start voltage, and hence the address discharge is not generated. The above address operation is sequentially performed up to discharge cell 15 on an n-th row, and the address period is completed.
In the subsequent sustain period, positive sustain pulse voltage Vs(V) as a first voltage is applied to each of scan electrodes Y1 to Yn. A ground potential, namely 0(V), is applied as a second voltage to each of sustain electrodes X1 to Xn. At this time, in discharge cell 15 where the address discharge has been generated, a voltage between the top of scan electrode Yi (i=1 to n) and the top of sustain electrode Xi is one obtained by adding the wall voltage on the top of scan electrode Yi and the wall voltage on the top of sustain electrode Xi to sustain pulse voltage Vs(V), and it exceeds the discharge start voltage. Then, sustain discharge is generated between scan electrode Yi and sustain electrode Xi, and by means of ultraviolet rays generated at this time, the phosphor layer emits light. Then, the negative wall voltage is accumulated on the top of scan electrode Yi, and the positive wall voltage is accumulated on the top of sustain electrode Xi. At this time, the positive wall voltage is also accumulated on data electrode Ak.
In discharge cell 15 where the address discharge has not been generated in the address period, the sustain discharge is not generated, and the wall voltage at the end of the initializing period is held. Subsequently, 0(V) as the second voltage is applied to each of scan electrodes Y1 to Yn. Sustain pulse voltage Vs (V) as the first voltage is applied to each of sustain electrodes X1 to Xn. Then, in discharge cell 15 where the sustain discharge has been generated, a voltage between the top of sustain electrode Xi and the top of scan electrode Yi exceeds the discharge start voltage, and hence sustain discharge is generated again between sustain electrode Xi and scan electrode Yi. Then, the negative wall voltage is accumulated on the top of sustain electrode Xi, and the positive wall voltage is accumulated on the top of scan electrode Yi.
Hereinafter, as in the above, sustain pulses in the number corresponding to luminance weight are alternately applied to scan electrodes Y1 to Yn and sustain electrodes X1 to Xn, whereby the sustain discharge is continuously performed in discharge cell 15 where the address discharge has been generated in the address period. In this manner, the sustain operation in the sustain period is completed. Since operations in the initializing period, the address period and the sustain period in and after a subsequent subfield are almost the same as the operations in the first subfield, descriptions of those operations are omitted.
Next, a configuration of display electrode 7 in PDP 100 according to the present exemplary embodiment will be described in more detail with respect to
As shown in
First transparent electrode 5a, second transparent electrode 6c and third transparent electrode 6a are formed on front plate 1. A plurality of first transparent electrodes 5a is formed in parallel with horizontal barrier rib 13b. A plurality of second transparent electrodes 6c is formed in parallel with vertical barrier rib 13a. A plurality of third transparent electrodes 6a is formed in parallel with horizontal barrier rib 13b. Third transparent electrodes 6a are electrically connected with both ends of the plurality of second transparent electrodes 6c.
Further, a plurality of first bus electrodes 5b and second bus electrodes 6b is formed on front plate 1. First bus electrode 5b is electrically connected with first transparent electrode 5a. Second bus electrode 6b is electrically connected with the plurality of second transparent electrodes 6c. Second bus electrode 6b is formed in a position opposed to horizontal barrier rib 13b. First bus electrodes 5b and second bus electrodes 6b have the same width and are arranged with the same interval. That is, width W1 of first bus electrode 5b is the same as width W2 of second bus electrode 6b. Further, interval S1 between first bus electrode 5b and second bus electrode 6b is the same as interval S2 between adjacent first bus electrodes 5b. First bus electrode 5b and second bus electrode 6b are formed in an order of second bus electrode 6b, first bus electrode 5b and second bus electrode 6b. Interval W3 between second bus electrode 6b and third transparent electrode 6a, out of third transparent electrodes 6a formed at both-side ends of second transparent electrode 6c, is the same as interval W4 between second bus electrode 6b and the other third transparent electrode 6a. A plurality of third transparent electrodes 6a is formed in parallel with second bus electrode 6b. A plurality of discharge gaps is provided between first transparent electrode 5a and third transparent electrode 6a.
As thus described, PDP 100 of the present exemplary embodiment is configured such that second bus electrode 6b is formed in a position opposed to horizontal barrier rib 13b. With this configuration, second bus electrode 6b of sustain electrode 6 constituting discharge cell 15 does not exist inside discharge cell 15, whereby it is possible to improve an opening rate of discharge cell 15. Herewith, PDP 100 of the present exemplary embodiment can improve the efficiency in extracting light from discharge cell 15, so as to improve emission efficiency.
Further, PDP 100 of the present exemplary embodiment is configured such that first bus electrodes 5b and second bus electrodes 6b are formed with the same width and the same interval. Therefore, when PDP 100 is not turned on, first bus electrode 5b and second bus electrode 6b are inconspicuous. That is, PDP 100 of the present exemplary embodiment can suppress recognition of first bus electrode 5b and second bus electrode 6b as a striped pattern. Further, even with first bus electrode 5b and second bus electrode 6b having a black pigment, the PDP can suppress recognition of first bus electrode 5b and second bus electrode 6b as the striped pattern.
It should be noted that second transparent electrode 6c may be formed in parallel with vertical barrier rib 13a and on one side of second bus electrode 6b. Third transparent electrode 6a may be formed in parallel with second bus electrode 6b and at one ends of the plurality of second transparent electrodes 6c. In that case, scan electrode 5 and sustain electrode 6 can be formed in an order of scan electrode 5, sustain electrode 6, scan electrode 5 and sustain electrode 6.
Moreover,
First transparent electrode 5a, second transparent electrode 6c and third transparent electrode 6a are formed on front plate 1. A plurality of first transparent electrodes 5a is formed in parallel with horizontal barrier rib 13b. A plurality of second transparent electrodes 6c is formed in parallel with vertical barrier rib 13a. Third transparent electrode 6a is formed in a position opposed to horizontal barrier rib 13b. Third transparent electrode 6a is electrically connected with the plurality of second transparent electrodes 6c. Third transparent electrode 6a is electrically connected with second bus electrode 6b.
Further, a plurality of first bus electrodes 5b and second bus electrodes 6b is formed on front plate 1. First bus electrode 5b is electrically connected with first transparent electrode 5a. Second bus electrode 6b is electrically connected with the plurality of second transparent electrodes 6c. Second bus electrode 6b is formed in a position opposed to horizontal barrier rib 13b. First bus electrodes 5b and second bus electrodes 6b have the same width and are arranged with the same interval. That is, width W1 of first bus electrode 5b is the same as width W2 of second bus electrode 6b. Further, interval S1 between first bus electrode 5b and second bus electrode 6b is the same as interval S2 between adjacent first bus electrodes 5b. First bus electrode 5b and second bus electrode 6b are formed in an order of second bus electrode 6b, first bus electrode 5b and second bus electrode 6b. A plurality of discharge gaps is provided between first transparent electrode 5a and second transparent electrode 6c.
Although another exemplary embodiment has been illustrated in
As thus described, by arrangement of first bus electrodes 5b and second bus electrodes 6b with the same width and the same interval, PDP 100 of the present exemplary embodiment can suppress recognition of first bus electrode 5b and second bus electrode 6b as the striped pattern when PDP 100 is not turned on. Further, by formation of second bus electrode 6b in the position opposed to horizontal barrier rib 13b, PDP 100 of the present exemplary embodiment can improve the efficiency in extracting light from discharge cell 15, so as to improve emission efficiency.
As described above, the technique of the present disclosure is useful in enhancing appearance of a plasma display panel when it is turned off.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-025078 | Feb 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2011/000538 | 2/1/2011 | WO | 00 | 11/21/2011 |
