Patent Application
20100109527
1. Field
Embodiments relate to a plasma display panel (PDP) and, more particularly, to a PDP that can reduce or prevent damage to a substrate due to thermal expansion coefficient mismatch between a dielectric layer and frit glass.
2. Description of the Related Art
In general, a PDP is flat display devices in which a predetermined discharge gas is injected between two substrates having a plurality of discharge electrodes thereon to generate a mutual discharge. Vacuum ultraviolet radiation generated by the mutual discharge excites phosphor materials of phosphor layers, thereby realizing display of desired numbers, text, or graphics.
Due to the recent demand for large PDPs, a multi-cutting process technology that enables production of a plurality of, e.g., two to eight, divided glass substrates from a mother glass is used in a manufacturing process to improve efficiency. That is, the mother glass can be divided into unit substrates by forming various pattern layers, e.g., pairs of discharge electrode, a dielectric layer formed to cover the pairs of discharge electrodes, barrier ribs, phosphor layers, and frit glass, are formed on each of the unit substrates, and then cutting a border portion between each of the unit substrates of the mother glass to form unit substrates.
However, conventional PDPs have problems in that, as multiple substrates are obtained at the same time, the substrates are vulnerable to damage due to differences in bending, thermal deformation, contraction, and so forth.
Embodiments are therefore directed to a PDP, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
It is therefore a feature of an embodiment to provide a PDP that can reduce thermal expansion coefficient mismatch and prevent damage to a substrate by allowing the absolute value of a thermal expansion coefficient difference between a dielectric layer and a sealing material to be defined by a specific numerical formula.
At least one of the above and other features and advantages may be realized by providing a PDP, including a first substrate and a second substrate facing each other, a plurality of first discharge electrodes on the first substrate, a first dielectric layer covering the first discharge electrodes, a plurality of second discharge electrodes on the second substrate and intersecting the discharge electrodes, a second dielectric layer covering the second discharge electrodes, and a sealing material between the first substrate and the second substrate, wherein an absolute thermal expansion coefficient difference between the second dielectric layer and the sealing material is less than or equal to 13×10−7/° C.
The second dielectric layer may be formed of at least one of a lead-based material, a bismuth-based material, a boron-zinc-based material, and a boron-alumina-based material.
The lead-based material may have a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., the bismuth-based material may have a thermal expansion coefficient of about 65×10−7/° C. to about 90×10−7/° C., the boron-zinc-based material may have a thermal expansion coefficient of about 75×10−7/° C. to about 95×10−7/° C., and the boron-alumina-based material may have a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
The sealing material may be formed of a lead-based material or a bismuth-based material.
The lead-based material may have a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., and the bismuth-based material may have a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
The first discharge electrodes may be sustain electrode pairs arranged in one direction of the first substrate, and the second discharge electrodes may be address electrodes arranged in one direction of the second substrate.
The sealing material may be along edges of inner surfaces of the first substrate and the second substrate facing each other.
The sealing material may be between a surface of the first dielectric layer covering the discharge electrodes and a surface of the second dielectric layer covering the address electrodes.
A protective layer may be between the surface of the first dielectric layer and the sealing material.
The PDP may further include discharge barrier ribs in a display area where an image is displayed and dummy barrier ribs in a non-display area that is an area other than the display area, wherein the sealing material is continuously provided along edges of at least one of the first substrate and the second substrate in the non-display area outside the dummy barrier ribs.
The PDP may further include Red, green, and blue phosphor layers in a space formed by the discharge barrier ribs, wherein no phosphor layers in a space formed by the dummy barrier ribs.
At least one of the above and other features and advantages may also be realized by providing a PDP, including a substrate, a plurality of discharge electrodes disposed on the substrate, a dielectric layer covering the discharge electrodes, and a sealing material on the substrate, wherein an absolute thermal expansion coefficient difference between the second dielectric layer and the sealing material is less than or equal to 13×10−7/° C.
The dielectric layer may be formed of at least one of a lead-based material, a bismuth-based material, a boron-zinc-based material, and a boron-alumina-based material.
The lead-based material may have a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., the bismuth-based material may have a thermal expansion coefficient of about 65×10−7/° C. to about 90×10−7/° C., the boron-zinc-based material may have a thermal expansion coefficient of about 75×10−7/° C. to about 95×10−7/° C., and the boron-alumina-based material may have a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
The sealing material may be formed of a lead-based material or a bismuth-based material.
The lead-based material may have a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., and the bismuth-based material may have a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
The discharge electrodes may produce an address discharge.
The sealing material may be formed on a surface of the dielectric layer covering the discharge electrodes.
The sealing material may be continuously provided along edges of the substrate.
The PDP may further include discharge barrier ribs in a display area where an image is displayed and dummy barrier ribs in a non-display area that is an area other than the display area, wherein the sealing material is continuously provided along edges of at least one of the first substrate and the second substrate in the non-display area outside the dummy barrier ribs.
The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
Korean Patent Application No. 10-2008-0110012, filed on Nov. 6, 2008, in the Korean Intellectual Property Office, and entitled: “Plasma Display Panel,” is incorporated by reference herein in its entirety.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
Referring to
The first substrate 101 may be a transparent substrate formed of, e.g., soda lime glass, or an opaque substrate formed of, e.g., colored glass or synthetic resin.
Sustain electrode pairs 105 including X electrodes 103 and Y electrodes 104 may be formed on an inner surface of the first substrate 101 extending along an x-axis direction of the PDP 100. The X electrodes 103 and the Y electrodes 104 may be alternately arranged in a y-axis direction and one sustain electrode pair including an X electrode 103 and a Y electrode 104 may be disposed in each discharge cell.
Each of the X electrodes 103 may include a first transparent electrode 106 formed on the inner surface of the first substrate 101 and a first bus electrode line 107 electrically connected to the first transparent electrode 106. The first transparent electrode 106 may have a rectangular cross-section and may be disposed in each discharge cell. The first bus electrode lines 107 may be on the first substrate 101 in a stripe pattern along the x-axis direction.
Each of the Y electrodes 104 may be symmetric with respect to the X electrode 103, and may include a second transparent electrode 108 formed on the inner surface of the first substrate 101 and a second bus electrode line 109 electrically connected to the second transparent electrode 108. The second transparent electrode 108 may have a rectangular cross-section and may be disposed in each discharge cell to face the first transparent electrode 106. The second bus electrode lines 109 may be on the first substrate 101 in a stripe pattern along the x-axis direction.
Each of the first transparent electrode 106 and the second transparent electrode 108 may be a transparent conductive layer, e.g., an indium tin oxide (ITO) layer, to improve an aperture ratio of the first substrate 101. Each of the first bus electrode line 107 and the second bus electrode line 109 may be formed of, e.g., silver (Ag) paste or a chrome-copper-chrome (Cr—Cu—Cr) alloy to improve conductivity. The first transparent electrode 106 and the second transparent electrode 108 may be disposed apart from each other by a predetermined distance at a center of each of discharge cells, thereby forming a discharge gap.
A space between one sustain electrode pair 105 disposed in one discharge cell and other sustain electrode pair 105 disposed in adjacent discharge cell may be a non-discharge area. An insulating black stripe layer (not shown) may be further formed in the non-discharge area to improve contrast.
The sustain electrode pairs 105 may be covered by a first dielectric layer 110. The first dielectric layer 110 may be formed of a glass paste containing various fillers.
A protective layer 111 may be formed of magnesium oxide (MgO) on a surface of the first dielectric layer 110 to prevent damage to the first dielectric layer 110 and to obtain a higher secondary electron emission yield.
The second substrate 102 may be formed of substantially the same material as that of the first substrate 101, and the material of the second substrate 102 may vary according to the type of PDP 100, e.g., a transmissive type or a reflective type.
Address electrodes 112 may be disposed on the inner surface of the second substrate 102 along the y-axis direction. The address electrodes 112 may be disposed to intersect the X and Y electrodes 103 and 104. The address electrodes 112 may be covered by a second dielectric layer 113.
Barrier ribs 114 may be formed between the first substrate 101 and the second substrate 102 to define discharge cells together with the first substrate 101 and the second substrate 102. The barrier ribs 114 may include a plurality of discharge barrier ribs 115 disposed in a display area and dummy barrier ribs 116 disposed in a non-display area, i.e., an area other than the display area. For example, the non-display area may be an area between the display area and an area where the sealing material 117 is located.
The discharge barrier ribs 115 may include first walls 118 intersecting the address electrodes 112, e.g., extending along the x-axis direction, and second walls 119 parallel to the address electrodes 112, e.g., extending along the y-axis direction. Since the first walls 118 and the second walls 119 may be arranged in rows and columns to intersect each other, the discharge barrier ribs 115 may be formed in a matrix pattern.
Alternatively, the discharge barrier ribs 115 may be formed in, e.g., a meander pattern, a delta pattern, or a honeycomb pattern. In this case, the discharge cells defined by the discharge barrier ribs 115 may have, e.g., polygonal, circular, or oval cross-sections.
Red, green, and blue phosphor layers 120 may be coated in the discharge space formed by the discharge barrier ribs 115 and may emit light to display an image during a discharge. The red phosphor layers may be formed of (Y,Gd)BO3:Eu3+, the green phosphor layers may be formed of Zn2SiO4:Mn2+, and the blue phosphor layers may be formed of BaMgAl10O17:Eu2+.
The dummy barrier ribs 116 disposed in the non-display area may be integrally connected to the discharge barrier ribs 115 to prevent the discharge barrier ribs 115 from being deformed when the barrier ribs 114 are patterned. For example, the dummy barrier ribs 116 may have the same form as the discharge barrier ribs 115 and may be, e.g., formed in a matrix pattern, a meander pattern, a delta pattern, or a honeycomb pattern. The cells defined by the dummy barrier ribs 116 may have, e.g., rectangular polygonal, circular, or oval cross-sections. Unlike the discharge barrier ribs 115, the red, green, and blue phosphor layers 120, however, may not be coated in a space formed by the dummy barrier ribs 116.
A discharge gas, e.g., neon (Ne)-xenon (Xe) or helium (He)-xenon (Xe), may be injected into the discharge cells defined by the first substrate 101, the second substrate 102, and the barrier ribs 114.
The absolute value of a thermal expansion coefficient difference between the second dielectric layer 113 and the sealing material 117 may be defined by a specific numerical formula to ensure that the thermal expansion coefficients sufficiently match, which will be explained in detail below.
The sealing material 117, e.g., frit glass, may be coated on a surface of the second dielectric layer 113 covering the address electrodes 112 to seal the inner space formed when the first substrate 101 and the second substrate 102 are coupled to each other.
The sealing material 117 may be coated along the edges of the inner surface of the first substrate 101 or the second substrate 102 outside the dummy barrier ribs 116, e.g., toward the edge of the first and second substrates 101 and 102, in a continuous shape. For example, the sealing material 117 may be coated along the edge of the inner surface of the second substrate 102 in the non-display area at a predetermined distance from the dummy barrier ribs 116. The sealing material 117 may be coated along an entire periphery of the first substrate 101 and the second substrate 102, e.g., may be on the second dielectric layer 113. There may be a predetermined space between the sealing material 117 and an outermost dummy barrier rib 116 from the display area, closest to the sealing material 117. The sealing material 117 may be disposed apart from the discharge barrier ribs 115 by having the dummy barrier ribs 116 therebetween. The sealing material 117 may have a height that is substantially the same as that of the barrier ribs 114. The sealing material 117 may have a width of eight to ten millimeters to maintain reliable sealing.
The second dielectric layer 113 may be formed of a lead-based material, e.g., PbO—B2O3—SiO2, having a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., a bismuth-based material, e.g., Bi2O3—B2O3—SiO2, having a thermal expansion coefficient of about 65×10−7/° C. to about 90×10−7/° C., a boron-zinc-based material, e.g., B2O3—ZnO—SiO2, having a thermal expansion coefficient of about 75×10−7/° C. to about 95×10−7/° C., or a boron-alumina-based material, e.g., B2O3—SiO2—Al2O3, having a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
The sealing material 117 may be formed of a lead-based material, e.g., PbO, having a thermal expansion coefficient of about 60×10−7/° C. to about 85×10−7/° C., or a bismuth-based material, e.g., Bi2O3, having a thermal expansion coefficient of about 70×10−7/° C. to about 90×10−7/° C.
A thermal expansion coefficient difference between the second dielectric layer 113 and the sealing material 117 may satisfy below Formula 1
|thermal expansion coefficient of second dielectric layer−thermal expansion coefficient of sealing material|≦13×10-7/° C. (1).
A defect that frequently occurs in the multi-cutting process technology, which is used in manufacturing of a PDP to improve efficiency, may be warping of a panel. In particular, the substrates are often damaged due to thermal expansion coefficient mismatch between sealing material, e.g., frit glass, which may be the thickest pattern layer, and a dielectric layer disposed under the frit glass.
Once thermal expansion coefficient mismatch occurs between the frit glass and the dielectric layer, the substrates may be damaged during a baking process of the frit glass, may be damaged due to a temperature difference between a panel effective part and a panel outskirt part during an aging process, and may be damaged due to a pressure applied during electrical connection between a signal transmitting unit and discharge electrodes.
Accordingly, it may be very important to ensure appropriate thermal expansion coefficient match between the frit glass and the dielectric layer to reduce damage during the processes. Also, as interest in restricting the use of hazardous substances has been recently increased, lead-free materials are being developed. Even using a lead-free material, a thermal expansion coefficient should be one of the factors to be deliberately considered in selecting the material.
If an absolute value of the thermal expansion coefficient difference between the second dielectric layer 113 and the sealing material 117 satisfies Formula 1, damage to the first substrate 101 or the second substrate 102 during a baking process of the sealing material 117, damage to the PDP 100 during an aging process, and/or damage during electrical connection between a signal transmitting unit and the discharge electrodes may be reduced or prevented.
Experiments were conducted to determine the effect of thermal expansion coefficient mismatch between a second dielectric layer and a sealing material, and results thereof are shown in Table 1.
The experiments were performed by checking for damage to a substrate during a baking process of the sealing material, damage to a PDP during an aging process, and damage during electrical connection between a signal transmitting unit and discharge electrodes as a thermal expansion coefficient difference between the second dielectric layer and the sealing material was changed.
Referring to Table 1, when the absolute value of the thermal expansion coefficient difference between the second dielectric layer and the sealing material was equal to or less than 13, only one damaged case occurred, thereby ensuring good process yield. Accordingly, if the absolute value of the thermal expansion coefficient difference between the second dielectric layer and the sealing material was equal to or less than 13, damage due to thermal expansion coefficient mismatch between the second dielectric layer and the sealing material may be prevented.
Experiments were conducted to determine if damage to the substrate would occur when the materials of the second dielectric layer and the sealing material were changed, thereby changing the absolute value of thermal expansion coefficient difference between the second dielectric layer and the sealing material, and results thereof are shown in Table 2.
Referring to Table 2, when the absolute value of a thermal expansion coefficient difference between the second dielectric layer and the sealing material was equal to or less than 13, the substrate was not damaged. When the absolute value of the thermal expansion coefficient difference between the second dielectric layer and the sealing material was greater than 13, as in the comparative examples 1 and 2, both substrates were damaged.
As described above, the PDP according to the present embodiment may reduce or prevent damage due to thermal expansion coefficient mismatch between the dielectric layer and the sealing material by allowing the absolute value of the thermal expansion coefficient difference between the second dielectric layer and the sealing material to be defined by a specific numerical formula.
Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2008-0110012 | Nov 2008 | KR | national |
