Patent Application
20140331237
Currently, operating system (OS) and software application stacks are integrally tied to the platform architecture on which they execute. Consequently, the corresponding back-end architecture must be developed, based on, and starting with, the application programming interfaces (APIs) and instruction sets specific to the particular platform. Unless the native hardware and instruction set is somehow modified to accommodate the needs of the application/OS stacks, the platform may not be viable.
If a legacy application relies on a legacy instruction set architecture (ISA), the platforms and operating systems of today have no way to support it other than natively, which only increases the demands by both sides, resulting in any of a number of negative consequences such as a decrease in efficiency and an increase in power consumption, for example.
Thus, there remains a need for improved hardware/software architectures, particularly with regard to middleware resident therebetween.
Embodiments of the disclosed technology are illustrated by way of example, and not by way of limitation, in the drawings and in which like reference numerals refer to similar elements.
Certain embodiments of the disclosed technology allow applications developed for specific hardware and/or instruction set architectures (ISAs) to be viable, e.g., supported, independent of the type of hardware platform on which they must execute. Such embodiments may serve to eliminate the hardware design specificity and, in some cases, the corresponding overhead, required to support applications that rely on the corresponding hardware and/or ISAs.
Certain implementations include leveraging a flexible, adaptable, and easily modifiable binary emulator to act as the translator between high level application/OS stacks and the corresponding platform hardware architecture, From the perspective of the applications running on the platform, this middleware layer may abstract out the hardware and provide either a universal, e.g., standardized, interface or a programmable emulator interface with which they may communicate. Such embodiments enable the applications to interact with the native hardware on the platform regardless of whether it is an ARM or IA ISA, for example, or virtually any other type of architecture.
Certain implementations may allow for all corresponding applications to be portable regardless of the underlying platform architecture, e.g., ARM or some other type of architecture. Implementations may allow platform hardware designs to shed legacy support, e.g., implemented in hardware, and be essentially unencumbered as they strive for continuous performance improvements through hardware evolution/redesign.
Application stack developers may rely on interface options provided by a middleware layer in accordance with the disclosed technology to communicate with the back-end hardware. Those interface options may include new universal standard instruction sets or, in the case of current ISAs, improved portability of applications associated therewith.
Certain implementations of the disclosed technology may include emulating certain types of functionality rather than implementing such functionality natively. A processor in such an architecture may have enough processing power, e.g., as measured in terms of central processing unit (CPU) and/or graphics processing unit (GPU) capabilities, to emulate an ARM ISA, for example. In this context, binary emulators may be considered middleware.
In certain embodiments involving smaller cores, e.g., minute architectures, instructions having longer latencies may be offloaded to an emulator in order to facilitate a tradeoff in terms of functionality and/or performance. Such embodiments may include a mechanism for offloading legacy ISAs, e.g., x87 ISAs, foreign ISAs, and/or less frequently executed ISAs while maintaining a compatibility layer within middleware. These implementations my be extended to scenarios including the emulation of RS-232 protocols over a universal serial bus (USB) connection to reduce the number of legacy ports, for example.
In the example, the binary emulator middleware 220 may become a piece of the high-level software stack 210 and thus have any or all of the advantages associated with traditional software, such as flexibility, programmability, and quick turn-around, for example, without the overhead of having to redesign the native hardware platform 230 to support new and/or multiple instruction sets or to improve performance.
In certain embodiments, the middleware layer 220 may enable ARM-based applications to run on other architectures and vice-versa, thus resulting in improved interoperability of both applications and platforms. This may translate to a broadened applicability of platforms, applications, and, ultimately, the number of choices available to the consumer.
In certain implementations, the architecture 200 may allow for offloading the handling of legacy ISAs or low performance ISAs to the middleware 220 in order to free the architecture 200 to target newer performance goals without being encumbered, for example.
The device 400 includes a housing 402, a display 404 in association with the housing 402, an input mechanism 406 in association with the housing 402, a processor 408 within the housing 402, and a memory 410 within the housing 402. The input mechanism 406 may include a physical device, such as a keyboard, or a virtual device, such as a virtual keypad implemented within a touchscreen. The processor 408 may perform virtually any of a number of operations such as those described above. The memory 410 may store information resulting from processing performed by the processor 408.
The system 500 also includes three mobile electronic devices 508-512. Two of the mobile electronic devices 508 and 510 are communications devices such as cellular telephones or smartphones. Another of the mobile devices 512 is a handheld computing device such as a personal digital assistant (PDA) or tablet device. A remote storage device 514 may store some of all of the data that is accessed and used by any of the computers 504 and 506 or mobile electronic devices 508-512.
In certain implementations, a platform-independent hardware/software architecture, such as the architecture 200 of
Embodiments of the disclosed technology may be incorporated in various types of architectures. For example, certain embodiments may be implemented as any of or a combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, a graphics and/or video processor, a multicore processor, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The term “logic” as used herein may include, by way of example, software, hardware, or any combination thereof.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the embodiments of the disclosed technology. This application is intended to cover any adaptations or variations of the embodiments illustrated and described herein. Therefore, it is manifestly intended that embodiments of the disclosed technology be limited only by the following claims and equivalents thereof.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US11/68227 | 12/30/2011 | WO | 00 | 6/25/2013 |
