The present invention relates to using a single platform semiconductor device to generate a large number of products. More specifically, the present invention relates to using a single platform semiconductor device for the mass customization of a variety of different semiconductor devices with different functional characteristics.
A semiconductor company that produces microcontrollers and other related semiconductor products will typically have a large number of products with minor feature differences. To maximize the utilization of the manufacturing process, it is desirable to build a single semiconductor device that incorporated all features of the various products. And, then program the semiconductor device with the appropriate feature set before shipping the device to the customer. The STELLARIS family of microcontrollers by Luminary Micro, Inc. (Luminary Micro), the assignee of the disclosure, use the ARM Cortex M3 Intellectual Property (IP) core. In order to build a family of parts from a single die, the peripherals built around the ARM Cortex M3 core need to be able to connect to different GPIO ports depending on the configuration of the specific part. This disclosure describes the process where Luminary Micro uses a single semiconductor platform die to generate a large number of products.
This application claims the benefits of the earlier filed U.S. Provisional Application Ser. No. 60/869,841, filed 13 Dec. 2006, which is incorporated by reference for all purposes into this specification.
This disclosure describes a configuration data structure that describes the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The configuration data structure comprises a device identification member, a peripheral enable member, an alternate function select member, a port bonding specification member, and a resource specification member.
This disclosure also describes a system that specifies and controls the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The system comprises the following one or more internal peripheral buses, one or more peripherals coupled to the internal peripheral bus, a functional I/O mux coupled to the peripherals, a configuration data structure that couples to the functional I/O mux, and a GPIO coupled to the functional I/O mux.
To further aid in understanding the invention, the attached drawings help illustrate specific features of the invention and the following is a brief description of the attached drawings:
This disclosure describes a single platform semiconductor device for the mass customization of a variety of different semiconductor devices with different functional characteristics. This disclosure describes numerous specific details in order to provide a thorough understanding of the present invention. For example, this disclosure describes a data structure residing in non-volatile memory, one-time programmed, that describes the functional characteristics of the underlying silicon platform. One skilled in the art will appreciate that one may practice the present invention without these specific details. Additionally, this disclosure does not describe some well known items in detail in order not to obscure the present invention.
The STELLARIS family of microcontrollers by Luminary Micro use the ARM Cortex M3 Intellectual Property (IP) core. To achieve a high utilization of manufacturing resources, the STELLARIS family of microcontrollers use a single die for multiple products. Products in the family are differentiated from each other through the contents of an on-chip, non-volatile configuration memory that specifies the features included in the final product. As an example, product features may include GPIOs, one or more peripheral devices, FLASH (non-volatile) memory, SRAM (volatile) memory, and Analog to Digital Converters (ADC) and associated sample rates. The configuration memory is programmed after the chip has been assembled, and the configuration memory assigns each chip to a product. One skilled in the art will appreciate that portion of the configuration memory may or may be accessible to the end user of the product
In one embodiment, the non-volatile configuration memory may comprise FLASH memory. One skilled in the art will appreciate that other types of non-volatile memory may be used other than FLASH memory such as EEPROMs or fuses.
In general, the organization of the configuration data structure 100 is such that the data width of the configuration memory matches that of the natural data width of the processor, which in the STELLARIS family of microcontrollers, for example, is 32-bits. Padding of the configuration data structure may be inserted where appropriate to align the configuration data structure to the same data granularity.
The configuration data structure 100 in one embodiment is a separate, small block of memory that resides in the main configuration memory (or the main non-volatile memory storage) in the semiconductor device. The size of the configuration data structure depends upon the total number of integrated peripherals and system features.
The configuration data structure 100 enables the desired peripherals and features on a particular product. Using the configuration data structure 100 allows different parts to be created from a single platform die without giving the end customer the ability to use peripherals or features that are not provided on that product or part. The flexibility of the configuration data structure 100 also provides for multiple peripherals or features to use a limited number of package pins since the number of peripheral signals that want to drive or be driven by an external signal typically exceeds the number of pins on the product packages. Thus, not all peripherals can be bonded out on any particular part so several pads are assigned to more than one peripheral and the configuration data structure 100 determines which of the peripherals are actually able to use the pad. In one embodiment one the invention, when one bit of the configuration data structure 100 is set to one, the peripheral is enabled and allowed to function. When set to zero, the peripheral is disabled and does not function. And, peripherals that simply do not exist on the die have their corresponding bits set to zero.
During the initial power on configuration or later reset of the configuration data structure 100, a state machine copies the programmed values of the configuration data structure from the configuration memory. The state machine generates read access cycles to the configuration memory and copies the returned data values to internal registers (or flip flops). The registers are of two classes: one class is made available to the end-user for use by software and provides configuration information, and the other class are connected directly to peripherals and features and are not accessible to software. These register bits then connect to their applicable peripherals and functional units to control their operation. One skilled in the art will appreciate the state machine could be part of a power on loader or load sequence that initially configures the product for use. In addition, one skilled in the art will appreciate that the end user of the product may or may not have access to the state machine during the initial power on figuration or later reset. Further, one skilled in the art will appreciate that the internal registers may reside anywhere in the design.
One skilled in the art will appreciate that the value of each peripheral enable bit may be used to control the availability of a peripheral by a number of methods. These methods include, for example, disabling power to the peripheral, disabling clocks to the peripheral, holding the peripheral in reset, and preventing read/write access to the peripheral by disabling the address decode of the peripheral.
One embodiment of the invention comprises information for the peripherals as follows: Timers (Timer0-Timer7), SSIs (SSI0-SSI3), UARTs (UART0-UART3), Comparators (Compartor0-Comparator7), QEIs (QEI0-QEI3), I2Cs (I2C0-I2C3), ADCs (ADC0-ADC3) with data ports (pADC0-pADC15), PWMs (PWM0-PWM3) with data ports (pPWM0-pPWM15), Ports (PortA-PortH). In addition, this embodiment includes information for other peripherals that include: MPU, DCWR, TempSensor, PLL, WatchDogTimer, SWT, SWD, and JTAG.
The ARM GPIO structure 200 includes the peripheral data bus 201 that couples to a individual peripheral 202 and GPIO 212. The alternate function interface couples the peripheral 202 to GPIO 212 with the following control signals peripheral input 208, peripheral output 206, and peripheral direction 204. The GPIO 212 contains a control register 214, a data register 216, a direction register 218, and multiplexors 220 and 222. The GPIO 212 couples to the driver interface 230 with data in 228, data out 226, and direction signal 224. The driver interface 230 couples to bond pad 234 through connection 232.
In a given product there is one alternate signal provided as the alternate function for each pin. However, the product-specific alternative is the result of selecting among a set of platform alternatives. The selection is specified in the configuration data structure 100 in the alternate function select member 112. Each pin has an encoded bit field that describes which peripheral signal is designated as the alternate function for the GPIO, and it is connected to the corresponding GPIO port through the functional I/O mux 302. The functional I/O mux 302 couples to the configuration data structure 100 via internal registers as previously described. The alternate function bit fields are copied from the configuration memory at reset and stored in user-inaccessible registers in the functional I/O mux 302 (N:1 MUXs and N:1 DEMUX).
One embodiment of the invention is system 300 that includes the peripheral data bus 201 that couples to an N number of peripherals 320 through 326. Peripheral data bus 201 additionally couples to GPIO 212. Each peripheral 320 through 326 includes its own input, output, and direction signal. The functional I/O mux 302 couples the input/output/direction signal of peripherals 320-326 to the following control signals GPIO 212: peripheral input 208, peripheral output 206, and peripheral direction 204. The GPIO 212 couples to the driver interface 230 with data in 228, data out 226, and direction signal 224. The driver interface 230 couples to bond pad 234 through connection 232.
To summarize, this disclosure describes a configuration data structure that describes the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The configuration data structure comprises a device identification member, a peripheral enable member, an alternate function select member, a port bonding specification member, and a resource specification member.
This disclosure also describes a system that specifies and controls the functional characteristics of a single semiconductor device during the mass customization of semiconductor devices. The system comprises the following: one or more internal peripheral buses; one or more peripherals coupled to the internal peripheral buses; a functional I/O mux coupled to the peripherals; a configuration data structure that describes the functional characteristics of a semiconductor device that couples to the functional I/O mux; and a GPIO coupled to the functional I/O mux.
Other embodiments of the invention will be apparent to those skilled in the art after considering this specification or practicing the disclosed invention. The specification and examples above are exemplary only, with the true scope of the invention being indicated by the following claims.
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/US07/87133 | 12/12/2007 | WO | 00 | 4/20/2009 |
Number | Date | Country | |
---|---|---|---|
60869841 | Dec 2006 | US |