Patent Application
20080019336
As noted above, the methods and systems described herein multiplex bidirectional data over a bidirectional PTP communication link such that each communication system either transmits or receives at any particular point in time, but not simultaneously. At each system, transmission and reception use different frequencies. The communication links described hereinbelow are usually deployed in licensed FDD spectrum.
Unlike some known FDD links in which each communication system transmits and receives continually over respective transmit and receive frequencies, the communication systems described herein are constrained to transmit at a partial duty-cycle, alternating between transmission and reception. Since at any given time at least one frequency band is unused, the transmission time available to each link direction is reduced, which may reduce the spectral efficiency and the capacity of the link. On the other hand, the constraint of not allowing simultaneous transmission and reception enables connecting the system's transmitter and receiver to the antenna without a diplexer. Eliminating the diplexer reduces the cost, size and complexity of the system, and also offers better operational flexibility.
The reduced link capacity is re-gained using other means, depending on the specific application. For example, when the links described herein are operated in a licensed FDD band, it may not be possible to increase the symbol rate of the link to compensate for the reduced duty-cycle, because of the constrained bandwidth allocation. Therefore, in some embodiments, the links described below re-gain the capacity by using modulation schemes having higher spectral efficiencies.
However, high spectral efficiency modulation schemes are often characterized by small Euclidean distances, which degrade the error performance and/or the communication range of the link. In order to compensate for this degradation, some embodiments of the present invention use additional measures, such as high-performance forward error correction (FEC), peak-to-average ratio (PAR) reduction and predistortion of the transmitted signal, and/or improved digital carrier recovery.
Link 20 comprises a bidirectional link, in which data is transferred both from system 24A to system 24B and in the opposite direction. The two directions of the link may be symmetrical, i.e., transferring the same data rate, or asymmetrical, i.e., transferring different data rates.
Unlike some known methods and systems that use either TDD or FDD, the two directions of link 20 are multiplexed in time division and transmitted over two different radio frequencies. In other words, each communication system either transmits or receives at any given time, but does not transmit and receive simultaneously. At each communication system, transmission and reception use different frequencies. As a result, the spectral efficiency of the link is reduced. The reduction in spectral efficiency is compensated for using means that are described hereinbelow.
Since a given communication system does not transmit and receive simultaneously, the system does not need to use a diplexer in order to connect the transmitter and receiver to the antenna. Eliminating the diplexer reduces the cost, size and complexity of the system. Additionally, eliminating the diplexer provides better operational flexibility in selecting and changing transmission and reception frequencies. In some cases, eliminating the diplexer reduces the insertion loss of both the transmitted and the received signals.
Since each communication system transmits and receives on different frequencies, link 20 can be operated in licensed frequency bands that are allocated to FDD links. Some of these frequency bands are dedicated to FDD PTP links. For example, FDD PTP spectrum is allocated in the 13, 15, 18, 23, and 38 GHz bands. FDD PTP channels are typically allocated in pairs of transmit and receive frequencies. Links operating in these bands comprise, for example, cellular backhaul links and links for bridging remote data networks.
From a regulatory standpoint, link 20 qualifies both as a TDD and an FDD link. Therefore, the link can be deployed in any suitable licensed frequency band. Alternatively, link 20 may use unlicensed spectrum, as well.
Systems 24A and 24B alternate between transmission and reception in accordance with a repetitive frame structure. The time domain is divided into a sequence of frames 32, which are sub-divided into time intervals referred to as slots. Frames 32 are divided into respective first slots 36 and second slots 40. During first time slots 36, system 24A transmits data and system 24B receives the transmitted data over frequency F1. During second time slots 40, system 24B transmits data and system 24A receives the transmitted data over frequency F2. (Usually, frames 32 additionally comprise guard time intervals for accounting for the propagation delay between systems 24A and 24B. The guard time intervals are omitted from the figure for clarity.)
The length of frames 32 is typically in the range of 100 microseconds to 3 milliseconds, although other frame lengths can also be used. The first and second time slots can be of equal lengths or different lengths. The exemplary frame structure of
As demonstrated by
However, high spectral efficiency modulation schemes are often characterized by relatively small Euclidean distances, which degrade the noise and distortion immunity of the link. As a result, the achievable error performance and/or the communication range of the link are typically degraded when using such modulation schemes. In some embodiments, systems 24 comprise one or more mechanisms for improving the link performance in order to compensate for the reduced performance of the modulation scheme. Such performance-improving mechanisms may comprise, for example, high performance forward error correction (FEC), reduction of the peak-to-average ratio (PAR) of the transmitted signal, improved digital carrier recovery and pre-distortion of the transmitted signal. These mechanisms are described in greater detail below.
The encoded data is modulated by a modulator 54, which produces a sequence of transmitted symbols responsively to bits of data. Modulator 54 maps data bits to symbols selected from a predetermined symbol constellation. As noted above, the modulator uses a high spectral efficiency modulation scheme. The high spectral efficiency is typically achieved by mapping multiple data bits onto each transmitted symbol. For example, modulator 54 may use quaternary phase shift keying (QPSK) modulation (two bits per symbol), 16 symbol quadrature-amplitude modulation (16-QAM, four bits per symbol), 64-QAM (six bits per symbol) or any other suitable modulation scheme. In some embodiments, modulator 54 can use orthogonal frequency division multiplexing (OFDM) or other multi-carrier modulation.
In many practical cases, the sequence of transmitted symbols produced by modulator 54 has an instantaneous power which varies significantly over time. These instantaneous power variations can be expressed in terms of the peak-to-average ratio (PAR), also known as crest factor, which is defined as the ratio between the maximum instantaneous power and the average power of the signal at the modulator output. High PAR values typically degrade the link performance by causing non-linear distortion in various transmitter and/or receiver circuits during periods of large instantaneous signal power. In particular, high PAR values limit the operating point of the transmitter's power amplifier, thus reducing its output power and efficiency.
In some embodiments, system 24 comprises a PAR reduction module 56, which reduces the PAR of the signal produced by modulator 54. Numerous methods and several devices for reducing PAR are known in the art, and any suitable method or device can be used for this purpose.
In some embodiments, system 24 comprises a predistortion (PD) module 58, which predistorts the signal before transmission in order to compensate for non-linear effects of the transmitter, particularly of the transmitter power amplifier. Predistortion may be applied using digital and/or analog circuitry. Predistorting the transmitted signal improves the linearity of the transmitter and enables it to provide a higher output power and better efficiency. Predistortion may be performed either in combination with or separately from PAR reduction.
Various predistortion methods and devices known in the art can be used for implementing PD module 58. For example, Karam and Sari describe three types of predistortion schemes applied to 64-QAM and 256-QAM digital microwave radio systems in “Analysis of predistortion, equalization, and ISI cancellation techniques in digital radio systems with nonlinear transmit amplifiers,” IEEE transactions on Communications (37:12), December, 1989, pages 1245-1253, which is incorporated herein by reference. Another paper by Karam and Sari entitled “A data predistortion technique with memory for QAM radio systems,” IEEE transactions on Communications (39:2), February, 2001, pages 336-344, which is incorporated herein by reference, describes a predistortion technique with memory for compensating for high power amplifier (HPA) nonlinearities in digital microwave radio systems. Some predistortion methods apply a polynomial function to the transmitted signal. The polynomial coefficients (e.g., the linear, third and fifth orders) determine the predistortion characteristics.
The predistorted signal is converted to an analog signal using a digital-to-analog converter (not shown) and then up-converted to an appropriate transmit frequency by an up-converter 60, and amplified by a power amplifier (PA) 62. The amplified signal is then fed via a Transmit/Receive (T/R) switch 64 to antenna 28 and transmitted over the wireless channel. As noted above, system 24 alternates between transmission and reception. During transmission, T/R switch 64 connects PA 62 to the antenna.
During reception, T/R switch connects antenna 28 to a down-converter 66, which down-converts the received radio signal to a suitable baseband or intermediate frequency (IF). The down-converted signal is processed by a receiver front end (FE) 67. The FE samples the signal using an analog-to-digital converter and performs functions such as synchronization, equalization, carrier recovery, gain control, and matched filtering. FE 67 produces a stream of digitally-represented received symbols. A demodulator 68 demodulates the received symbols to produce a stream of encoded data bits. A FEC decoder 70 decodes the FEC-encoded data.
The elements of system 24 related to signal transmission, in the present example comprising elements 50-62 of
In an alternative embodiment, the transmitter and receiver may be connected to the antenna using a power divider or similar device, without using a T/R switch. The insertion loss of these configurations is typically higher with respect to configurations that use a T/R switch.
It should be noted that since system 24 alternates between transmission and reception, the received signal is received intermittently during discontinuous time slots. Therefore, the receiver, and in particular FE 67, should be capable of receiving such a bursty signal. For example, adaptive receiver loops such as synchronization and carrier recovery loops in FE 67 should either remain locked between successive reception time slots, or be able to resume their lock rapidly at the beginning of a new reception time slot.
In some embodiments, a rapid carrier recovery loop may be implemented using pilot signals. In these embodiments, the transmitter transmits one or more pilot signals or symbols, which are used by the receiver to recover the phase (and hence the frequency) of the transmitter carrier. Carrier recovery loops based on pilot signals are described, for example, in U.S. Pat. No. 6,965,633, whose disclosure is incorporated herein by reference, and in a paper by Gansman et al., entitled “Optimum and suboptimum frame synchronization for pilot-symbol-assisted modulation,” IEEE transactions on communication (45:10), October, 1997, pages 1327-1337, which is incorporated herein by reference. Alternatively, any other suitable carrier recovery method can be used.
In some embodiments, for example when the FEC code comprises an LDPC or turbo code, decoder 70 uses an iterative decoding process. Iterative FEC decoding processes are described, for example, by Worthen and Stark in “Unified Design of Iterative Receivers using Factor Graphs,” IEEE Transactions on Information Theory, (47:2), February, 2001, pages 843-849, and by Richardson and Urbanke in “An Introduction to the Analysis of Iterative Coding Systems,” Proceedings of the 1999 Institute for Mathematics and its Applications (IMA) Summer program: Codes, Systems and Graphical Models, Minneapolis, Minn., Aug. 2-6, 1999, which are incorporated herein by reference.
A de-framer 72 converts the blocks of data produced by the iterative decoder to a continuous stream of data and provides the stream as output data. A timing and control module 74 controls the different elements of systems 24. In particular, module 74 provides the timing signals for alternating between transmission and reception. In some embodiments, module 74 may control T/R switch 64, set the transmission and reception frequencies of the system, and/or provide clock, timing, and other signals to up-converter 60 and down-converter 66.
The system configuration of
In general, the two directions of a particular link need not necessarily have the same configuration. For example, the two link directions may use different FEC codes, different modulation schemes and/or different data rates. Each direction may or may not use PAR and/or predistortion, independently of the opposite direction. In each direction, the modulation scheme and/or FEC code used may vary over time, for example in order to match the current channel conditions.
Systems 24A and 24B accept data for transmission to one another, at a data input step 84. Each system encodes its data using FEC and modulates the encoded data, at an encoding and modulation step 88. Each system applies PAR reduction and/or predistortion, at a predistortion step 92. Each system performs up-conversion and power amplification, to produce a radio signal.
Systems 24A and 24B transmit their respective radio signals to one another, at a transmission step 96. As described above, system 24A transmits data to system 24B during first time slots 36 over frequency F1, and system 24B transmits data to system 24A during second time slots 40 over frequency F2. Each system alternates between transmission and reception on the appropriate frequencies, in accordance with the frame structure defined at step 80 above.
Systems 24A and 24B receive the respective radio signals, at a reception step 100. The signals are down-converted and sampled. The systems demodulate and decode the received symbols, at a demodulation and decoding step 104. Each system outputs the decoded data, at an output step 108.
It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.
