Patent Application
20220224358
This application claims the priority benefit of Taiwan application serial no. 110101426, filed on Jan. 14, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
This disclosure relates to a decoder, and in particular to a polar code decoding apparatus and an operation method thereof.
Polar codes are a type of forward error correction coding. The encoding method of the polar codes has been proven to achieve Shannon capacity. The polar codes have been adopted by the Third Generation Partnership Project (3GPP) as the coding for controlling channels in the fifth generation (5G) mobile communication technology. Main coding for the polar codes includes the Successive cancellation list (SCL) algorithm and the Belief propagation algorithm. SCL-based polar codes use list-based successive cancellation decoding algorithm to perform decoding. Although it can achieve good decoding results, it is not conducive for parallelization, and complexity of hardware implementation and decoding time delay are higher. Node-wise SCL decoding or multi-bit SCL decoding may decode multiple bits concurrently, which effectively reduces the complexity and the decoding delay. Therefore, they have become the main hardware implementation manners of the SCL-based polar codes.
An encoded bit string generates polarization of the channels after the polar codes are encoded, which enables some of the channels to become very reliable, while concurrently causing other channels to become very unreliable. Information (information bits, that is, bits with unknown values) that is to be transmitted may be placed on the reliable channels, and known information (frozen bits, that is, bits with known values) may be placed on the unreliable channels. For example, the value of the frozen bit may be fixed to logic “0”.
The successive cancellation list decoding method based on nodes, divides the bit string into multiple sub-bit strings, and each of the sub-bit strings may be regarded as a node. The decoding hardware may process one node (one sub-bit string) at a time. The Fast simplified SCL (Fast-SCCL) algorithm may be applied to the decoder in order to reduce the complexity. Each node is classified into at least four types of nodes based on the number and distribution of its information bits, such as a Rate-0 node, a Rep node, a Rate-1 node and a single parity check (SPC) node. In the Rate-0 node, each bit is a frozen bit. In the Rep node, only the last bit is an information bit, while the remaining bits are frozen bits. In the Rate-1 node, each bit is an information bit. In the SPC node, only the first bit is a frozen bit, while the remaining bits are information bits. Nodes of the same type have the same decoding process. Nodes that cannot be classified into the four types are called maximum likelihood (ML) nodes.
During the node-wise successive cancellation list decoding, assume that the list size is L and the path expanding number is E. That is, each expansion of the L paths is E candidate paths. During the processing of each of the nodes, a conventional decoder have to select a best L path from E*L expanded paths (candidate paths). A path expanding number E of each of the nodes may not be the same. In general, the size of the path expanding number E is between 1 and 21, where I is the information bit number contained in the node. In the conventional technology, the nodes of the same type have the same decoding process, and each of the nodes has the same path expanding number E, regardless of the position of the node.
In order to perform a path competition operation on the E*L candidate paths, an E*L-to-L sorter is generally required. A lot of hardware resources and time are consumed to implement the E*L-to-L sorter. Therefore, in practice, an E−1 path competition operation is executed through a 2L-to-L sorter in the conventional technology to achieve “the path competition operation being performed on the E*L candidate paths”.
The information bit numbers contained in the Rate-0 node and the Rep node are 0 and 1. Therefore, the Rate-0 node and the Rep node are easy to process. As for the Rate-1 node and the SPC node having many information bits, a lot of time is consumed if a 2L-to-L sorter is used to perform the E−1 path competition operation. Therefore, restrictions are imposed on the Rate-1 node and the SPC node in the conventional technology, even if the path expanding number E of the Rate-1 node and the SPC node are respectively equal to 2min(L-1,M) and 2min(L,M-1), where L is the list size, and M is the node size (the bit number of the node).
During the path competition operation, the conventional decoder uses path metric value (PM) to measure the reliability of the candidate path. In the hardware implementation, a clock frequency mainly depends on a length of a critical path. In a conventional polar code decoder, the critical path is often located in the process of “calculating and sorting the path metric values”. If this part can be optimized, the clock frequency may be further increased, thereby increasing throughput of communication transmission.
It should be noted that the content in the “related art” is used to facilitate understanding of the disclosure. Part of the content (or all of the content) disclosed in the “related art” may not be the conventional technology known to those with ordinary knowledge in the technical field. The content disclosed in the “related art” does not mean that the content has been known to those with ordinary knowledge in the technical field before the patent application.
This disclosure provides a polar code decoding apparatus and an operation method thereof to perform polar code decoding on an encoded bit string.
In an embodiment of the disclosure, the polar code decoding apparatus includes a path expanding circuit and a node processing circuit. The path expanding circuit is configured to expand each of multiple previous paths corresponding to multiple previous decoding results into multiple candidate paths according to a current node. The encoded bit string is divided into multiple sub-bit strings to serve as multiple nodes including the current node. The path expanding circuit is configured to dynamically determine a path expanding number of the candidate paths for each of the previous paths according to an unreliable information bit number of the current node. The node processing circuit is coupled to the path expanding circuit. The node processing circuit is configured to perform a path competition operation to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results.
In an embodiment of the disclosure, the operation method includes the following steps. Each of multiple previous paths corresponding to multiple previous decoding results is expanded into multiple candidate paths by a path expanding circuit according to a current node. A path expanding number of the candidate paths of each of the previous paths is dynamically determined by the path expanding circuit according to an unreliable information bit number of the current node. A path competition operation is performed by a node processing circuit to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results.
Based on the foregoing, the polar code decoding apparatus and the operation method thereof according to the embodiments of the disclosure can optimize the efficiency of polar code decoding to a maximum extent. The nodes at the different positions will have different reliabilities. The term “reliability” is an inherent difference caused by the polarization of the polar code channels. A node containing many reliable information bits is not required to expand into many candidate paths. In the case where “nodes with different reliabilities have the same path expanding number”, the path expanding circuit may perform expansion of redundant paths (expand out into redundant candidate paths). It is conceivable that the redundant candidate paths will increase the hardware complexity and decoding delay. Therefore, in some embodiments, the path expanding circuit may dynamically determine the path expanding number of each of the previous paths according to the unreliable information bit number of the current node, so as to reduce the redundant candidate paths as much as possible.
In an embodiment of the disclosure, the polar code decoding apparatus includes a path expanding circuit and a node processing circuit. The path expanding circuit is configured to expand each of multiple previous paths corresponding to multiple previous decoding results into multiple candidate paths according to a current node. The node processing circuit is coupled to the path expanding circuit. The node processing circuit is configured to perform a path competition operation to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results. The path competition operation performed by the node processing circuit includes selecting some paths from the candidate paths to serve as the current paths according to a path metric value of each of the previous paths and a log-likelihood ratio (LLR) value of each of multiple bits of the current node.
In an embodiment of the disclosure, the operation method includes the following steps. Each of multiple previous paths corresponding to multiple previous decoding results is expanded into multiple candidate paths by a path expanding circuit according to a current node. A path competition operation is performed by the node processing circuit to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results. The path competition operation performed by the node processing circuit includes selecting some paths from the candidate paths to serve as the current paths according to a path metric value of each of the previous paths and a LLR value of each of multiple bits of the current node.
Based on the foregoing, the polar code decoding apparatus and the operation method thereof according to the embodiments of the disclosure can optimize the efficiency of polar code decoding to a maximum extent. The node processing circuit has to process all of the candidate paths when the node processing circuit performs the path competition operation in an irregular manner. The polar code decoding apparatus may preferentially select a more reliable candidate path to undergo the path competition operation according to the path metric values of the previous paths and the LLR value of the current node. The LLR value here is the LLR value of each dynamic bit received by the node from the channel end. For example, some embodiments may perform offline statistical analysis on the node according to the bit reliability, so as to sort the flipping pattern that is more likely to be the correct path in the position prioritized for sorting. The polar code decoding apparatus may determine the path to be compared in the next stage according to the flipping pattern and the surviving path from the previous stage. Therefore, the polar code decoding apparatus can accurately and efficiently find out which of the candidate paths are more likely to be the correct paths.
In an embodiment of the disclosure, the polar code decoding apparatus includes a path expanding circuit and a node processing circuit. The path expanding circuit is configured to expand each of multiple previous paths corresponding to multiple previous decoding results into multiple candidate paths according to a current node. The node processing circuit is configured to perform a path competition operation to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results. The path competition operation performed by the node processing circuit includes the following steps. At least one candidate path is selected from the candidate paths of each of the previous paths to serve as multiple first candidate paths. A path metric value of each of the first candidate paths is calculated. Some paths are selected from the first candidate paths to serve as multiple first surviving paths according to the path metric values of the first candidate paths. A normalization operation is performed on the path metric values of multiple final surviving paths.
In an embodiment of the disclosure, the operation method includes the following steps. Each of multiple previous paths corresponding to multiple previous decoding results is expanded into multiple candidate paths by a path expanding circuit according to a current node. A path competition operation is performed by a node processing circuit to select some paths from the candidate paths to serve as multiple current paths corresponding to multiple current decoding results. The path competition operation performed by the node processing circuit includes the following steps. At least one candidate path is selected from the candidate paths of each of the previous paths to serve as multiple first candidate paths. A path metric value of each of the first candidate paths is calculated. Some paths are selected from the first candidate paths to serve as multiple first surviving paths according to the path metric values of the first candidate paths. A normalization operation is performed on the path metric values of multiple final surviving paths.
Based on the foregoing, the polar code decoding apparatus and the operation method thereof according to the embodiments of the disclosure can optimize the efficiency of polar code decoding to a maximum extent. The length of the critical path is related to the bit number of the path metric value. In some embodiments, the node processing circuit may perform the normalization operation on the path metric value of the candidate path (the final surviving path) that survives the last stage to reduce the bit number of the path metric value. In other embodiments, the node processing circuit may perform the normalization operation on the path metric value of the candidate path that survives each stage to reduce the bit number of the path metric value.
To make the abovementioned more comprehensible, several embodiments accompanied by drawings are described in detail as follows.
The terms “coupled” or “connected” used in the full text of this specification (including the scope of the patent application) can refer to any direct or indirect means of connection. For example, if the first device is being described as coupled (or connected) to the second device, it should be interpreted as that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through another device or some types of connection means. Terms such as “first” and “second” mentioned in the specification (including the scope of the patent application) are used to name the elements, or to distinguish between different embodiments or ranges, and are not intended to limit an upper limit or a lower limit of the number of the elements, or to limit the order of the elements. In addition, wherever possible, elements/components/steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Reference may be made to the relevant descriptions of the elements/components/steps using the same reference numerals or using the same terms in different embodiments.
The node processing circuit 130 may perform a path competition operation on the candidate paths of the previous paths P11 to P1L, so as to select L paths from the candidate paths to serve as current paths P21, P22, . . . , P2L. The current paths P21 to P2L correspond to multiple candidate decoding results of the current node. The paths P21 to P2L corresponding to the current node may serve as the previous paths P11 to P1L corresponding to a next node during decoding of the next node after the current node.
In some embodiments, the path expanding circuit 120 may adaptively determine the path expanding number E (with reference to relevant description of
The unreliable information bit number c is described as follows. The encoded bit string 101 contains multiple information bits (that is, bits with unknown values) and multiple frozen bits (that is, bits with known values), after the polar code encoding operation is completed. The polar code encoding apparatus 10 may provide the polar code decoding apparatus 100 with the bit reliability of each of the bits in the encoded bit string 101. This embodiment does not limit specific implementation of the bit reliability. In some embodiments, the bit reliability may include a well-known Bhattacharyya parameter or other values suitable for showing the reliability of each of the bits in the encoded bit string 101 according to the design requirements.
Each of the bits in the encoded bit string 101 has a corresponding bit reliability. Each of the bits in the encoded bit string 101 may be classified as an “information bit” or a “frozen bit” according to the bit reliability, based on the polar code encoding operation of the polar code encoding apparatus 10. Specifically, a numerical range of the bit reliability may at least be divided into a first sub-range and a second sub-range. The first sub-range is a partial numerical range with highest reliability in the numerical range, and the second sub-range is a partial numerical range with lowest reliability in the numerical range. A certain bit (current bit) may be classified as an “information bit” when the bit reliability of the current bit in the encoded bit string 101 falls within the first sub-range. The current bit may be classified as a “frozen bit” when the bit reliability of the current bit falls within the second sub-range.
Sizes of the first sub-range and the second sub-range may be determined according to the design requirements. For example (but not limited to this), the first sub-range may be first 50% of the numerical range of the bit reliability, and the second sub-range may be last 50% of the numerical range of the bit reliability. The “first 50%” means the 50% with the highest reliability in the numerical range. Similarly, the “last 50%” is the 50% with the lowest reliability in the numerical range.
The first sub-range may at least be divided into a third sub-range and a fourth sub-range. The third sub-range is a partial numerical range with highest reliability in the first sub-range, and the fourth sub-range is a partial numerical range with lowest reliability in the first sub-range. The current bit may be classified as a “reliable information bit” when the bit reliability of the current bit falls within the third sub-range. The current bit may be classified as an “unreliable information bit” when the bit reliability of the current bit falls within the fourth sub-range. Sizes of the third sub-range and the fourth sub-range may be determined according to the design requirements. For example (but not limited to this), the third sub-range may be first 72.54% of the first sub-range, and the fourth sub-range may be remaining 27.46% of the first sub-range.
The unreliable information bit number c of the current node may be a number of the bits classified as “unreliable information bits” in the current node. In the Step S310, the path expanding circuit 120 may dynamically determine the path expanding number E of the candidate paths of each of the L previous paths P11 to P1L according to the unreliable information bit number c of the current node. For example (but not limited to this), the path expanding number E=min (2ε, L), where min( ) represents a “minimum value” function, E represents the number of the bits classified as the “unreliable information bits” in the current node, and L represents a path number of the previous paths P11 to P1L (or a path number of the current paths P21 to P2L).
With reference to
The node processing circuit 130 is coupled to the path expanding circuit 120. In Step S330, the node processing circuit 130 may perform the path competition operation to select some paths from the multiple candidate paths expanded from the previous paths P11 to P1L to serve as the L current paths P21 to P2L corresponding to the current decoding results. The embodiment does not limit specific implementation of the path competition operation performed in the Step S330. In some embodiments, according to the design requirements, the path competition operation performed in the Step S330 may be a path competition operation in the conventional polar code decoding algorithm. In other embodiments, the Step S330 may perform other path competition operations, such as a path competition operation performed in Step S420 as shown in
With reference to
A small circle shown in
It can be seen from
The node processing circuit 130 may sort the candidate paths of each of the previous paths P11 to P1L after the sorting of the previous paths P11 to P1L (as shown in
The embodiment uses the flipping pattern to sort the E paths expanded from a certain previous path. The flipping pattern is a combination of the multiple bits of a node. In the embodiment, offline statistical analysis may be performed on each type of the nodes, so as to sort the flipping pattern that is more likely to be the correct path in a position prioritized for sorting. For example, assuming that a node has 2 bits, the flipping pattern includes “all bits are not flipped”, “only one bit is flipped and a most unreliable (smallest LLR) position is flipped”, “only one bit is flipped and a second most unreliable (second smallest LLR) position is flipped” and “both bits are flipped”. If the LLR value of the current node is (−0.5,5), a first path (first in the order) in the selection order of the flipping pattern of the current node is (1,0), a second path (second in the order) in the selection order is (0,0), a third path (third in the order) in the selection order is (1,1), and a fourth path (fourth in the order) in the selection order is (0,1). The flipping pattern is analyzed and fixed in advance, but the actual expanded paths are related to the LLR value received by the current node.
The node processing circuit 130 may preferentially select a more likely to be correct candidate path to undergo the path competition operation after the path metric values PMs of the parent paths (the previous paths P11 to P1L) and the flipping pattern of the current node are sorted. A concept of this type of path competition operation is that the candidate path (flipping pattern) to undergo the path competition operation in a next stage (step) is determined by the candidate paths that survive the current stage. The node processing circuit 130 may select first two types of the flipping patterns (candidate paths) of a highest possibility for each of the parent paths (the previous paths P11 to P1L) to undergo 2L-to-L path competition in a first stage. That is, the node processing circuit 130 may preferentially select 2L candidate paths that are more likely to survive to undergo the path competition, and then obtain the L surviving paths when the number of the parent paths is L. Assuming that a surviving path is located at an i-th position in the selection order (an i-th position of the flipping pattern), the candidate path expanded from the same parent path at a k-th stage is located in an i+2(k-1)th position (an i+2(k-1)th position of the flipping pattern). The node processing circuit 130 may complete the path competition of a node (the current node) after log2 E “2L-to-L path competition”.
For example,
In a first stage S1 shown in
In a case where a certain path (herein called a target surviving path) of the first surviving paths P11, P12, P13, and P21 belongs to a certain path (herein called a target previous path) of the previous paths P11 to P14, the node processing circuit 130 may select an unselected candidate path from the candidate paths of the target previous path according to the selection order of the target previous path to serve as one of multiple second candidate paths in a second stage S2. The second candidate paths also include the first surviving paths. The node processing circuit 130 may calculate the path metric value PM of the selected unselected candidate path.
In the second stage S2 shown in
In a case where a certain surviving path (the target surviving path) of the second surviving paths P11, P12, P21, and P31 belongs to a certain path (the target previous path) of the previous paths P11 to P14, the node processing circuit 130 may select an unselected candidate path from the candidate paths of the target previous path according to the selection order of the target previous path to serve as one of multiple third candidate paths in the second stage S2.
In a third stage S3 shown in
With reference to
Using
In the embodiment shown in
The LLR memory 111 stores and provides the bit reliability (for example, the LLR) of N bits of the current node during a successive cancellation (SC) decoding process. In general, the list successive cancellation (LSC) decoding requires a L*N*QLLR bits (QLLR is a quantization bit of the LLR) memory (configured to determine a LLR interval during the SC decoding process), and N*Qch bits of memory (configured for a channel LLR value). Therefore, a total of L*N*QLLR+N*Qch bits of memory are required. In some embodiments, the node size M=8, number of the PE in each of the lists is 64, a stage number of the PE is SPE=log264=6, and area consumption is reduced by 2*L(2SPE+2SPE−1+ . . . +2SPE-log2M)Q=240LQ. Due to calculation in advance of LLR of some G nodes, decoding latency may also be reduced by N/2SPE+1+N/2SPE+ . . . +N/2log2M+1=120 cycles.
There is an L-to-L cross-bar multiplexer 112 controlled by the pointer memory 115 between the PE array 113 and the LLR memory 111. As the order of the candidates in the list may change each time the node processing circuit 130 gives a new surviving path, therefore the cross-bar multiplexer 112 is responsible for providing the corresponding list LLR to the PE array 113. The partial sum unit (PSU) 114 is configured to store and calculate partial sum of the node calculate in the PE array 113. The partial sum unit (PSU) 114 may provide the partial sum for nodes that are required to be calculated in advance, and calculate the partial sum of a node with the node size M of up to 8. The path memory 117 and the CRC unit 116 successively store decision bits of each of the lists coming from the node processing circuit 130. The modules use the L-to-L cross-bar multiplexer 112 during decoding to enable the decision bits to continuously have a same list of candidates. At the end of decoding, the CRC unit 116 outputs legitimate signals, so as to select one of legal paths legal paths in the path memory 117 to serve as a decoded frame.
The path expanding circuit 120 and the node processing circuit 130 select the surviving path and the path metric value PM by calculating and sorting the path metric value PM according to the received node LLR. The path management unit 121 calculates the path metric value PM according to the current node type and decoding stage, and then the sorter 131 selects the best L paths and repeatedly feedbacks to the path management unit 121. It should be noted that the embodiment shown in
The path metric value memory 132 is configured to store the path metric value PM. The normalized circuit 133 is coupled to the path metric value memory 132. The normalized circuit 133 performs a normalization operation on the path metric value PM in the path metric value memory 132, and updates a normalized operation result to the path metric value memory 132. For example, in some embodiments, the normalized circuit 133 may calculate PMi=PMi−PMmin, so as to perform the normalization operation.
According to different design requirements, implementation manners of the blocks of the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130 may be through hardware, firmware, or software (that is, programs), or a combination thereof.
In terms of hardware, the blocks of the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130 described above may be implemented in a logic circuit on an integrated circuit. The relevant functions of the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130 may be implemented as the hardware using hardware description languages (for example, Verilog HDL or VHDL) or other suitable programming languages. For example, relevant functions of the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130 may be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuit (ASIC), digital signal processor (DSP), field programmable gate array (FPGA) and/or various logic blocks, modules, and circuits in other processing units.
In terms of software and/or firmware, the relevant functions of the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130 may be implemented as a programming code. For example, general programming languages (such as C, C++ or an assembly language) or other suitable programming languages are used to implement the interface circuit 110, the path expanding circuit 120, and/or the node processing circuit 130. The programming code may be recorded/stored in a recording medium. In some embodiments, the recording medium includes, for example, a read only memory (ROM), a random access memory (RAM), and/or a storage device. The storage device includes a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. In other embodiments, the recording medium may include “non-transitory computer readable medium”, such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, which may be used to implement the non-transitory computer readable medium. A computer, a central processing unit (CPU), a controller, a microcontroller, or a microprocessor may read and execute the programming code from the recording medium, thereby performing the relevant functions of the interface circuit 110, the path expanding circuit 120, and (or) the node processing circuit 130. Moreover, the programming code may also be provided to the computer (or the CPU) through any transmission medium (such as a communication network or broadcasting waves). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.
In summary, the polar code decoding apparatus 100 and the operation method thereof in the foregoing embodiments can optimize the efficiency of polar code decoding to a maximum extent. A current node containing many reliable information bits is not required to expand into many candidate paths. In the case where “nodes with different reliabilities have the same path expanding number”, the conventional path expanding circuit may perform expansion of redundant paths (expand out into redundant candidate paths). It is conceivable that the redundant candidate paths will increase the hardware complexity and decoding delay. Therefore, in some embodiments, the path expanding circuit 120 may dynamically determine the path expanding number E of each of the previous paths P11 to P1L according to the unreliable information bit number c of the current node (for example, E=min(2ε, L)), so as to reduce the redundant candidate paths as much as possible.
The conventional node processing circuit performs the path competition operation in an irregular manner, that is, the conventional node processing circuit has to process all of the candidate paths. The polar code decoding apparatus 100 may preferentially select a more reliable candidate path to undergo the path competition operation according to the path metric values PMs of the previous paths P11 to P1L and the LLR value of each bit of the current node. Therefore, the polar code decoding apparatus 100 can accurately and efficiently find out which of the candidate paths are more likely to be the correct paths.
The length of the critical path is related to the bit number of the path metric value PM. The node processing circuit 130 may perform the normalization operation on the path metric value PM of the candidate path to reduce the bit number of the path metric value PM. The normalization of the path metric value PM can reduce the complexity and decoding delay.
Although the disclosure has been disclosed with the foregoing exemplary embodiments, they are not intended to limit the disclosure. Any person skilled in the art can make various changes and modifications within the spirit and scope of the disclosure. Accordingly, the scope of the disclosure is defined by the claims appended hereto and the equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 110101426 | Jan 2021 | TW | national |
