POROUS TWO-WAFER BATTERY

Abstract

A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode. The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.

Description

FIELD OF THE INVENTION

This invention relates generally to a porous two-wafer battery. More particularly, the present invention relates to a porous silicon two-wafer, lithium battery.

BACKGROUND OF THE INVENTION

For lithium batteries, lithium metal dendritic growth is one of the most serious problems affecting the safety and functionality of lithium-based batteries. Dendrites are fractal deposits of various shapes such as needle-like, snowflake-like, tree-like, bush-like, moss-like, and whisker- like structures. During charging in Li metal (and Li-ion) anodes, lithium does not form a flat, homogeneous layer on the anode, but instead dendrites that can be needle-like or branched. Factors affecting Li dendrite growth at the anode are current density, electrolyte composition and concentration, and solid-electrolyte-interphase layer (SEI). Dendrites grow in a non-linear fashion and in apparently random motion of the tips of the lithium. The dendrites growth are not dominated by the direction of the electric field. In a configuration with two planar-type electrodes, the lithium dendrites inevitably grow towards the other electrode, penetrating thereby through the separator and causing short upon reaching the conductive surface of the opposite electrode.

Methods using polymers, block copolymers, ionomers, HF, metal ions with a higher reduction potential than Li such as Sn4+, Sn2+, Al3+, In3+, Ga3+ and Bi3+, oligomers, ionic liquids to possibly suppress the dendrites growth are reported in the battery industry. Other methods include use of solid electrolyte, ceramic electrolyte, and self-healing electrostatic shield, e.g., Cs+.

Variations of the formulations of electrolyte have also been reported. It includes modifications of the electrolyte salts: LiClO4, LiPF6, LiAsF4 and LiBF4, addition of ethers (DME and DEE), esters (PC, EC, DMC and DEC), EC/DMC and PC/DMC mixture with LiTFSI demonstrated to promote delayed dendrite formation.

The methods above may suppress dendrite growth. But, it also introduce additional problems such as increased side reaction and modified cycling characteristics.

The growth of lithium dendrite may result in electrical short. It can lead to battery heating up, catching fire, or exploding.

Therefore, it is required for suppressing the growth of lithium dendrite especially for a high-power density, high current, low cost battery. It is possible to completely eliminate dendrite growth by placing the reaction of lithium reduction away from the surface of electrode and inside the pore of porous silicon. It is also possible to provide a structure that allows for high-power density and high current abilities.

SUMMARY OF THE INVENTION

A porous two-wafer battery comprises a first wafer and a second wafer. Each of the first wafer and the second wafer comprises a substrate, a conductive layer, and a passivation layer. The first wafer is parallel to the second wafer. The passivation layer of the first wafer is closer to the passivation layer of the second wafer. The first wafer serves as an anode and the second wafer serves as a cathode.

The substrate comprises a plurality of pores and a P+ doped region. The plurality of pores are symmetric with respect to a respective center of each of the first wafer and the second wafer. An adhesion promotion layer is between the conductive layer and a respective side wall of the plurality of pores.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a side view of a porous two-wafer battery in examples of the present disclosure.

FIG. 2 is a front view of a wafer of a porous two-wafer battery in examples of the present disclosure.

FIG. 3 is a side view of another porous two-wafer battery in examples of the present disclosure.

FIG. 4 is a cross-sectional plot along AA′ of the wafer of FIG. 2 in examples of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a side view of a porous two-wafer battery 100 in examples of the present disclosure. The porous two-wafer battery 100 comprises a first wafer 120, a second wafer 160, and an optional electrolyte separator 110 (shown in dashed lines) between a front side 131 of the first wafer 120 and a front side 171 of the second wafer 160. FIG. 2 is a front view of the first wafer 120 of the porous two-wafer battery 100 in examples of the present disclosure. The first wafer 120 comprises a first substrate 122. The first substrate 122 comprises a plurality of pores 140 (shown in dashed lines because of the side view). The second wafer 160 comprises a second substrate 162. The second substrate 162 comprises a plurality of pores 180 (shown in dashed lines because of the side view).

In one example, the plurality of pores 140 and the plurality of pores 180 are of rectangular shapes. In another example, the plurality of pores 140 and the plurality of pores 180 are of square shapes. In still another example, the plurality of pores 140 and the plurality of pores 180 are of circular shapes. A diameter of the plurality of pores 140 and the plurality of pores 180 is in a range from 1 micron to 100 microns. In examples of the present disclosure, a diameter and a pitch of the plurality of pores 140 and the plurality of pores 180 is 20 microns and 22 microns respectively.

In one example, a diameter of the first wafer 120 is 4 inches. In another example, a diameter of the first wafer 120 is 6 inches. In still another example, a diameter of the first wafer 120 is 8 inches. In yet another example, a diameter of the first wafer 120 is 12 inches. The capacity (charge) of the first wafer 120 is 60 Ah. In yet still another example, a diameter of the first wafer 120 is 18 inches. In examples of the present disclosure, the capacity (charge) of the first wafer 120 is in a range from 1 Ah to 100 Ah. A thickness of the first wafer is in a range from 100 microns to 750 microns.

In examples of the present disclosure, the first wafer 120 is parallel to the second wafer 160. The front side 131 of the first wafer 120 is closer to the front side 171 of the second wafer 160 than a back side 173 of the second wafer 160. The front side 171 of the second wafer 160 is closer to the front side 131 of the first wafer 120 than a back side 133 of the first wafer 120.

In examples of the present disclosure, the first substrate 122 of the first wafer 120 is made of a silicon material. The second substrate 162 of the second wafer 160 is made of the silicon material.

In examples of the present disclosure, the first plurality of pores 140 are symmetric with respect to a center 231 of the first wafer 120. The second plurality of pores 180 are symmetric with respect to a center of the second wafer 160. The first plurality of pores 140 are symmetric with respect to X-axis. The first plurality of pores 140 are symmetric with respect to Y-axis. The second plurality of pores 180 are symmetric with respect to X-axis. The second plurality of pores 180 are symmetric with respect to Y-axis.

In examples of the present disclosure, a centerline 130 of the first wafer 120 is aligned with a centerline 170 of the second wafer 160. The porous two-wafer battery 100 may include hundreds or thousands of cathode or anode pores.

In examples of the present disclosure, the first wafer 120 serves as an anode and the second wafer 160 serves as a cathode.

FIG. 3 is a side view of a porous two-wafer battery 300 in examples of the present disclosure. The porous two-wafer battery 300 comprises a first wafer 320 and a second wafer 360. The first wafer 320 comprises a first substrate 322 and a first passivation layer 345 on a front side 331 of the first wafer 320. The first substrate 322 comprises a first plurality of pores 340 (shown in dashed lines because of the side view). The second wafer 360 comprises a second substrate 362 and a second passivation layer 385 on a front side 371 of the second wafer 360. The second substrate 362 comprises a second plurality of pores 380 (shown in dashed lines because of the side view).

In examples of the present disclosure, the first passivation layer 345 and the second passivation layer 385 are made of a material selected from the group consisting of Ta2O5, HfO2, and SiN. A thickness of each of the first passivation layer 345 and the second passivation layer 385 is in a range from 30 microns to 100 microns.

In examples of the present disclosure, the first wafer 320 is parallel to the second wafer 360. In examples of the present disclosure, the first substrate 322 of the first wafer 320 is made of a silicon material. The second substrate 362 of the second wafer 360 is made of the silicon material.

In examples of the present disclosure, the first plurality of pores 340 are symmetric with respect to a center of the first wafer 320. The second plurality of pores 380 are symmetric with respect to a center of the second wafer 360.

In examples of the present disclosure, the first passivation layer 345 directly contacts the second passivation layer 385. A centerline 330 of the first wafer 320 offsets from a centerline 370 of the second wafer 360 by a pre-determined distance 351. In examples of the present disclosure, the pre-determined distance 351 is in a range from 10% of a width 353 of a selected pore of the first plurality of pores 340 to 50% of the width 353 of the selected pore of the first plurality of pores 340.

In examples of the present disclosure, the first wafer 320 serves as an anode and the second wafer 360 serves as a cathode.

FIG. 4 is a cross-sectional plot along AA′ of the first wafer 120 of FIG. 2 in examples of the present disclosure. The second wafer 160 has similar structure as the first wafer 120. The first wafer 120 comprises a first substrate 122, a first conductive layer 430 on a respective side wall 442 of each of the first plurality of pores 140, and a first passivation layer 476 on a front side of the first wafer 120. The first substrate 122 comprises a plurality of pores 140 and a P+ doped region 123.

The first conductive layer 430 provides electrical conductivity and serves as a reactive surface for battery reactions. The silicon substrate may not in contact with lithium. The first passivation layer 476 prevents lithium reduction and prevents dendrite growth.

In examples of the present disclosure, the first passivation layer 476 comprises a first plurality of passivation sections 477. Each of the first plurality of passivation sections 477 is of a first letter U shape. A first leg 471 of the first letter U shape is directly attached to the first conductive layer 430 of a first selected pore 491 of the first plurality of pores 140. A second leg 472 of the first letter U shape is directly attached to the first conductive layer 430 of a second selected pore 492 of the first plurality of pores 140. A length of the first leg 471 and a length of the second leg 472 is in a range from 20 microns to 50 microns.

In examples of the present disclosure, the first conductive layer 430 is made of a material selected from the group consisting of titanium nitride, silicates, silicon carbide, copper, and nickel. The first passivation layer 476 is made of a material selected from the group consisting of Ta2O5, HfO2, and SiN. The first conductive layer 430 may be formed by impregnation or deposition.

An entirety of the first conductive layer 430 is in the inner portion of the first plurality of pores 140. There is no direct path for electrical short. In addition, there is no SEI layer that would initiate the dendrite growth. Furthermore, there are no edge effects of protrusion.

In examples of the present disclosure, a first adhesion promotion layer 447 is between the first conductive layer 430 and the respective side wall 442 of each of the first plurality of pores 140.

In one example, a thickness of the first conductive layer 430 is in a range from 30 microns to 200 microns. In another example, a thickness of the first conductive layer 430 is in a range from 100 microns to 150 microns. In one example, a thickness of the adhesion promotion layer 447 is in a range from 20 microns to 200 microns.

In examples of the present disclosure, each of a porous silicon anode and a porous silicon cathode comprises 20 μm pore dimension, 22 μm pitch, 350 μm electrode thickness; TiN coating (100 μm), Ta2O5 dielectric coating on the inner surface (50 μm). The cathode material is LiCoO₂ or LiMn₂O₄. The electrolyte is 1 M LiFP6 in CE/DE.

In examples of the present disclosure, the battery is held in a pouch-type cell including rigid or semi-rigid containers. Another conductive layer may be added on top of the first conductive layer 430 to further improve conductivity.

Those of ordinary skill in the art may recognize that modifications of the embodiments disclosed herein are possible. For example, a number of the first plurality of pores may vary. Other modifications may occur to those of ordinary skill in this art, and all such modifications are deemed to fall within the purview of the present invention, as defined by the claims.

Claims

1. A porous two-wafer battery comprising a first wafer comprising a first substrate comprising a first plurality of pores;a first conductive layer on a respective side wall of each of the first plurality of pores; anda first passivation layer on a front side of the first wafer; anda second wafer comprising a second substrate comprising a second plurality of pores;a second conductive layer on a respective side wall of each of the second plurality of pores; anda second passivation layer on a front side of the second wafer;wherein the first wafer is parallel to the second wafer;wherein the front side of the first wafer is closer to the front side of the second wafer than a back side of the second wafer; andwherein the front side of the second wafer is closer to the front side of the first wafer than a back side of the first wafer.

2. The porous two-wafer battery of claim 1, wherein the first substrate of the first wafer is made of a silicon material; and wherein the second substrate of the second wafer is made of the silicon material.

3. The porous two-wafer battery of claim 1, wherein an electrolyte separator is between the front side of the first wafer and the front side of the second wafer.

4. The porous two-wafer battery of claim 1, wherein the first passivation layer comprises a first plurality of passivation sections; wherein each of the first plurality of passivation sections is of a first letter U shape;wherein the second passivation layer comprises a second plurality of passivation sections; andwherein each of the second plurality of passivation sections is of a second letter U shape.

5. The porous two-wafer battery of claim 4, wherein a first leg of the first letter U shape is directly attached to the first conductive layer of a first selected pore of the first plurality of pores; wherein a second leg of the first letter U shape is directly attached to the first conductive layer of a second selected pore of the first plurality of pores;wherein the first selected pore of the first plurality of pores is different from the second selected pore of the first plurality of pores;wherein a first leg of the second letter U shape is directly attached to the first conductive layer of a first selected pore of the second plurality of pores;wherein a second leg of the second letter U shape is directly attached to the first conductive layer of a second selected pore of the second plurality of pores; andwherein the first selected pore of the second plurality of pores is different from the second selected pore of the second plurality of pores.

6. The porous two-wafer battery of claim 1, wherein the first plurality of pores are symmetric with respect to a center of the first wafer; and wherein the second plurality of pores are symmetric with respect to a center of the second wafer.

7. The porous two-wafer battery of claim 6, wherein a centerline of the first wafer is aligned with a centerline of the second wafer.

8. The porous two-wafer battery of claim 6, wherein the first passivation layer directly contacts the second passivation layer.

9. The porous two-wafer battery of claim 8, wherein a centerline of the first wafer offsets from a centerline of the second wafer by a range from ten percent of a width of a selected pore of the first plurality of pores to fifty percent of the width of the selected pore of the first plurality of pores.

10. The porous two-wafer battery of claim 1, wherein a first adhesion promotion layer is between the first conductive layer and the respective side wall of each of the first plurality of pores; and wherein a second adhesion promotion layer is between the second conductive layer and the respective side wall of each of the second plurality of pores.

11. The porous two-wafer battery of claim 1, wherein the first wafer serves as an anode and the second wafer serves as a cathode.

12. The porous two-wafer battery of claim 1, wherein the first conductive layer and the second conductive layer are made of a material selected from the group consisting of titanium nitride, silicates, silicon carbide, copper, and nickel.

13. The porous two-wafer battery of claim 1, wherein the first passivation layer and the second passivation layer are made of a material selected from the group consisting of Ta2O5, HfO2, and SiN.

14. The porous two-wafer battery of claim 1, wherein the first substrate further comprises a first P+ doped region; and wherein the second substrate further comprises a second P+ doped region.