Patent Grant
11967934
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-087945, filed on May 20, 2020, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a power amplifier circuit.
JP2011-151694A discloses a technique relating to a power amplifier circuit.
The present disclosure provides a power amplifier circuit. The power amplifier circuit is a Doherty type power amplifier circuit and includes a main amplifier and a peak amplifier. A first input signal and a second input signal branched off from one input signal are respectively input to the main amplifier and the peak amplifier. The power amplifier circuit synthesizes and outputs a first output signal from the main amplifier and a second output signal from the peak amplifier. The peak amplifier includes a first transistor and a second transistor. The first transistor includes a first source terminal, a first drain terminal and a first control terminal. The second transistor includes a second source terminal, a second drain terminal and a second control terminal. The first source terminal is connected to a first constant potential line. The first drain terminal is connected to a first node. The second source terminal is connected to the first node. The second drain terminal is connected to a second constant potential line having a higher potential than the first constant potential line. The first control terminal is connected to a first bias voltage application circuit. A second input signal is input to the first control terminal via a first alternating current coupling circuit. The first bias voltage application circuit applies a first bias voltage to the first control terminal. The second control terminal is connected to a second bias voltage application circuit and is connected to the first node via a second alternating current coupling circuit. The first node is connected to the first constant potential line via a third alternating current coupling circuit. The second bias voltage application circuit applies a second bias voltage to the second control terminal. A second node between the second drain terminal and the second constant potential line is connected to a fourth alternating current coupling circuit, and outputs a second output signal via the fourth alternating current coupling circuit.
For example, in a power amplifier circuit such as a microwave amplifier circuit, a so-called Doherty type configuration may be used to improve power efficiency. The Doherty type power amplifier circuit includes a main amplifier which performs class A to class AB or class B operations and a peak amplifier which performs a class C operation, and individually amplifies an input signal in the main amplifier and the peak amplifier, and synthesizes and outputs an output signal from the main amplifier and an output signal from the peak amplifier. In the Doherty type power amplifier circuit, an impedance of the peak amplifier decreases as output power increases, and as a result, a load on the main amplifier is reduced, and amplification can be performed with high power efficiency.
In such a Doherty type power amplifier circuit, when gains of transistors constituting the main amplifier and the peak amplifier are smaller than a gain required for the power amplifier circuit, it is necessary to configure a plurality of transistors in multiple stages. In that case, in the peak amplifier, it is desirable that timings at which the plurality of transistors connected in multiple stages are turned into an ON state (in other words, the plurality of transistors are turned on) are close to each other.
According to the present disclosure, in the peak amplifier of the Doherty type power amplifier circuit, the timings at which the plurality of transistors connected in multiple stages are turned into the ON state can be brought close to each other.
First, embodiments of the present disclosure will be listed and described. The power amplifier circuit according to one embodiment is a Doherty type power amplifier circuit and includes a main amplifier and a peak amplifier. A first input signal and a second input signal branched off from one input signal are input to the main amplifier and the peak amplifier, respectively. The power amplifier circuit synthesizes and outputs a first output signal from the main amplifier and a second output signal from the peak amplifier. The peak amplifier has a first transistor and a second transistor. The first transistor has a first source terminal, a first drain terminal, and a first control terminal. The second transistor has a second source terminal, a second drain terminal, and a second control terminal. The first source terminal is connected to a first constant potential line. The first drain terminal is connected to a first node. The second source terminal is connected to the first node. The second drain terminal is connected to a second constant potential line having a higher potential than the first constant potential line. The first control terminal is connected to a first bias voltage application circuit. The second input signal is input to the first control terminal via a first alternating current coupling circuit. The first bias voltage application circuit applies a first bias voltage to the first control terminal. The second control terminal is connected to a second bias voltage application circuit and is connected to the first node via a second alternating current coupling circuit. The first node is connected to the first constant potential line via a third alternating current coupling circuit. The second bias voltage application circuit applies a second bias voltage to the second control terminal. A second node between the second drain terminal and the second constant potential line is connected to a fourth alternating current coupling circuit and outputs the second output signal via the fourth alternating current coupling circuit. With such a configuration, in the peak amplifier of the Doherty type power amplifier circuit, timings at which a plurality of transistors connected in multiple stages are turned into an ON state can be brought close to each other.
In the above-described power amplifier circuit, the first bias voltage may have a magnitude such that the first transistor is in a pinch-off state when power of a signal input to the first control terminal does not exceed a first level, and the first transistor is in the ON state when the power of the signal input to the first control terminal exceeds the first level.
In the above-described power amplifier circuit, the second bias voltage may have a magnitude such that the second transistor is in a pinch-off state when the power of the signal input to the first control terminal does not exceed the first level, and the second transistor is in the ON state when the power of the signal input to the first control terminal exceeds the first level.
In the above-described power amplifier circuit, the peak amplifier may further include a third transistor having a third source terminal, a third drain terminal, and a third control terminal. The third source terminal may be connected to the first constant potential line. The third drain terminal may be connected to the first node. The third control terminal may be connected to a third bias voltage application circuit configured to apply a third bias voltage to the third control terminal. The second input signal may be input to the third control terminal via a fifth alternating current coupling circuit. The first control terminal may be connected to the third drain terminal via the first alternating current coupling circuit. The second input signal may be amplified by the third transistor and is then input to the first control terminal via the first alternating current coupling circuit.
In the above-described power amplifier circuit, a total gate width of the second transistor may be equal to or greater than a sum of a total gate width of the first transistor and a total gate width of the third transistor.
In the above-described power amplifier circuit, the third bias voltage may have a magnitude such that the third transistor is in the pinch-off state when the power of a signal input to the third control terminal does not exceed a first level, and the third transistor is in the ON state when the power of the signal input to the third control terminal exceeds the first level.
In the above-described power amplifier circuit, the first bias voltage may have a magnitude such that the first transistor is in the pinch-off state when power of a signal input to the first control terminal does not exceed a second level, and the first transistor is in an ON state when the power of the signal input to the first control terminal exceeds the second level. The second level may be greater than the first level.
In the above-described power amplifier circuit, the main amplifier may have the same configuration as the peak amplifier except for a magnitude of each of the bias voltages.
Specific examples of a power amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. The present invention is not limited to the examples, but is indicated by the appended claims and is intended to include all modifications within the meaning and scope equivalent to the appended claims. In the following description, the same elements will be designated by the same reference numerals in the description of the drawings, and redundant description will be omitted. In the description below, “connected” means “being electrically connected”. Unless otherwise specified, the electrical connection includes a connection via conductive wires with substantially zero electrical resistance, as well as a connection via electronic components such as resistors.
An input terminal of the driver amplifier 3 is connected to a signal input terminal 8 of the power amplifier circuit 1A. The driver amplifier 3 inputs a signal to be amplified from a signal input terminal 8, amplifies the signal, and outputs the amplified signal. The driver amplifier 3 is configured to include, for example, a transistor. A frequency of the signal input from the signal input terminal 8 is, for example, 60 GHz or more and 90 GHz or less. An output terminal of the driver amplifier 3 is connected to a node NA.
The main amplifier 4 and the peak amplifier 5 individually amplify the input signal. In the present embodiment, each of the main amplifier 4 and the peak amplifier 5 is configured as a two-stage amplifier. An input terminal of the main amplifier 4 is connected to the output terminal of the driver amplifier 3 via the node NA. The input terminal of the main amplifier 4 receives a first input signal which is one of signals branched off at the node NA after being amplified by the driver amplifier 3. The main amplifier 4 performs class A to class AB or class B amplification operations. An output terminal of the main amplifier 4 is connected to a signal output terminal 9 of the power amplifier circuit 1A via a node NB. The λ/4 line 6 is interposed between the output terminal of the main amplifier 4 and the node NB. The amplified signal output from the main amplifier 4 reaches the node NB through the λ/4 line 6. On the other hand, an input terminal of the peak amplifier 5 is connected to the output terminal of the driver amplifier 3 via the node NA. The λ/4 line 7 is interposed between the node NA and the input terminal of the peak amplifier 5. The input terminal of the peak amplifier 5 receives a second input signal which is the other signal branched off at the node NA after being amplified by the driver amplifier 3 via the λ/4 line 7. The peak amplifier 5 performs a class C amplification operation. An output terminal of the peak amplifier 5 is connected to the signal output terminal 9 of the power amplifier circuit 1A via the node NB. The amplified signal output from the peak amplifier 5 reaches the node NB. The output signal from the main amplifier 4 and the output signal from the peak amplifier 5 are synthesized with each other at the node NB and are output from the signal output terminal 9 to the outside of the power amplifier circuit 1A.
A control terminal, that is, a gate of the first transistor TR1 is connected to an input terminal 5a of the peak amplifier 5 via a coupling capacitor C1 as a first alternating current coupling circuit in an alternating current manner and is isolated from the input terminal 5a in a direct current manner. The control terminal of the first transistor TR1 receives an input signal Sin from the input terminal 5a via the coupling capacitor C1. The input signal Sin is a second input signal branched off at the node NA in
A control terminal, that is, a gate of the second transistor TR2 is connected to the first node N1 via a coupling capacitor C2 as a second alternating current coupling circuit in an alternating current manner and is isolated from the first node N1 in a direct current manner. The input signal Sin′ is propagated as an input signal Sin2 to the first node N1 via the first transistor TR1. The control terminal of the second transistor TR2 is connected to a circuit 12 which applies a second bias voltage VG2 to the control terminal. An input signal Sin2′ is input to the control terminal of the second transistor TR2. In the input signal Sin2′, the second bias voltage VG2 is applied to a high frequency signal component of the input signal Sin2 propagating through the coupling capacitor C2. In the present embodiment, the circuit 12 includes a voltage input terminal 12a and a resistor R12. The voltage input terminal 12a is connected to the control terminal of the second transistor TR2 via the resistor R12. The second bias voltage VG2 has a magnitude such that the second transistor TR2 is in the pinch-off state when the power of the input signal Sin2′ does not exceed the first level, and the second transistor TR2 is in the ON state when the power of the input signal Sin2′ exceeds the first level. In one embodiment, the second bias voltage VG2 is 3.6 V.
The first node N1 is connected to the ground potential line GND via a coupling capacitor C3 as a third alternating current coupling circuit in an alternating current manner and is isolated from the ground potential line GND in a direct current manner. The second node N2 between the second transistor TR2 and the power supply potential line VD is connected to an output terminal 5b of the peak amplifier 5 via a coupling capacitor C4 as a fourth alternating current coupling circuit in an alternating current manner and is isolated from the output terminal 5b in a direct current manner. The peak amplifier 5 outputs an amplified output signal Sout from the second node N2 via the coupling capacitor C4.
An operation of the peak amplifier 5 having the above-described configuration will be described. When the input signal Sin is received at the input terminal 5a, the input signal Sin which is a high frequency signal passes through the coupling capacitor C1 and reaches the control terminal of the first transistor TR1. The first bias voltage VG1 is applied from the circuit 11 to the control terminal of the first transistor TR1. Therefore, a voltage obtained by synthesizing the first bias voltage VG1 with the input signal Sin is applied to the control terminal of the first transistor TR1 as the input signal Sin′. When the first bias voltage VG1 is set to an appropriate magnitude, and the power of the input signal Sin′ does not exceed the first level, the first transistor TR1 is in the pinch-off state, and only a small amount of current flows between current terminals of the first transistor TR1. When the power of the input signal Sin′ exceeds the first level, the first transistor TR1 is in the ON state, and a current corresponding to a magnitude of the input signal Sin′ flows between the current terminals of the first transistor TR1.
Further, the high frequency component of the voltage applied to the control terminal of the first transistor TR1 caused by the input signal Sin′ is amplified and is then input as the input signal Sin2 from the first node N1 to the control terminal of the second transistor TR2 through the coupling capacitor C2. An arrow ARF in
Since the first transistor TR1 and the second transistor TR2 are connected in series between the power supply potential line VD and the ground potential line GND, the current flowing therethrough is common. An arrow ADC in
The main amplifier 4 shown in
When the power of the input signal Sin to the peak amplifier 5 is low (see
On the other hand, due to the circuit configuration, a drain current ID1 of the first transistor TR1 becomes equal to a drain current ID2 of the second transistor TR2. Thus, the potential of the drain voltage VD1 of the first transistor TR1 which is also the potential of the source voltage VS2 of the second transistor TR2 is determined with respect to the voltage Vg1s1 between the gate and the source of the first transistor TR1 so that the drain current ID1 and the drain current ID2 become equal to each other. Subsequently, the voltage VD1S1 between the drain and the source of the first transistor TR1, the voltage Vg2s2 between the gate and the source of the second transistor TR2, and the voltage VD2S2 between the drain and the source of the second transistor TR2 are determined. Actually, the voltage VD1S1 between the drain and the source of the first transistor TR1 is different from the voltage VD2S2 between the drain and the source of the second transistor TR2, and there is a slight difference therebetween, that is, VG1S1<VG2S2.
After that, when the power of the input signal Sin to the peak amplifier 5 starts to increase, the power of each of the input signal Sin′ and the input signal Sin2′ also starts to increase. Then, when the voltage Vg1s1 between the gate and the source of the first transistor TR1 and the voltage Vg2s2 between the gate and the source of the second transistor TR2 exceed a predetermined level (−0.4 V), as shown in
Then, as shown in
Effects obtained by the power amplifier circuit 1A of the present embodiment described above will be described together with the conventional problems.
In such a Doherty type power amplifier circuit, when a gain of the amplifier is a small value such as less than 10 dB, for example, as shown in
Therefore, as shown in
Regarding the above-described problem, in the peak amplifier 5 of the present embodiment, a current reuse configuration in which the two-stage transistors TR1 and TR2 are connected in series with each other is configured. Further, a high frequency signal path indicated by the arrow Air in
Here, as a comparative example, a power amplifier circuit having the current reuse configuration is shown in
In the power amplifier circuit 100 shown in
However, in order to realize the class C operation with such a self-bias configuration, it may be necessary to design the bias so that the transistor TR1 is in the OFF state when the level of the input signal Sin is low. Therefore, the bias should be designed as if the potential level of not only the input signal Sin′ to the gate of the first transistor TR1 but also the input signal Sin2 to the gate of the second transistor TR2 is sufficiently in the OFF state to the same extent. As a result, when the level of the input signal Sin becomes high, a delay inevitably occurs between the timing at which the first transistor TR1 is turned into the ON state and the timing at which the second transistor TR2 is turned into the ON state in conjunction with the first transistor TR1.
On the other hand, according to the peak amplifier 5 of the present embodiment, the gate bias of the first transistor TR1 and the gate bias of the second transistor TR2 can be input independently by providing the coupling capacitor C2. Therefore, it is possible to realize a power amplifier circuit capable of bringing the timing at which the first transistor TR1 is turned into the ON state and the timing at which the second transistor TR2 is turned into the ON state close to each other while the class C operation is performed. Since the main amplifier 4 of the present embodiment performs the class A to class AB or class B operation, it may have the configuration of the power amplifier circuit 100 shown in
According to the present embodiment, the voltages VD1S1 and VD2S2 between the drain and the source applied to the first transistor TR1 and the second transistor TR2 can be arbitrarily changed to some extent. Therefore, by changing a ratio of the voltage VD1S1 between the drain and the source of the first transistor TR1 to the voltage VD2S2 between the drain and the source of the second transistor TR2, it is possible to change saturation power of the first transistor TR1 and the second transistor TR2 without changing a total gate width of the first transistor TR1 and the second transistor TR2.
As described above, the first bias voltage VG1 may be set to such a magnitude that the first transistor TR1 is sufficiently in the pinch-off state with respect to the input signal Sin′ when the power of the input signal Sin does not exceed the first level, and the first transistor TR1 is in the ON state with respect to the input signal Sin′ when the power of the input signal Sin exceeds the first level. The class C operation of the first transistor TR1 can be performed by setting the first bias voltage VG1 in this way, for example.
On the other hand, the second bias voltage VG2 may be set to such a magnitude that the second transistor TR1 is shallowly in the pinch-off state with respect to the input signal Sin2′ when the power of the input signal Sin does not exceed the first level, and the second transistor TR2 is quickly turned into the ON state with respect to the input signal Sin2′ when the power of the input signal Sin exceeds the first level. As a result, in the peak amplifier 5 as a whole, it is possible to realize a power amplifier circuit capable of bringing the timing at which the first transistor TR1 is turned into the ON state and the timing at which the second transistor TR2 is turned into the ON state close to each other while the class C operation is performed.
As described above, the main amplifier 4 may have the same configuration as the peak amplifier 5 except for the magnitudes of the first bias voltage VG1 and the second bias voltage VG2. In this case, it becomes possible to simplify an analysis and the like for a design, and the design can be easy.
The transistor TR3 is connected in series between the ground potential line GND and the first node N1. Specifically, one current terminal of the transistor TR3, for example, the source is connected to the ground potential line GND, and the other current terminal, for example, the drain is connected to the first node N1 via a distributed constant circuit L3. The transistor TR3 is, for example, a GaN-HEMT, like the transistors TR1 and TR2.
The transistor TR1 is connected in series between the ground potential line GND and the first node N1. Specifically, one current terminal of the transistor TR1, for example, the source is connected to the ground potential line GND, and the other current terminal, for example, the drain is connected to the first node N1 via a distributed constant circuit L2.
The transistor TR2 is connected in series between the first node N1 and the power supply potential line VD as in the first embodiment. Specifically, one current terminal of the transistor TR2, for example, the source is connected to the first node N1, and the other current terminal, for example, the drain is connected to the power supply potential line VD via a distributed constant circuit L6. A total gate width W2 of the transistor TR2 is equal to or larger than a sum (W1+W3) of a total gate width W1 of the transistor TR1 and a total gate width W3 of the transistor TR3. In one embodiment, the total gate width W2 of the transistor TR2 is equal to the sum (W1+W3) of the total gate width W1 of the transistor TR1 and the total gate width W3 of the transistor TR3. Anode between the power supply potential line VD and the distributed constant circuit L6 may be connected to the ground potential line GND via a bypass capacitor C6.
The control terminal, that is, the gate of the transistor TR3 is connected to the input terminal 5a of the peak amplifier 5C via a coupling capacitor C5 as a fifth alternating current coupling circuit in an alternating current manner and is isolated from the input terminal 5a in a direct current manner. The total gate width W3 of the transistor TR3 is smaller than the total gate width W1 of the transistor TR1. In one embodiment, the total gate width W3 of the transistor TR3 is half the total gate width W1 of the transistor TR1. A distributed constant circuit L4 is interposed between the control terminal of the transistor TR3 and the coupling capacitor C5. At the control terminal of the transistor TR3, the input signal Sin′ is received from the input terminal 5a via the coupling capacitor C5 and the distributed constant circuit L4. The input signal Sin is a second input signal branched off at the node NA in
The control terminal of the transistor TR3 is connected to a circuit 13 which applies a bias voltage VG3 (a third bias voltage) to the control terminal. The circuit 13 includes a voltage input terminal 13a, a resistor R13, a distributed constant circuit L13, and a bypass capacitor C13. The voltage input terminal 13a is connected to the control terminal of the transistor TR3 via the distributed constant circuit L13 and the resistor R13 which are connected in series with each other. A node between the voltage input terminal 13a and the distributed constant circuit L13 is connected to the ground potential line GND via the bypass capacitor C13. In order to cause the transistor TR3 to perform the class C operation, the bias voltage VG3 is set to such a magnitude that the transistor TR3 is in the pinch-off state when the power of the input signal Sin′ does not exceed a level P1 (a first level), and the transistor TR3 is in the ON state when the power of the input signal Sin′ exceeds the level P1. In one embodiment, the bias voltage VG3 is −1 V, and the level P1 is −0.4 V as a value of a voltage between the gate and the source of the transistor TR3. The level P1 is determined based on, for example, a level at which the main amplifier 4 is saturated.
The control terminal of the transistor TR1 of the present embodiment is connected to a current terminal (for example, the drain) of the transistor TR3 on the first node N1 side via the coupling capacitor C1 in an alternating current manner and is isolated from the current terminal of the transistor TR3 in a direct current manner. More specifically, the control terminal of the transistor TR1 is connected to a node N3 between the transistor TR3 and the distributed constant circuit L3 via the coupling capacitor C1 in an alternating current manner and is isolated from the node N3 in a direct current manner. The control terminal of the transistor TR1 receives an input signal Sin3′, which is a signal after amplification by the transistor TR3, from the node N3 via the coupling capacitor C1.
The control terminal of the transistor TR1 is connected to a circuit 11A which applies a bias voltage VG1 (a first bias voltage) to the control terminal. The circuit 11A includes a voltage input terminal 11a, a resistor R11, a distributed constant circuit Ln, and a bypass capacitor Cn. The voltage input terminal 11a is connected to the control terminal of the transistor TR1 via the distributed constant circuit Lu and the resistor R11 which are connected in series with each other. A node between the voltage input terminal 11a and the distributed constant circuit L11 is connected to the ground potential line GND via the bypass capacitor Cn. In order to cause the transistor TR1 to perform the class C operation, the bias voltage VG1 is set to such a magnitude that the transistor TR1 is in the pinch-off state when the power of the input signal Sin3′ does not exceed a level P2 (a second level, P1<P2), and the transistor TR1 is in the ON state when the power of the input signal Sin′ exceeds the level P2. In one embodiment, the magnitude of the bias voltage VG1 is the same as the magnitude of the bias voltage VG3.
The control terminal of the transistor TR2 of the present embodiment is connected to the first node N1 via the coupling capacitor C2 in an alternating current manner and is isolated from the first node N1 in a direct current manner. More specifically, the control terminal of the transistor TR2 is connected to a node N4 between the transistor TR1 and the distributed constant circuit L2 via the coupling capacitor C2 in an alternating current manner and is isolated from the node N4 in a direct current manner. The control terminal of the transistor TR2 receives a signal obtained by synthesizing the output signal Sin3 and the output signal Sin2 as an input signal Sin2′ via the coupling capacitor C2. The output signal Sin3 is a signal after amplification by the transistor TR3 and is obtained from node N3 via the node N1 and the node N4. The output signal Sin2 is a signal after amplification by the transistor TR1 and is obtained via the node N4.
The control terminal of the transistor TR2 is connected to a circuit 12A which applies a bias voltage VG2 (a second bias voltage) to the control terminal. The circuit 12A includes a voltage input terminal 12a, a resistor R12, a distributed constant circuit L12, and a bypass capacitor C12. The voltage input terminal 12a is connected to the control terminal of the transistor TR2 via the distributed constant circuit L12 and the resistor R12 which are connected in series with each other. A node between the voltage input terminal 12a and the distributed constant circuit L12 is connected to the ground potential line GND via the bypass capacitor C12. In order to cause the transistor TR2 to perform the class C operation, the bias voltage VG2 has a magnitude such that the transistor TR2 is in the pinch-off state when the power of the input signal Sin2′ does not exceed the level P1, and the transistor TR2 is in the ON state when the power of the input signal Sin2′ exceeds the level P1. In one embodiment, the bias voltage VG2 is 3.6V.
Similar to the first embodiment, the first node N1 is connected to the ground potential line GND via a coupling capacitor C3 in an alternating current manner and is isolated from the ground potential line GND in a direct current manner. A second node N2 between the transistor TR2 and the power supply potential line VD is connected to the output terminal 5b of the peak amplifier 5C via a distributed constant circuit L5 and a coupling capacitor C4 in an alternating current manner and is isolated from the output terminal 5b in a direct current manner. The distributed constant circuit L5 and the coupling capacitor C4 are connected in series with each other. The peak amplifier 5C outputs an amplified output signal Sout from the second node N2 via the coupling capacitor C4.
An operation of the peak amplifier 5C having the above-described configuration will be described. When the input signal Sin is received at the input terminal 5a, the input signal Sin which is a high frequency signal passes through the coupling capacitor C5 and reaches the control terminal of the transistor TR3. The bias voltage VG3 is applied from the circuit 13 to the control terminal of the transistor TR3. Therefore, a voltage obtained by synthesizing the bias voltage VG3 and the high frequency signal component of the input signal Sin is applied to the control terminal of the transistor TR3 as the input signal Sin′. By setting the bias voltage VG3 to an appropriate magnitude, the transistor TR3 is in the pinch-off state and only a small amount of current flows between the current terminals when the power of the input signal Sin′ does not exceed the level P1. When the power of the input signal Sin′ exceeds the level P1, the transistor TR3 is in the ON state, and a current corresponding to the magnitude of the input signal Sin′ flows between the current terminals.
Further, the high frequency component of the voltage applied to the control terminal of the transistor TR3 caused by the input signal Sin′ is amplified as an output signal Sin3 and then input as an input signal Sin3′ from the node N3 to the control terminal of the transistor TR1 through the coupling capacitor C1. An arrow AR in
The high frequency component included in the voltage applied to the control terminal of the transistor TR1 is further amplified by the transistor TR1 and becomes an output signal Sin2. The output signal Sin2 is synthesized with the output signal Sin3, and is input from the node N4 through the coupling capacitor C2 to the control terminal of the transistor TR2 as an input signal Sin2′ (refer to the arrow ARF). The output signal Sin3 is a signal after amplification by the transistor TR3 and is obtained from node N3 via the node N1 and the node N4. The bias voltage VG2 is applied to the control terminal of the transistor TR2 from the circuit 12A. Therefore, a voltage obtained by synthesizing the bias voltage VG2 and the output signals Sin3 and Sin2 is applied to the control terminal of the transistor TR2 as the input signal Sin2′. The output signals Sin3 and Sin2 are high frequency components in which the input signal Sin′ is amplified. By setting the bias voltage VG2 to an appropriate magnitude, the transistor TR2 is in the pinch-off state and only a small amount of current flows between the current terminals when the power of the input signal Sin2′ does not exceed the level P1. When the power of the input signal Sin2′ exceeds the level P1, the transistor TR2 is in the ON state, and a current corresponding to the magnitude of the amplified high frequency component flows between the current terminals.
Since the transistors TR1 and TR2 are connected in series between the power supply potential line VD and the ground potential line GND, a current flowing therethrough is common. Since the transistor TR3 and the transistor TR2 are connected in series between the power supply potential line VD and the ground potential line GND, the current flowing therethrough is common. That is, a magnitude of the current flowing through the transistor TR2 is a sum of a magnitude of the current flowing through the transistor TR1 and a magnitude of the current flowing through the transistor TR3. An arrow ADC in
The main amplifier 4C shown in
As shown in
Similarly, the level P2 (the second level) which is a boundary of whether or not the transistor TR1 is in the pinch-off state is determined by whether or not the voltage between the gate and the source of the transistor TR1 is larger than −0.2V. In
At this time, in the current of the transistors TR3, TR2 and TR1 which flow slightly therethrough, a relationship in which a drain current ID2 of the transistor TR2 is equal to a sum (ID3+ID1) of a drain current ID3 of the transistor TR3 and a drain current ID1 of the transistor TR1 is maintained. The input signals Sin′, Sin3′ and Sin2′ applied to the gates of the transistors TR3, TR2 and TR1 are determined according to the input signal Sin input from the input terminal 5a. Subsequently, a source voltage VS2 of the transistor TR2 is determined so that the relationship of ID2=ID3+ID1 is maintained between the drain currents of the transistors TR3, TR2 and TR1. That is, the voltage VD2S2 between the drain and the source of the transistor TR2, the voltage VD3S3 between the drain and the source of the transistor TR3, and the voltage VD1S1 between the drain and the source of the transistor TR1 are determined.
After that, when the power of the input signal Sin to the peak amplifier 5C starts to increase, the power of each of the input signal Sin′, the input signal Sin2′, and the input signal Sin3′ also starts to increase. As shown in
Since −0.2V>Vg1s1>−0.4V, the transistor TR1 still remains in the pinch-off state, and only a small amount of drain current ID1 flows. However, since the relationship of ID2=ID3+ID1 is maintained between the drain currents of the transistors TR3, TR2 and TR1, the source voltage VS2 of the transistor TR2 is determined so that the drain currents ID2, ID3 and ID1 corresponding to the input signals Sin′, Sin3′ and Sin2′ applied to each of the gates flow. That is, the voltage VD2S2 between the drain and the source of the transistor TR2, the voltage VD3S3 between the drain and the source of the transistor TR3, and the voltage VD1S1 between the drain and the source of the transistor TR1 are determined.
When compared to
Additionally, when the power of the input signal Sin to the peak amplifier 5C is further increased, the power of each of the input signal Sin′, the input signal Sin2′, and the input signal Sin3′ is also further increased. As shown in
Since Vg1s1>−0.2V, the transistor TR1 also changes from the pinch-off state to the ON state, and the drain current ID1 starts to flow. When compared to
Subsequently, when the power of the input signal Sin to the peak amplifier 5C is further increased (
Like the power amplifier circuit 1B of the present embodiment, the peak amplifier 5C may further include the transistor TR3 connected in parallel with the transistor TR1 between the ground potential line GND and the first node N1, in addition to the configuration of the power amplifier circuit 1A of the first embodiment. In that case, the control terminal of the transistor TR3 may receive the input signal Sin via the coupling capacitor C5 and be electrically connected to the circuit 13 which applies the bias voltage VG3 to the control terminal. Then, the control terminal of the transistor TR1 may receive the voltage of the current terminal of the transistor TR3 on the first node N1 side, for example, the drain as an intermediate signal.
In this power amplifier circuit 1B, the current reuse configuration in which the transistors TR1 and TR2 of the peak amplifier 5C are connected in series with each other is formed, and the current reuse configuration in which the transistors TR3 and TR2 are connected in series with each other is formed. Thus, power efficiency can be improved. Also in the present embodiment, the high frequency signal path indicated by the arrow ARF in
As a comparative example,
With reference to
As the current reuse configuration, the power supply of the third-stage transistor TR2 which is the rear stage is supplied to the first-stage transistor TR3 and the second-stage transistor TR1 in parallel with each other via the transistor TR2. Additionally, the level P1 at which the transistor TR3 is turned into the ON state is determined based on the level at which the main amplifier 4C is saturated, whereas the level P2 at which the transistor TR1 is turned into the ON state is set to a value larger than the level P1. The transistor TR1 is turned into the ON state after the main amplifier 4C is saturated and the transistor TR3 is turned into the ON state by setting in this way. As a result, the transistor TR1 can increase the current value of the peak amplifier 5C without lowering the power efficiency while the leakage current is curbed in the pinch-off state. Further, since the timing at which the transistor TR1 is turned into the ON state can be set independently of the timing at which the transistor TR3 is turned into the ON state, the saturation value of the output power of the peak amplifier 5C can be increased.
When comparing
As described above, the total gate width W2 of the transistor TR2 may be equal to or greater than the sum (W1+W3) of the total gate width W1 of the transistor TR1 and the total gate width W3 of the transistor TR3. In this case, the total gate width corresponding to an amount of current flowing through the transistor TR2 can be secured.
As described above, the bias voltage VG3 may be set to such a magnitude that the transistor TR3 is in the pinch-off state when the power of the signal input to the control terminal of the transistor TR3 does not exceed the level P1, and the transistor TR3 is in the ON state when the power of the signal input to the control terminal of the transistor TR3 exceeds the level P1. For example, the class C operation of the transistor TR3 can be performed by setting the bias voltage VG3 in this way.
As described above, the bias voltage VG2 may have such a magnitude that the transistor TR2 is in the pinch-off state when the power of the signal input to the control terminal of the transistor TR3 does not exceed the level P1, and the transistor TR2 is in the ON state when the power of the signal exceeds the level P1. For example, the class C operation of the transistor TR2 can be performed by setting the bias voltage VG2 in this way.
As described above, the bias voltage VG1 may be set to such a magnitude that the transistor TR1 is in the pinch-off state when the power of the signal input to the control terminal of the transistor TR1 does not exceed the level P2, and the transistor TR1 is in the ON state when the power of the signal input to the control terminal of the transistor TR1 exceeds the level P2. For example, the class C operation of the transistor TR1 can be performed by setting the bias voltage VG1 in this way.
The power amplifier circuit according to the present disclosure is not limited to the above-described embodiment, and various other modifications are possible. For example, in the first embodiment, although the transistor TR1 constitutes the first stage transistor, and in the second embodiment, the transistor TR3 constitutes the first stage transistor, the number of stages may be further increased by providing another transistor in the previous stage of each of the transistors. When another transistor is provided in the previous stage of the transistor TR3, a signal based on the input signal Sin, for example, a signal obtained by amplifying the input signal Sin in the previous stage is input to the control terminal of the transistor TR3.
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| 2020-087945 | May 2020 | JP | national |
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