Patent Application
20230318537
The present disclosure relates to radio frequency amplification systems and methods of operating the same.
Traditional power amplifiers typically employ either n-type field-effect transistors (NFETS) or n-type-p-type-n-type (NPN) bipolar transistors in an output stage. This is due to a larger transition frequency and/or larger transconductance of the N-type devices such as NFETS and NPN bipolar transistors. In other words, electrons within N-type devices typically have higher mobility, which makes employing N-type devices as output stage power amplification devices desirable. However, an inductor employed as a choke coil within a power supply path that supplies the last stage with power causes voltage and current ringing that often becomes problematic, particularly with metal oxide semiconductor (MOS)-based implementations.
When the last stage power amplification devices turn OFF, that is, stop conducting, the level to which the output voltage of the last stage reaches can be several times larger than the supply voltage powering the output stage. For example, while a typical supply voltage may be 4.5 V, the output voltage can easily reach 16 V or more, over the load voltage standing wave ratio (VSWR) variation that can bring extreme changes in the complex load impedance. High impedance levels result in large output voltage swings. To counter the excessive voltage at the output of the power amplification stage, an undesirably large number of output stage devices must be stacked. This undesirable number of output stage devices results in a large area for the output stage, high individual parasitic capacitance, and a loss of efficiency due to multiple capacitive paths where the signal gets lost to ground. What is needed is a new output amplifier stage structure that reduces the number of stacked devices in the power amplification stage needed to counter the excessive voltage within at the output node.
Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating (CC) amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.
In some embodiments the main amplifier includes a series stack of p-type transistors having a first RF input and a series stack of n-type transistors having a second RF input. The first RF input and the second RF input are coupled to a common RF input that is the main input and the series stack of p-type transistors, and the series stack of n-type transistors are coupled together at a common RF output that is the main output. The compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output. In at least some embodiments, amplitude modulation-amplitude modulation (AM-AM) compensators are included to improve to AM-AM linearity required for fifth generation (5G) applications. In at least some embodiments, additional amplitude modulation-phase modulation (AM-PM) compensators are included to improve to AM-PM linearity required for fifth generation (5G) applications.
In yet another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.
During operation of the amplifier system 10, any soft amplitude modulation-amplitude modulation (AM-AM) distortion created by the main amplifier 12 at millimeter wave frequencies is compensated by the CC amplifier 14 that is biased as a class-C parallel amplifier stage. At small signal to medium signal levels, the CC amplifier 14 usually has a linear gain characteristic and no AM-AM correction is needed. At some given higher signal level the gain of the CC amplifier 14 may exhibit distortion, for example, soft compression. This is where the CC amplifier 14 begins gradually providing additional amplification as an RF signal being amplified grows in signal level and as soft compression begins. In essence, the bias provided by the class-C bias network 32 generates an offset bias that aligns the activation of the class-C parallel amplifier with the inflection point of the distortion (e.g., soft compression) in the main amplifier 12. The additional gain provided by the class-C biased CC amplifier 14 (gain boosting) needs to inversely match a soft compression profile of the main amplifier 12. Regarding operation of the input AM-PM compensator 36 providing compensation for the input capacitance of the CC amplifier 14, the input capacitance is relatively low when the CC amplifier 14 is turned-off up to the point that the CC amplifier 14 begins compensating for the soft compression. However, as the CC amplifier 14 becomes increasingly active, the input capacitance of the CC amplifier 14 also increases. To compensate, the input AM-PM compensator 36 has a capacitance that is higher before the beginning of soft compression and a capacitance that lowers as RF signal level increases and the CC amplifier becomes active. As such, input capacitance is maintained relatively constant as soft compression is compensated for by the CC amplifier 12.
An exemplary embodiment of the compression compensating (CC) amplifier 14 is depicted in
In the exemplary embodiment of
Also, an input AM-PM compensator 36B includes a transistor Q11B that is configured as a varactor. A resistor R2 and a second series voltage source V2 is coupled between a fixed voltage node, which in this case is ground (GND1), and a drain and a source of the transistor Q11B. The input AM-PM compensator 36B is configured to substantially maintain constant input capacitance of at least the transistor Q10. It is to be understood that additional AM/PM compensators structured substantially like the input AM-PM compensators 36A and 36B may added to the inputs/gates of any or all the remaining transistors Q2, Q3, Q4, Q5, and Q9.
In this regard, a power amplifier may be comprised of one, two, three or even more amplifying stages. All stages or only a subset of the power amplifier stages may use the presented AM-AM and AM-PM correction circuits. In general, the front-end stages operate at lower signal level and thus exhibit more linear characteristics that may not require AM-AM and/or AM-PM linearization. It is the back-end stages (in particular, the last output stage) that operates at the largest signal level and thus exhibits a higher level of distortion, mandating the use of AM-AM and/or AM-PM correction circuits.
In some embodiments, the main amplifier 12 and the CC amplifier 14 are complementary metal oxide semiconductor (CMOS)-type amplifiers. In other embodiments, the main amplifier 12 and the CC amplifier 14 are partially depleted silicon-on-insulator (SOI) CMOS-type amplifiers. In yet other embodiments, the main amplifier 12 and the CC amplifier 14 are fully depleted SOI CMOS-type amplifiers.
It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements
