The present application relates to amplifiers and in particular to power amplifiers that use a compound semiconductor transistor to amplify a digitally pre-distorted input signal.
Recent telecommunications standards use complex modulation schemes such as Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM) that require highly linear power amplification. Typically, the amplifier is required to operate at microwave frequencies of the order of 109Hz.
Power amplifiers have been proposed that use digital pre-distortion techniques to achieve the necessary linearity. However, in order to function effectively, the relationship between the output of the amplifier and input signal should be independent of the dynamics of the input signal. One way in which the dynamics of the input signal affect the output signal is the action of memory effects. Memory effects are caused by trapping or de-trapping of electrons or holes within the transistor and change the characteristics of the transistor dependent upon the previous values of the input signal.
Pre-distortion algorithms have been proposed that include both memoryless and memory terms to take into account memory effects. The complex coefficients used for any particular amplifier are calculated at full power at a given frequency.
In amplitude modulated signals, such as WCDMA and OFDM, power levels can change rapidly in millisecond time frames. In these circumstances, the performance of the pre-distortion algorithm is reduced because it assumed a full power signal. The linearity of the amplifier can therefore be reduced. One result of the reduced linearity is a rise in the relative power of intermodulation products in the output signal.
It is therefore an object of the present invention to provide a power amplifier in which the linearity of an output signal for an input signal of varying power levels is improved.
The present invention provides a power amplifier having a drain bias voltage and a terminating impedance selected such that, for a given gate bias voltage, the drain current for a DC input signal and the drain current for a pulsed input signal is substantially the same.
According to an aspect of the present invention, there is provided a power amplifier comprising:
According to another aspect of the present invention, there is provided a method of amplifying a signal using a compound semiconductor transistor, the method comprising:
When the drain-source voltage is referred to as approximately the same as the locus passing through the points on the characteristic curves, this means that the voltage is generally within about 10%, preferably about 5%, more preferably about 1% of the value of the locus at a particular gate bias voltage. Similarly, when the drain current is referred to as substantially the same for a DC signal and a pulsed signal, the drain current need not be exactly the same, but they are generally within about 10%, preferably about 5%, more preferably about 1% of each other.
The present invention is based on the fact that, for a given gate bias voltage, there exists a drain voltage and out put impedance at which the drain current is the same for a pulsed signal as for a DC signal and is invariant to quiescent bias points occurring when a pulsed signal is applied. If an amplifier operates at this point, the trapping effects that lead to memory effects do not affect the dynamic behaviour of a digitally pre-distorted amplifier, resulting in improved linearity. The existence of this point, and it's benefits to the linearity of a digitally pre-distorted amplifier, have not been previously recognised.
The nature of the input signal can be considered to derive a relationship for the terminating impedance. In one embodiment, the compound semiconductor transistor has an invariant locus (i.e. the locus passing through the points on the characteristic curves of the compound semiconductor transistor where the drain current is the substantially the same for a DC signal and a pulsed signal at the same gate bias voltage) which is approximately a straight line. In this embodiment, the compound semiconductor transistor is operated under Class B and the terminating impedance has a value of
where I0 is the maximum drain current, Vdc drain bias voltage and X is the amplitude of the fundamental frequency of the signal to be amplified.
In another embodiment, the compound semiconductor transistor has a quadratic invariant locus. In this embodiment, the compound semiconductor transistor is operated under Class B and the terminating impedance has a value of
there I0 is the maximum drain current and Vdc drain bias voltage.
In a further embodiment, the compound semiconductor transistor has an invariant locus at a constant drain voltage. In this embodiment, the compound semiconductor transistor is operated under Class B and the terminating impedance has a value of
where I0 is the maximum drain current and Vdc is the drain bias voltage.
According to a further aspect of the present invention, there is provided a power amplifier comprising:
The transient effects are generally substantially absent when the signal has returned to its quiescent level within a few milliseconds, for example about 20 ms, preferably about 10 ms, more preferably about 5 ms.
According to a still further aspect of the present invention, there is provided a method of amplifying a signal using a compound semiconductor transistor, the method comprising:
By selecting the drain bias voltage and terminating impedance to reduce transient effects, the trapping effects do no not affect a dynamic signal, improving the linearity of the output signal.
In any of the above described aspects and embodiments, the compound semiconductor transistor may be any compound semiconductor device, for example a GaAs, InP or GaN device.
Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:
The present invention is applied to standard power amplifier circuits comprising a semiconductor compound transistor and a digital pre-distorter as are generally known in the art. The digital pre-distorter may be implemented in an Field Programmable Gate Array (FPGA) or a programmable DSP. It may also be implemented using a microprocessor. The digital pre-distorter includes both memory terms and memory-less terms. The coefficients are calculated for a continuous input signal of maximum power at the fundamental frequency in accordance with standard practice known in the art.
The power amplifier circuit includes a terminating network that establishes the load impedance. A biasing circuit establishes the drain bias voltage. Such circuits are generally known to the skilled person. The embodiments of the present invention differ from the prior art in the particular values selected for the terminating network at the fundamental frequency, and in the drain bias voltage. As will be discussed in more detail below, the selection of the terminating impedance and drain bias voltage result in improved linearity.
All embodiments of the present invention operate a compound semiconductor transistor so that the load line resulting from the choice of terminating impedance and drain bias voltage approximates to the locus of points where the drain current is the same for a pulsed signal as for a DC signal and is invariant to quiescent bias points occurring when a pulsed signal is applied.
The existence of these point can be demonstrated by experiments on compound semiconductor transistors.
The present invention provides an RF impedance termination so that the transistor operates on a load line that follows the locus 8 of the points in
For maximum efficiency, the amplifier is operated in Class B. In that case the drain current Id has the form:
where I0 is the amplitude of the drain current. The Fourier Series representation is:
If the output voltage is constrained to be devoid of harmonics then:
V=V
dc(1−X sin θ) (3)
where X is the amplitude of the fundamental frequency and X≦1. From this analysis, the locus in the I-V plane (the load line in
Equation (4) is a straight line with a slope of
and V=Vdc when I=0. The resulting locus 10 is illustrated in
If the terminating load is a resistor at the fundamental frequency, having a value of R, then from equations (2) and (3)
and hence the slope of the load line is
Therefore the value of Vdc and R can be chosen such that the resulting load line follows the locus 8 shown in
Alternatively, Vdc and R can also be determined by applying pulsed modulated or Continuous Wave (CW) to a compound semiconductor transistor. The drain current is measured as a function of time immediately after the pulse has been removed. This can be done by measuring the voltage across a resistor in the drain/source circuit.
If the drain voltage is then adjusted together with the effective load impedance at the fundamental frequency, the transient effect can be substantially removed.
As proof that the present invention arrives at the optimum load and drain voltage bias condition a full power WCDMA signal was used to determine coefficients for a digital pre-distorter for supplying a signal to compound semiconductor transistor.
In the cases discussed above, the locus approximated to a straight line, in general this will not be case for most transistors. A more general solution of the locus 30 is shown in
The Fourier Series is:
If again the output voltage is constrained to be devoid of harmonics then:
V=V
dc(1−X sin θ) (10)
where X≦1. Thus, for X=1, the locus in the IV plane is:
This locus 32 is illustrated in
If the input signal is increased further, the current tends towards a square wave defined by:
This has a Fourier Series:
The locus in the limiting case is the locus 34 depicted in
Although the embodiments have been described with reference to a single compound semiconductor transistor, in alternate embodiments more than one transistor can be used.
Number | Date | Country | Kind |
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0602147.1 | Feb 2006 | GB | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/GB07/00337 | 2/1/2007 | WO | 00 | 10/24/2008 |