Embodiments described herein pertain to power amplifiers. Some embodiments relate to linearization techniques for power amplifiers.
The never-ending increasing demand for high-speed communications involves wireless devices exchanging data and control signals with other devices for a wide variety of applications, including digital audio and video. With different numbers and generations of devices and communication protocols, the signal and complexity has concomitantly increased. In many cases, signals to be transmitted are amplified by one or more amplifiers, including a power amplifier (PA). In particular, a baseband signal may be amplified by the PA before up-conversion to a radio frequency (RF) frequency for over-the-air transmission. Like many communication components, the design of the PA involves tradeoffs between power consumption, which may be a significant contributor to the overall power consumption of the wireless device, and efficiency.
Referring to
Radio IC circuitry 106 may include a receive signal path which may include circuitry to down-convert RF signals received from the front-end module circuitry 104 and provide baseband signals to the baseband processing circuitry 108. Radio IC circuitry 106 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband processing circuitry 108 and provide RF output signals to the front-end module circuitry 104 for subsequent transmission.
Baseband processing circuitry 108 may include one or more processors and control logic to process the baseband signals received from the receive signal path of the radio IC circuitry 106 and to generate the baseband signals for the transmit signal path of the radio IC circuitry 106. Baseband processing circuitry 108 may interface with applications processor 110 for generation and processing of the baseband signals and for controlling operations of the radio IC circuitry 106.
In some embodiments, the antennas 101, the front-end module circuitry 104, the radio IC circuitry 106, and baseband processing circuitry 108 may be provided on a single circuit card, such as wireless circuit card 102, although the scope of the embodiments is not limited in this respect. In some other embodiments, the antennas 101, the front-end module circuitry 104 and the radio IC circuitry 106 may be provided on a single circuit card. In some embodiments, the radio IC circuitry 106 and the baseband processing circuitry 108 may be provided on a single chip or integrated circuit (IC), such as IC 112, although the scope of the embodiments is not limited in this respect.
It should be noted that the front-end module circuitry 200 may include one or more additional components, in some embodiments. In addition, one or more components of the front-end module circuitry 200 may be arranged differently than shown in
In some embodiments, the front-end module circuitry 200 may be configured to operate in multiple frequency bands. As a non-limiting example, either the 2.4 GHz frequency spectrum or the 5 GHz frequency spectrum may be used. As another example, more than two frequency bands may be used. In these embodiments, the receive signal path of the front-end module circuitry 200 may include a receive signal path diplexer 204 to separate the signals from each spectrum as well as a separate LNA 206 for each spectrum. In these embodiments, the transmit signal path of the front-end module circuitry 200 may also include a power amplifier 210 and a filter 212 for each frequency spectrum and a transmit signal path diplexer 214 to provide the signals of one of the different spectrums onto a single transmit path for subsequent transmission by the one or more of the antennas 101 (
It should be noted that embodiments are not limited to PAs included in external front-end module circuitry. In some embodiments, one or more internal PAs integrated in silicon may be used. As a non-limiting example, one or more internal PAs may be integrated in silicon in other circuitry/components of a device, including but not limited to the radio architecture 100.
In some embodiments, the radio IC circuitry 300 may include a receive signal path and a transmit signal path. The receive signal path of the radio IC circuitry 300 may include at least mixer circuitry 302, amplifier circuitry 306 (such as the power amplifiers described below) and filter circuitry 308. The transmit signal path of the radio IC circuitry 300 may include at least one filter circuitry 311 and mixer circuitry 314. The transmit signal path may also include pre-distortion circuitry 312, in some embodiments. Radio IC circuitry 300 may also include synthesizer circuitry 304 for synthesizing a frequency 305 for use by the mixer circuitry 302 and/or the mixer circuitry 314.
In some embodiments, mixer circuitry 302 may be configured to down-convert RF signals 207 received from the front-end module circuitry 104 (
In some embodiments, the mixer circuitry 314 may be configured to up-convert input baseband signals 309 based on the synthesized frequency 305 provided by the synthesizer circuitry 304 to generate RF output signals 209 for the front-end module circuitry 104. The baseband signals 309 may be provided by the baseband processing circuitry 108 and may be processed by one or more of the filter circuitry 311 and/or pre-distortion circuitry 312. The filter circuitry 311 may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.
In some embodiments, the output baseband signals 307 and the input baseband signals 309 may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals 307 and the input baseband signals 309 may be digital baseband signals. In these alternate embodiments, the radio IC circuitry may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry. In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.
In some embodiments (e.g., when analog baseband signals are exchanged between the baseband processing circuitry 400 and the radio IC circuitry 106), the baseband processing circuitry 400 may include ADC 410 to convert analog baseband signals received from the radio IC circuitry 106 to digital baseband signals for processing by the RX BBP 402. In these embodiments, the baseband processing circuitry 400 may also include DAC 412 to convert digital baseband signals from the TX BBP 504 to analog baseband signals.
Referring to
Although the radio-architecture 100 is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), radio-frequency integrated circuits (RFICs) and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, the functional elements may refer to one or more processes operating on one or more processing elements.
In some embodiments, the radio architecture 100 may be part of a communication device such as a wireless local area network (WLAN) communication station (STA), a wireless access point (AP), user equipment WE), an Evolved Node-B (eNB), a base station or a mobile device including a Wireless Fidelity (Wi-Fi) device. In some of these embodiments, radio architecture 100 may be configured to transmit and receive signals in accordance with specific communication standards, such as one or more Institute of Electrical and Electronics Engineers (IEEE) standards, including but not limited to various IEEE 802.11 standards. Such standards may include, but are not limited to IEEE 802.11-2012, 802.11n-2009, 802.11ac, and/or 802.11 ax standards and/or proposed specifications for WLANs. In some embodiments, radio architecture 100 may be configured to transmit and receive signals in accordance with Third Generation Partnership Project (3GPP) standards including Long Term Evolution (LTE) standards. The scope of the embodiments is not limited in this respect, however, as the radio architecture 100 may also be suitable to transmit and/or receive communications in accordance with other techniques and standards. In addition, the radio architecture 100 may be configured to transmit and receive signals in multiple frequency bands in some embodiments.
In some embodiments, the radio architecture 100 may be part of a communication device such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a smart-phone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a wearable device such as a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive and/or transmit information wirelessly. In some embodiments, the communication device may include one or more of a keyboard, a display, a non-volatile memory port, multiple antennas, a graphics processor, an application processor, speakers, and other mobile device elements. The display may be an LCD screen including a touch screen
In some embodiments, the communication device may be or may be configured to operate as a mobile device and/or a stationary non-mobile device. As an example, the communication device may be an AP or an STA. In some embodiments, the communication device may also be, or may be part of, an apparatus for such a device. As an example, an STA may include the communication device in addition to other equipment, components or elements. As another example, an AP may include the communication device in addition to other equipment, components or elements. It should also be noted that some embodiments may be related to other electrical devices, electrical circuits or other devices that may or may not be related to communication.
Accordingly, the term “module” (and “component”) is understood to encompass a tangible entity, be that an entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transitorily) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples in which modules are temporarily configured, each of the modules need not be instantiated at any one moment in time. For example, where the modules comprise a general-purpose hardware processor configured using software, the general-purpose hardware processor may be configured as respective different modules at different times. Software may accordingly configure a hardware processor, for example, to constitute a particular module at one instance of time and to constitute a different module at a different instance of time.
As shown in
Processor 510 may include a general-purpose processor, an application specific integrated circuit (ASIC), or other kinds of processors. Processor 510 may include a CPU. Memory device 520 may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, phase change memory, a combination of these memory devices, or other types of memory.
I/O controller 550 may include a communication module for wired or wireless communication (e.g., communication through one or more antenna 558). Such wireless communication may include communication in accordance with WiFi communication technique, Long Term Evolution Advanced (LTE-A) communication technique, or other communication techniques. I/O controller 550 may also include a module to allow the STA 500 to communicate with other devices or systems in accordance with to one or more of the following standards or specifications (e.g., I/O standards or specifications), including Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), Ethernet, and other specifications.
Connector 555 may be arranged (e.g., may include terminals, such as pins) to allow the STA 500 to be coupled to an external device (or system). This may allow the STA 500 to communicate (e.g., exchange information) with such a device (or system) through connector 555. Connector 555 and at least a portion of bus 560 may include conductive lines that conform with at least one of USB, DP, HDMI, Thunderbolt, PCIe, Ethernet, and other specifications.
As shown in
The illustrations described above are intended to provide a general understanding of the structure of different embodiments, and are not intended to provide a complete description of all the elements and features of an apparatus that might make use of the structures described herein. In some arrangements, STA 500 does not have to include a display. Thus, display 552 may be omitted from STA 500. In some arrangements, the STA 500 does not have to include any antenna. Thus, antenna 558 may be omitted from the STA 500. In some arrangements, the STA 500 does not have to include a connector. Thus, connector 555 may be omitted from the STA 500.
The memory device 520 may include a non-transitory machine readable medium (hereinafter simply referred to as machine readable medium) on which is stored one or more sets of data structures or instructions (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions. The term “machine readable medium” may include any medium that is capable of storing, encoding, or carrying instructions for execution by the STA 500 and that cause the STA 500 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine readable medium examples may include solid-state memories, and optical and magnetic media. Specific examples of machine readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; Random Access Memory (RAM); and CD-ROM and DVD-ROM disks.
The instructions may further be transmitted or received over a communications network using a transmission medium utilizing any one of a number of wireless local area network (WLAN) transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks. Communications over the networks may include one or more different protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi, IEEE 802.16 family of standards known as WiMax, IEEE 802.15.4 family of standards, a Long Term Evolution (LTE) family of standards, a Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, a next generation (NG)/5th generation (5G) standards among others. In an example, the network interface device may include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the transmission medium.
Note that the term “circuitry” as used herein refers to, is part of, or includes hardware components such as an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group), an Application Specific Integrated Circuit (ASIC), a field-programmable device (FPD) (e.g., a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable SoC), digital signal processors (DSPs), etc., that are configured to provide the described functionality. In some embodiments, the circuitry may execute one or more software or firmware programs to provide at least some of the described functionality. The term “circuitry” may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) with the program code used to carry out the functionality of that program code. In these embodiments, the combination of hardware elements and program code may be referred to as a particular type of circuitry.
The term “processor circuitry” or “processor” as used herein thus refers to, is part of, or includes circuitry capable of sequentially and automatically carrying out a sequence of arithmetic or logical operations, or recording, storing, and/or transferring digital data. The term “processor circuitry” or “processor” may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single- or multi-core processor, and/or any other device capable of executing or otherwise operating computer-executable instructions, such as program code, software modules, and/or functional processes.
In the detailed description and the claims, a list of items joined by the term “at least one of” may mean any combination of the listed items. For example, if items A and B are listed, then the phrase “at least one of A and B” means A only; B only; or A and B. In another example, if items A, B, and C are listed, then the phrase “at least one of A, B and C” means A only; B only; C only; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.
To increase the efficiency of spectrum use, various modulation schemes have been developed. One such digital modulation scheme, Quadrature Amplitude Modulation (QAM), is a combination of both amplitude and phase modulation techniques in which two carriers shifted in phase by 90 degrees are modulated and the resultant output includes both amplitude and phase variations. Modern wireless communication protocols such as IEEE 802.1 lac use 256 QAM, with IEEE 802.11ax use 1024 QAM. In such systems, a particular type of power amplifier—a Doherty power amplifier may be used to achieve back-off efficiency improvement.
The Doherty power amplifier combines two amplifiers, a main (carrier) amplifier and an auxiliary (peaking) amplifier. The main and auxiliary amplifiers are biased differently. The main amplifier is biased at Class AB or Class B that delivers power at any power level. The auxiliary amplifier is biased at Class C that only conducts over high power region. The Doherty amplifier improves the power added efficiency (PAE) compared to a normal power amplifier at backed off power levels.
During operation, the main amplifier is used to accommodate power levels around the average power level of the input signal; the auxiliary amplifier is biased that operation starts only when large peaks are present that the main amplifier would not be able to accommodate. Up to a 6 dB power backoff (PBO), the main amplifier operates with a load impedance of 2×RLΩ, while the auxiliary amplifier is deactivated to achieve a peak efficiency at 6 dB PBO. The PBO is the power level below the saturation point at which the amplifier operates in the linear region even if there is a slight increase in the input power level; 6 dB PBO is thus 6 dB below the saturation point. From 6 dB PBO to 0 dB PBO, the auxiliary amplifier is activated and modulates the load impedance of the main amplifier (RLΩ at 0 dB PBO) and the Doherty power amplifier achieves another peak efficiency at 0 dB PBO. Typically, the Class-AB main amplifier is designed (sized) to achieve a peak efficiency at 6 dB PBO with a load impedance of 2×RL Ω.
The main amplifier of the Doherty power amplifier is designed to have a desired device size and bias point to achieve a high efficiency both with a load impedance of 2×RL at 6 dB PBO and RL at 0 dB PBO. However, as usual, a tradeoff exists between 6 dB PBO efficiency (load impedance of 2×RL) and 0 dB PBO efficiency (load impedance of RL) with the given device size of a Class-AB biased main power amplifier. For example, a Class-AB biased main amplifier size designed to achieve a high efficiency at 6 dB PBO with the load impedance of 2×RL has a degraded efficiency at 0 dB PBO due to the load impedance modulation (RL at 0 dB PBO) and corresponding driving capability. Furthermore, the linearity of the Doherty power amplifier is also degraded due to the load impedance modulation and driving capability of main amplifier.
In order to address these challenges, in some embodiments one or more Class-C biased power amplifiers may be provided as additional amplifiers in parallel with the Class-AB power amplifier in the main amplifier in addition to using one or more Class-C power amplifiers in the auxiliary amplifier. In this case, the Class-AB power amplifier in the main amplifier may be sized/optimized to achieve the highest efficiency with a load impedance of 2×RL at 6 dB PBO and the added Class-C power amplifier may be sized/optimized to achieve the highest efficiency when used together with the parallel Class-AB power amplifier with a load impedance of RL at 0 dB PBO. The additional Class-C power amplifier(s) in the main amplifier may improve the driving capability of the main amplifier in the Doherty power amplifier in the 6 dB PBO to 0 dB PBO region as well as improving the linearity of the Doherty power amplifier, thereby relaxing the tradeoff between 6 dB PBO efficiency and 0 dB PBO efficiency with device size.
The phase linearity of the power amplifier supports a spectrum efficient modulation scheme such as 256 QAM with a wide modulation bandwidth. The phase distortion of the power amplifier is often due to power amplifier output capacitance variations over power {power amplifier output device capacitance (Cdev)} that modulates the phase response of the power amplifier output passive network (L-C network), resulting in amplitude modulation-phase modulation (AM-PM) distortion of the power amplifier. Therefore, to minimize the AM-PM distortion of the power amplifier, the power amplifier output device output capacitance variations may be reduced over power. The bias scheme and power amplifier topology described herein can compensate the power amplifier output device capacitance variation over power. The Doherty power amplifier may use one or more biasing circuits to bias the various amplifiers, as well as separate tuning inputs to tune cascode transistors of one or more of the amplifiers.
As above, the splitter 602 introduces a 90° phase shift on one leg. The Doherty power amplifier power combiner 608 may adjust the phase of the signals from at least one of the main and auxiliary amplifiers 604, 606 to compensate for (i.e., cancel) this phase shift. In addition, however, the main and auxiliary amplifiers 604, 606 may themselves introduce a phase shift. This amplifier phase shift may not be match as each of the main and auxiliary amplifiers 604, 606 is designed to handle different power levels. Moreover, it is desirable for the impedances and linearities of the main and auxiliary amplifiers 604, 606 to be maintained over the operating range, the latter of which may encounter distortion when the auxiliary amplifier 604 activates.
The main amplifier 606 contains at least two individual power amplifiers: a Class-AB power amplifier 606a in addition to a main Class-C power amplifier 606b, which may be independently activated and deactivated. The addition of the main Class-C power amplifier 606b enables the main amplifier 606 to provide the efficiency described above in the Doherty power amplifier 600. In particular, the Class-AB power amplifier 606a in the main amplifier 606 is sized/optimized to achieve the highest efficiency with a load impedance of 2×RL at 6 dB PBO and the main Class-C power amplifier 606b is sized/optimized to achieve the highest efficiency together with the parallel Class-AB power amplifier 606a with a load impedance of RL at 0 dB PBO.
In operation, the Class-AB power amplifier 606a operates with a load impedance of 2×RL up to about 6 dB PBO. As used herein, about x dB includes up to about 0.1 dB. Since the Class-AB power amplifier 606a is optimized/sized with a load impedance of 2×RL, the Class-AB power amplifier 606a achieves the highest first peak efficiency at 6 dB PBO. However, the main Class-C power amplifier 606b is deactivated up to about 6 dB PBO. A power detector 610 may be used to sense the voltage or power of the RF signal before the RF signal is applied to the splitter 602. In other embodiments, the power detector 610 may be used to detect the voltage or power of the RF signal between splitter 602 and the main amplifier 606. The power detector 610 may provide an indication to a controller 612, such as a processor, which may independently activate/deactivate the main Class-C power amplifier 606b and auxiliary amplifier 604, as well as control other aspects of the Doherty power amplifier 600 as indicated herein.
From about 6 dB PBO to about 0 dB PBO, with increasing input power, the auxiliary amplifier 604 (which is a Class-C power amplifier) starts delivering RF current and modulates the load impedance of the main amplifier 604. At the same time, the Class-C power amplifier 606b in main amplifier 606 starts delivering RF current to the load, enhancing driving capability of main amplifier 606 for the reduced load impedance. Together with the (Class-C power amplifier) auxiliary amplifier 604, and the Class-AB power amplifier 606a and the Class-C power amplifier 606b of the main amplifier 606 enhance a second peak efficiency at 0 dB PBO. Furthermore, the Class-C power amplifier 606b of main amplifier 606 provides an expansive gain response (positive third harmonic coefficient) and compensates a compressive gain response of the Class-AB power amplifier 606a (negative third harmonic coefficient), linearizing the overall gain response of the Doherty power amplifier 600 from about 6 dB PBO to about 0 dB PBO. For more precise control of turn on point of the auxiliary amplifier 604 and the Class-C power amplifier 606b of the main amplifier 606, adaptive bias techniques can be employed to further enhance the efficiency and linearity the Doherty power amplifier 600.
To support a spectrum-efficient modulation scheme such as 256 QAM with a wide modulation bandwidth, the phase linearity of the Doherty power amplifier 600 is considered. The phase distortion of a power amplifier is often due to output capacitance variations of the power amplifier over power {power amplifier output device capacitance (Cdev)} that modulates the phase response of the power amplifier output passive network (L-C network), resulting in AM-PM distortion of the power amplifier. The power-dependent Cdev is mainly due to the Cgd variations of a cascode transistor over the operating region of the cascode transistor (saturation, triode, etc. due to the large voltage swing at the drain).
Adaptive bias techniques involve changing bias of the power amplifier dynamically (rather than using a fixed bias point) so that the turn on point can be more precisely controlled. One example of an adaptive bias technique may use a diode-connected NMOS in which the gate and drain terminal are connected together. The diode-connected NMOS may have a small DC current flowing into the drain terminal. The shorted drain/gate terminal may have a DC operation point close to the threshold voltage of the NMOS (Vth). Adaptive bias can be based on the Vth with a fixed DC value lower than Vth (i.e., Vth−ΔV) for a Class-C device, or a fixed DC value higher than Vth (i.e., Vth+ΔV) for a Class-AB device. A voltage adder or subtractor may be implemented by a summing amplifier or subtractor amplifier. The adaptive bias is to set a particular power amplifier (e.g., Class-AB or Class-C) constantly over process and temperature, which can vary Vth and may change the mode of the amplifier.
The output capacitance can thus be averaged (either using the parallel scheme shown in
In addition to linearity, it is desirable to increase the power amplifier reliability. One power amplifier arrangement to increase reliability is to stack power amplifiers, however distortion of the stacked stage degrades the linearity performance. High DC current in the transconductance (gm) stage to boost the gain and linearity increases the static and dynamic currents in the stacked stages. The differences at the stack stage NMOS gate, source, and drain terminals introduces the non-linearity of the NMOS transconductance and capacitances, which degrades the power amplifier linearity.
As shown in
As shown in
Each shunt network 1008 includes a low pass filtering inductor that is resonant with a parasitic capacitance (the capacitance between the source and drain) for each stacked NMOS source terminal input. The shunt network 1008 of each amplifier stage 1004a, 1004b, . . . 704n contains a resistor (Rn), two identical inductors (first inductor LnP and second inductor LnN), and a decoupling capacitor (CnD) coupled to ground. The first inductor LnP is coupled between node B, which is between resistor Rn and decoupling capacitor CnD, and node P, which is between the drain of the NMOS transistor NP_Sn of the amplifier stage 1004n and the source of the NMOS transistor NP_Sn+1 of the next amplifier stage 1004n+1. Similarly, the second inductor LnN is coupled between node B, and node N, which is between the drain of the NMOS transistor NN_Sn of the amplifier stage 1004n and the source of the NMOS transistor NN_Sn+1 of the next amplifier stage 1004n+1. Thus, as shown in
For the first amplifier stage 1004a, the parasitic capacitance looking into node P from the inductor L1P is Cpar. The inductor L1P resonates with Cpar at the RF frequency (ω) and is selected using:
This permits the DC current to pass through the inductor L1P. The RF signal in current mode has a relatively high impedance formed by the parasitic capacitance Cpar and the inductor L1P. The current loss that is caused by the parasitic capacitance (Cpar, which resonates with L1P) is thus reduced. The DC voltage of node P is about (VbiasCAS1−Vth). The DC current IB1 is determined by the supply voltage VDD_L1 and the DC voltage of node P:
That is VDD_L1 is higher than the voltage at node P, so that current flows to the drain of the gm stage 1002 transistor coupled to transistor NP_S1. This allows the shunt of the DC current flowing through the amplifier stages to be controlled and provides a lower overall power consumption by reducing the current draw from voltage VDD_H supplied by the output matching stage 1010 shown in
The input terminal of the first amplifier stage 1004a at the positive side is node P; the input terminal at the negative side of the first amplifier stage 1004a is node N. The RF current flows into the source terminal of NMOS FET—NP_S1 and NN_S1. The input impedance of NP_S1 or NN_S1 is
which can be relatively small. The gm is the transconductance of NP_S1 or NN_S1.
As shown in
At operation 1202, an RF signal to be amplified by a power amplifier is split along two paths. The split RF signal is provided to a main amplifier that includes a Class-AB amplifier and a Class-C amplifier in parallel with the Class-AB amplifier on one of the paths, and an auxiliary power amplifier that includes Class-C amplifier along the other of the paths.
At operation 1204, the power of the RF signal is determined. That is, a power detector may determine whether the RF signal is greater than a predetermined threshold. The threshold may be, for example, 6 dB PBO for the Class-AB amplifier.
If it is determined at operation 1204 that the power of the RF signal is not greater than the threshold, a controller selects the amplification of the power amplifier so that the RF signal is only amplified by the Class-AB amplifier at operation 1208.
If it is determined at operation 1204 that the power of the RF signal is greater than the threshold, the controller activates the Class-C amplifier of the main amplifier and the auxiliary amplifier at operation 1206 in addition to the Class-AB amplifier at operation 1208. The amplified signals from the main amplifier and the auxiliary amplifier are then combined. Thus, the amplification of the power amplifier is a combination of all three amplifiers when the RF signal is greater than the threshold.
The above description and the drawings illustrate some embodiments of the inventive subject matter to enable those skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.
The Abstract is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.