Patent Application
20240213934
This application claims priority to and the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2022-0182693 filed in the Korean Intellectual Property Office on Dec. 23, 2022, the entire contents of which are incorporated herein by reference for all purposes.
The following description relates to a power amplifier.
Wireless communication systems apply various digital modulation and demodulation schemes according to the evolution of communication standards. The existing code division multiple access (CDMA) communication system adopts the quadrature phase shift keying (QPSK) method, and the wireless LAN following the IEEE communication standard adopts the orthogonal frequency division multiplexing (OFDM) method. In addition, long term evolution (LTE) and LTE-Advanced, which are recent 3GPP standards, adopt QPSK, quadrature amplitude modulation (QAM), and OFDM schemes.
A transmitter used in a wireless communication system includes a power amplifier that amplifies a radio frequency (RF) signal to increase a transmission distance.
When a power voltage supplied to the power amplifier exceeds a threshold level, a situation in which the power amplifier transmits power exceeding its physical limit may occur. A method of protecting the power amplifier in this situation is called overvoltage protection (OVP). Here, a situation in which the power voltage exceeds the threshold level may occur when a battery voltage is unstable.
On the other hand, when a load impedance of the power amplifier is changed, a large amount of current flows, which may cause a situation in which the power amplifier transmits power exceeding its physical limit. Accordingly, it may be necessary to design a power amplifier that stably operates even in a situation in which an output current of a design limit or more is applied thereto. A technique of limiting an output current of a power amplifier is called overcurrent protection (OCP).
However, conventionally, OVP and OCP independently operate, and a power aspect is not considered. Because of this, the power amplifier may not be properly protected in abnormal situations.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
This Summary is provided to introduce a selection of concepts in simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one general aspect, a power amplifier includes: a power transistor configured to receive a power voltage; a first transistor including a first terminal configured to provide a bias current to the power transistor; and an overpower protection circuit configured to generate a first current corresponding to the power voltage and to provide the first current to a second terminal of the first transistor. The overpower protection circuit includes: a limiting current source configured to provide a limiting current to the second terminal of the first transistor; and a sink current generating circuit including a second transistor that includes a control terminal to which a voltage corresponding to the power voltage is applied and a first terminal connected to the second terminal of the first transistor, and configured to sink a second current from the limiting current.
When the power voltage increases, the second current may increase, and the first current may decrease.
When the power voltage is higher than a first voltage, the first current may decrease as the power voltage increases.
The first current may have a value obtained by subtracting the second current from the limiting current.
The sink current generating circuit may include a first resistor including a first end connected to the power voltage and a second resistor connected between a second end of the first resistor and a ground, and the second end of the first resistor may be connected to the control terminal of the second transistor.
The sink current generating circuit may further include a third resistor connected to a second terminal of the second transistor and the ground.
The second current may flow from the second terminal of the first transistor to the first terminal of the second transistor.
The first terminal of the first transistor may be an emitter, and the second terminal of the first transistor may be a collector.
In another general aspect, a power amplifier includes: a power transistor configured to receive a power voltage; a first transistor including a first terminal configured to provide a bias current to the power transistor; and an overpower protection circuit configured to generate a first current corresponding to the power voltage and to provide the first current to a second terminal of the first transistor. The overpower protection circuit is configured to generate the first current having a first value when the power voltage is higher than a first reference voltage, and the overpower protection circuit is configured to generate the first current having a second value when the power voltage is higher than a second reference voltage, and the second reference voltage is higher than the first reference voltage, and the second value is smaller than the first value.
The overpower protection circuit may generate the first current having a third value when the power voltage is lower than the first reference voltage, and the third value may be larger than the first value.
The overpower protection circuit may include a first comparator that compares the power voltage and the first reference voltage, and a second comparator that compares the power voltage and the second reference voltage.
The overpower protection circuit may further include a logic circuit that receives an output of the first comparator and an output of the second comparator and generates a logic signal, and a current source that generates the first current in response to the logic signal.
The first terminal of the first transistor may be an emitter, and the second terminal of the first transistor may be a collector.
In another general aspect, a power amplifier includes: a power transistor configured to receive a power voltage; a transistor configured to provide a bias current to the power transistor; and an overpower protection circuit configured to: generate a first current having a first value based on a comparison between the power voltage and a first reference voltage; generate a second current having a second value based on a comparison between the power voltage and a second reference voltage; and provide the first current or the second current to the transistor.
The second reference voltage may be higher than the first reference voltage, and the second value may be smaller than the first value.
The overpower protection circuit may include: a limiting current source configured to provide a limiting current to the transistor; and a sink current generating circuit including a second transistor that includes a control terminal to which a voltage corresponding to the power voltage is applied and a first terminal connected to the transistor, and configured to sink a second current from the limiting current.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent to one of ordinary skill in the art. The sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent to one of ordinary skill in the art, with the exception of operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that would be well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to one of ordinary skill in the art.
Herein, it is noted that use of the term “may” with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists in which such a feature is included or implemented while all examples and embodiments are not limited thereto.
Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.
Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.
The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.
Due to manufacturing techniques and/or tolerances, variations of the shapes illustrated in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes illustrated in the drawings, but include changes in shape that occur during manufacturing.
The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.
The drawings may not be to scale, and the relative sizes, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
Herein, an RF signal includes Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated thereafter, but is not limited thereto.
In addition, unless explicitly described to a first contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
As shown in
The input matching network 100 may be connected to an input terminal (B) (for example, a base) of the power transistor 200, and it performs impedance matching between an input radio frequency (RF) signal RFIN and the power transistor 200. The output matching network 300 may be connected to an output terminal (for example, a collector) of the power transistor 200, and it performs impedance matching between the output RF signal RFOUT and a next stage (for example, a next stage of the power amplifier). The input matching network 100 and the output matching network 300 may each be implemented as a combination of at least one of a resistor, an inductor, and a capacitor.
The power transistor 200 may amplify power for the RF signal RFIN inputted to the input terminal (B) and then output it to the output terminal (the collector). That is, an RF signal to be amplified may be inputted to the base of the power transistor 200, and the collector of the power transistor 200 may output the amplified RF signal. An emitter of the power transistor 200 may be connected to the ground, and although not shown in
On the other hand, in an abnormal state, a case in which the current ICC excessively flows may occur. An example of the abnormal state may be a case in which a load impedance of the power transistor 200 considerably varies. If the current ICC is excessively increased, the power transistor 200 may be damaged or destroyed. Hereinafter, such an abnormal state is referred to as an ‘overcurrent protection (OCP) state’.
In the abnormal state, the power voltage VCC may become excessively high. An example of the abnormal state may be when the battery is unstable. Even when the power voltage VCC becomes excessively high, the power transistor 200 may be damaged or destroyed. Hereinafter, such an abnormal state is referred to as an ‘overvoltage protection (OVP) state’.
In order to prevent the OCP state and the OVP state, the overpower protection circuit 600 according to the example supplies an adjustment limiting current ILIM_ADJ corresponding to the power voltage VCC to the bias circuit 400 to protect the power transistor 200 from overpowering.
The power transistor 200 may be realized as various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the power transistor 200 is shown as an n-type transistor in
A coupling capacitor Cc may be connected to the input terminal (the base) of the power transistor 200. The coupling capacitor Cc may perform a function of blocking a direct current (DC) component from an RF signal.
The bias circuit 400 receives a reference current IREF from the reference current generating circuit 500 and the adjustment limiting current ILIM_ADJ from the overpower protection circuit 600. The bias circuit 400 may generate a bias current IBIAS required by the power transistor 200 by using the reference current IREF and the adjustment limiting current ILIM_ADJ. The bias current IBIAS is supplied to the input terminal B of the power transistor 200, and a bias level (bias point) of the power transistor 200 may be set by the bias current IBIAS. As an example, a maximum value of the bias current IBIAS may be limited by the adjustment limiting current ILIM_ADJ, which will be described in more detail below.
The reference current generating circuit 500 may generate the reference current IREF and supply it to the bias circuit 400. As an example, the reference current generating circuit 500 may generate different reference currents IREF according to a power mode of the power amplifier 1000. When the power mode is a high power mode, the reference current generating circuit 500 may generate a reference current IREF_HPM. When the power mode is a low power mode, the reference current generating circuit 500 may generate a reference current IREF_LPM. Here, an amount of the reference current IREF_HPM may be larger than that of the reference current IREF_LPM. A method for generating the reference current IREF by the reference current generating circuit 500 may be conventional, so a detailed description thereof will be omitted.
The overpower protection circuit 600 may generate the adjustment limiting current ILIM_ADJ and supply it to the bias circuit 400. The overpower protection circuit 600 may receive the power voltage VCC, and may generate the adjustment limiting current ILIM_ADJ in response to the power voltage VCC. That is, the overpower protection circuit 600 may protect the power transistor 200 by generating the adjustment limiting current ILIM_ADJ considering the OCP state as well as the OVP state. A typical overcurrent protection circuit may detect only the OCP state to generate a limiting current. In contrast, the overpower protection circuit 600 may generate a limiting current (that is, the adjustment limiting current) additionally reflecting the OVP state.
As shown in
The transistors T1 to T3 may be realized as various transistors such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). Although the transistors T1 to T3 are shown as n-type transistors in
A base and a collector of the transistor T1 may be connected to each other, and the collector of the transistor T1 may be connected to a current source IREF through the resistor R1. The transistor T1 may have a diode-connection structure. The transistor T1 serves to sink a current I2 from the current source IREF. Since the reference current generating circuit 500 supplies the reference current IREF to the bias circuit 400, the reference current generating circuit 500 is indicated as a current source IREF in
A base and a collector of the transistor T2 may be connected to each other, and the collector of the transistor T2 may be connected to an emitter of transistor T1. The transistor T2 may have a diode-connection structure, and an emitter of the transistor T2 may be connected to the ground. Although not shown in
A collector of the transistor T3 may be connected to a current source ILIM, and a base of the transistor T3 may be connected to the base of the transistor T2. An emitter of the transistor T3 may be connected to the input terminal (B) of the power transistor 200, and may supply a bias current IBIAS to the power transistor 200. Since the overpower protection circuit 600 supplies the adjustment limiting current ILIM_ADJ to the bias circuit 400, the overpower protection circuit 600 is indicated as a current source ILIM_ADJ in
The reference current IREF is divided into a current I1 and a current I2, and the current I1 may be inputted to the base of the transistor T3. Accordingly, the bias current IBIAS may correspond to a sum of the adjustment limiting current ILIM_ADJ and the current I1. Here, since the bias current IBIAS corresponds to the base current of the power transistor 200, the bias current IBIAS and the current ICC may have a relationship of Equation 1 below.
In Equation 1, β is a common-emitter current gain of the power transistor 200.
As described above, in the OCP state, the current ICC may increase. Referring to Equation 1, as the current ICC increases, the bias current IBIAS also increases. For this reason, an increase in the adjustment limiting current ILIM_ADJ is required. In this case, the overpower protection circuit 600 may generate the adjustment limiting current ILIM in response to the power voltage VCC, and may provide the adjustment limiting current ILIM_ADJ to the collector of the transistor T3. The overpower protection circuit 600 performing this operation will be described in detail below.
As shown in
The limiting current source 610 may generate a power voltage VBAT by using a limit current ILIM, and may provide a limiting current ILIM to a collector of a transistor T3. Here, the limiting current ILIM is a current provided in the OCP state, and a method of generating the limiting current ILIM by the limiting current source 610 may be conventional, so a detailed description thereof will be omitted. As an example, the limiting current source 610 may include a plurality of transistors having a current mirror structure. The power voltage VBAT may be a battery voltage.
The sink current generating circuit 620 may receive a power voltage VCC, and may generate a sink current ISINK in response to the power voltage VCC. In addition, the sink current generating circuit 620 may sink as much as the sink current ISINK from the limiting current ILIM outputted from the limiting current source 610.
As shown in
One end of the resistor R2 may be connected to the power voltage VCC. That is, one end of the resistor R2 may be connected to a collector of a power transistor 200 to which the power voltage VCC is applied. One end of the resistor R3 may be connected to the other end of the resistor R2, and the other end of the resistor R3 may be connected to the ground. In
The gate of the transistor T4 may be connected to the junction between resistor R2 and resistor R3. In addition, a drain of the transistor T4 may be connected to the collector of the transistor T3. That is, the drain of the transistor T4 may be connected to the limiting current source 610. The resistor R4 may be connected between the source of the transistor T4 and ground. The transistor T4 may sink as much as the sink current ISINK from the limiting current ILIM outputted from the limiting current source 610. That is, a current flowing through the drain of transistor T4 is the sink current ISINK. In
In
The voltage VA is inputted to the gate of the transistor T4. When the voltage VA is higher than a threshold voltage of the transistor T4, the transistor T4 may be turned on. Here, the power voltage VCC at which the transistor T4 is turned on is referred to as a ‘threshold power voltage VCC_TH’. That is, when the power voltage is higher than the threshold power voltage VCC_TH, the transistor T4 may be turned on.
When the transistor T4 is turned on, the transistor T4 may generate the sink current ISINK. Since the sink current ISINK flows to the source of the transistor T4 through the drain thereof, the sink current ISINK may satisfy a relationship of Equation 3 below.
In Equation 3, VTH represents the threshold voltage of the transistor T4. A source voltage of the transistor T4 is ‘VA-VTH’, and Equation 2 may be applied instead of VA. In addition, since the source voltage of the transistor T4 is ISINK·R4, the relationship of Equation 3 may be derived.
Referring to Equation 3, the sink current ISINK is proportional to the power voltage VCC. As the power voltage VCC become higher, the sink current ISINK become larger. That is, as the power voltage VCC increases, the sink current ISINK increases.
When the power voltage VCC is higher than the threshold power voltage VCC_TH, the transistor T4 is turned on. In this case, the sink current ISINK is generated, and the sink current ISINK increases as the power voltage VCC increases.
On the other hand, the adjustment limiting current ILIM_ADJ may have a relationship of Equation 4 below.
Referring to Equation 4, the adjustment limiting current ILIM_ADJ decreases as the sink current ISINK increases. That is, when the power voltage VCC becomes higher, the adjustment limiting current ILIM_ADJ may become smaller.
When the power voltage VCC is lower than the threshold power voltage VCC_TH, the transistor T4 is turned off. In this case, the sink current generating circuit 620 does not generate the sink current ISINK. Accordingly, the adjustment limiting current ILIM_ADJ has the same value as the limit current ILIM.
When the power voltage VCC is higher than the threshold power voltage VCC_TH, the transistor T4 is turned on. Referring to Equation 3, the sink current ISINK increases as the power voltage VCC increases. Referring to Equation 4, when the power voltage VCC increases, the adjustment limiting current ILIM_ADJ decreases. As shown in
In
As shown in
The first comparator 630 may include a non-inverting terminal (+) and an inverting terminal (−). A power voltage VCC may be inputted to the non-inverting terminal (+) of the first comparator 630, and a reference voltage VREF1 may be inputted to the inverting terminal (−) of the first comparator 630. The non-inverting terminal (+) of the first comparator 630 may be connected to the power voltage VCC. That is, the non-inverting terminal (+) of the first comparator 630 may be connected to a collector of a power transistor 200 to which the power voltage VCC is applied. Here, the reference voltage VREF1 is a voltage arbitrarily set to detect an overvoltage state of the power voltage VCC. The first comparator 630 may compare the power voltage VCC and the reference voltage VREF1 to output a control voltage VCNT1. When the power voltage VCC is higher than the reference voltage VREF1, the first comparator 630 may output a high level control voltage VCNT1_H. When the power voltage VCC is lower than the reference voltage VREF1, the first comparator 630 may output a low level control voltage VCNT1_L.
The second comparator 640 may include a non-inverting terminal (+) and an inverting terminal (−). The power voltage VCC may be inputted to the non-inverting terminal (+) of the second comparator 640, and a reference voltage VREF2 may be inputted to the inverting terminal (−) of the second comparator 640. The non-inverting terminal (+) of the second comparator 640 may be connected to the power voltage VCC. That is, the non-inverting terminal (+) of the second comparator 640 may be connected to the collector of a power transistor 200 to which the power voltage VCC is applied. Here, the reference voltage VREF2 is a voltage arbitrarily set to detect an overvoltage state of the power voltage VCC. The reference voltage VREF2 may have a higher level than the reference voltage VREF1. The second comparator 640 may compare the power voltage VCC and the reference voltage VREF2 to output a control voltage VCNT2. When the power voltage VCC is higher than the reference voltage VREF2, the second comparator 640 may output a high level control voltage VCNT2_H. When the power voltage VCC is lower than the reference voltage VREF2, the second comparator 640 may output a low level control voltage VCNT2_L.
The logic circuit 650 may receive the control voltage VCNT1 of the first comparator 630 and the control voltage VCNT2 of the second comparator 640 to generate a logic signal VLOG. The logic circuit 650 may output the generated logic signal VLOG to the adjustable limiting current source 660. Here, the logic signal VLOG may include a logic signal VLOG1, a logic signal VLOG2, and a logic signal VLOG3. When the low level control voltage VCNT1_L is inputted from the first comparator 630 and the low level control voltage VCNT2_L is inputted from the second comparator 640, the logic circuit 650 may generate a logic signal VLOG1. When the high level control voltage VCNT1_H is inputted from the first comparator 630 and the low level control voltage VCNT2_L is inputted from the second comparator 640, the logic circuit 650 may generate a logic signal VLOG2. When the high level control voltage VCNT1_H is inputted from the first comparator 630 and the high level control voltage VCNT2_H is inputted from the second comparator 640, the logic circuit 650 may generate a logic signal VLOG3. A method of the logic circuit 650 generating a logic signal according to an input signal may be conventional, so a detailed description thereof will be omitted.
The adjustment limiting current source 660 may be connected between the power voltage VBAT and the collector of the transistor T3. The adjustment limiting current source 660 may generate the adjustment limit current ILIM_ADJ by using the power voltage VBAT and the logic signal VLOG, and may provide the adjustment limiting current ILIM_ADJ to the collector of the transistor T3.
When the logic signal VLOG is the logic signal VLOG1, the adjustment limiting current source 660 may generate and output the limiting current ILIM. When the logic signal VLOG is the logic signal VLOG2, the adjustment limiting current source 660 may generate and output the adjustment limiting current ILIM_ADJ1. When the logic signal VLOG is the logic signal VLOG3, the adjustment limiting current source 660 may generate and output the adjustment limiting current ILIM_ADJ2. Here, the adjustment limiting current ILIM_ADJ1 may have a value smaller than the adjustment limiting current ILIM, and the adjustment limiting current ILIM_ADJ2 may have a smaller value than the adjustment limiting current ILIM_ADJ1. A method of the adjustment limiting current source 660 generating the limiting current ILIM and the adjustment limiting current ILIM_ADJ by using the logic signal VLOG may be conventional, so a detailed description thereof will be omitted. As an example, the adjustment limiting current source 660 may include a plurality of transistors having a current mirror structure, and the turning on and off of the plurality of transistors may be controlled by the logic signal VLOG.
When the power voltage VCC is lower than the reference voltage VREF1, the first comparator 630 may output the low level control voltage VCNT1_L, and the second comparator 640 may also output the low level control voltage VCNT2_L. In this case, the logic circuit 650 may generate the logic signal VLOG1 in response to the low level control voltage VCNT1_L and the low level control voltage VCNT2_L. The adjustment limiting current source 660 may generate and output the limiting current ILIM in response to the logic signal VLOG1.
When the power voltage VCC is higher than the reference voltage VREF1 and lower than the reference voltage VREF2, the first comparator 630 may output the high level control voltage VCNT1_H, and the second comparator 640 may output the low level control voltage VCNT2_L. In this case, the logic circuit 650 may generate the logic signal VLOG2 in response to the high level control voltage VCNT1_H and the low level control voltage VCNT2_L. The adjustment limiting current source 660 may generate and output the adjustment limiting current ILIM_ADJ1 in response to the logic signal VLOG2. That is, when the power voltage VCC is higher than the reference voltage VREF1 and lower than the reference voltage VREF2, the adjustment limiting current source 660 may generate the smaller adjustment limiting current ILIM_ADJ1 than the limiting current ILIM to provide it to the collector of the transistor T3.
When the power voltage VCC is higher than the reference voltage VREF2, the first comparator 630 may output the high level control voltage VCNT1_H, and the second comparator 640 may output the high level control voltage VCNT2_H. In this case, the logic circuit 650 may generate the logic signal VLOG3 in response to the high level control voltage VCNT1_H and the high level control voltage VCNT2_H. The adjustment limiting current source 660 may generate and output the adjustment limiting current ILIM_ADJ2 in response to the logic signal VLOG3. When the power voltage VCC is higher than the reference voltage VREF2, the adjustment limiting current source 660 may generate the adjustment limiting current ILIM_ADJ2 smaller than the adjustment limiting current ILIM_ADJ1 to provide it to the collector of the transistor T3.
In
While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed to have a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0182693 | Dec 2022 | KR | national |
