Power amplifier

Abstract

A power amplifier being controlled by a feedback signal which is related to a product of currents each flowing through power transistors in an SEPP configuration. Current detecting transistors are connected in parallel at their base-emitter paths to the base-emitter paths of the power transistors, respectively, and detect respective currents flowing through the power transistors. An operating circuit is coupled to the current detecting transistors, and generates a current related to the product of the detected currents.

Description

FIELD OF THE INVENTION

The present invention relates to a power amplifier, and in particular to an amplifier having a single ended push-pull (SEPP) output stage.

BACKGROUND OF THE INVENTION

A power amplifier for power-amplifying an analog signal, e.g., an audio signal, must have a high power output efficiency in a large signal to noise ratio (S/N) condition, since the amplifier is used in general as an audio amplifier. An SEPP output stage consists of two amplifying sections connected to a common load circuit. One section of the SEPP output stage amplifies half cycles of an analog AC signal, and the other section amplifies the other half cycles of the AC signal.

In a conventional power amplifier, the two sections of an SEPP stage comprise two power transistors with at least one transistor being wired in an emitter-follower circuit configuration, and with a biasing circuit positioned as a pre-stage of the SEPP section. The conventional power amplifier, however, has several disadvantages mentioned below.

First, the biasing circuit is complicated, especially for an SEPP stage constructed by an emitter-grounded configuration at both sections.

Second, the power transistors are apt to be harmed by over current flowing when a large input signal is added so that the amplifier needs some form of protection circuit.

Third, the power transistors enter a cutoff condition when there is no signal at the base terminals of the transistors, so that the output signal includes a clipping noise.

Fourth, output amplitude is limited due to the use of an emitter-follower configuration, with a resistor for the biasing circuit or a resistor for an idling current circuit.

Accordingly, an object of the present invention is to provide a power amplifier with an improved biasing circuit.

A further object of the present invention is to provide a power amplifier which prevents an over current flowing through the power transistors.

Another object of the present invention is to provide a power amplifier with a small current flowing through the power transistors when there is no signal at the base of the power transistors.

A still further object of the present invention is to provide a power amplifier having a large output efficiency.

SUMMARY OF THE INVENTION

According to the present invention, a power amplifier is provided with: a preamplification stage; an output stage driven by the preamplification stage and having power transistors each coupled to a common output terminal; current detecting transistors connected in parallel at their base-emitter paths to the base-emitter paths of the power transistors for detecting currents flowing through the power transistors, respectively; an operating circuit coupled to the current detecting transistors, the operating circuit generating a feed back current which has a function related to the product of the respective currents through the power transistors; and means for feeding back the feed current from the operating circuit to the preamplification stage for keeping the feed back current constant.

Preferably, the power amplifier according to the present invention further includes a driver stage between the preamplification stage and the output stage. The output stage may comprise a pair of one conductivity type power transistors in which one of the power transistors is wired in a form of emitter-follower configuration and the other of the power transistors is wired in a form of grounded-emitter configuration.

The operating circuit preferably includes first and second transistors connected with emitter-collector path in series, respectively, to the emitter-collector paths of the current detecting transistors; first means for connecting the base-emitter paths of said first and second transistors in series; third and fourth transistors; second means for connecting the base-emitter paths of the third and fourth transistors in series circuit and for connecting the series base-emitter paths of third and fourth transistors in parallel with the base-emitter paths of the first and second transistors; and third means for connecting at least one of the collectors of the third and fourth transistors to the feedback means.

The first transistor is preferably a first conductivity type transistor connected at the collector to one of the current detecting transistors and to its own base and connected at the emitter to a power source terminal; the second transistor is preferably an opposite conductivity type transistor connected at the emitter to the other one of the current detecting transistors at the collector to said power terminal; the first means is preferably a connection between the bases of the first and second transistors; the third transistor is preferably of the first conductivity type, the fourth transistor is preferably of the opposite conductivity type transistor and is connected at the collector to both the power source terminal and to its own base; and the second means is preferably a connection between the emitters of the third and fourth transistors and between the emitter of the second transistor and the base of the third transistor.

In an alternative embodiment, the first and second transistors are preferably opposite conductivity type transistors respectively connected at their collectors to one of the current detecting transistors and to their own bases; the first means is a connection between emitters of the first and second transistors; the third and fourth transistors are opposite conductivity type transistors; and the second means is a connection between the bases of the third and fourth transistors and further is a connection between the bases of the first and third transistors and between the second and fourth transistors.

Additional objects and advantages of the present invention will become apparent to persons skilled in the art from a study of the following description and from the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a circuit diagram of a power amplifier embodying the present invention;

FIG. 2 graphically illustrates current variations flowing through transistors shown in FIG. 1;

FIG. 3 shows a detailed schematic circuit diagram of another power amplifier embodying the present invention;

FIG. 4 shows a detailed schematic circuit diagram of still another power amplifier embodying the present invention; and

FIG. 5 shows a detailed schematic circuit diagram of one more power amplifier embodying the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail with reference to the accompanying drawings. Throughout the drawings, like reference numerals will be used to designate like or equivalent portions, for simplicity of explanation.

Referring now to FIG. 1, there is shown an amplifier of one embodiment of this invention in which an output stage is constructed in a single ended push-pull (SEPP) amplifier configuration by using two NPN power transistors.

A preamplification stage 10 in the form of a differential amplifier including NPN transistors Q.sub.1 and Q.sub.2 drives output stage 12. In output stage 12, power transistors Q.sub.3 and Q.sub.4 are connected in the form of an SEPP amplifier which drives load L through a common output terminal 14. A feedback through resistors R.sub.1, R.sub.2, R.sub.3 and capacitor C.sub.1 provides an operating point stabilization of the voltage drops across the power transistors Q.sub.3 and Q.sub.4.

An input coupling network having a resistor R.sub.4, a transistor input impedance and a capacitor C.sub.2, determines the low frequency roll-off of the amplifier since the remainder of the amplifier is essentially direct coupled. Accordingly, collectors of transistors Q.sub.1 and Q.sub.2 are respectively direct-coupled to bases of the power transistors Q.sub.4 and Q.sub.3, respectively.

Resistor R.sub.5 operates as common emitter resistor for the differential amplifier transistor pair Q.sub.1 and Q.sub.2, and resistors R.sub.6, R.sub.7 and R.sub.8 operate as collector load resistors of the transistors Q.sub.1 and Q.sub.2.

Determining idle currents for the power transistors Q.sub.3 and Q.sub.4 is achieved by further circuits having transistors Q.sub.5, Q.sub.6, Q.sub.7, Q.sub.8, Q.sub.9 and Q.sub.10 connected between the bases of the power transistors Q.sub.3 and Q.sub.4 and the preamplification stage 10. Base-emitter paths of NPN transistors Q.sub.5 and Q.sub.6 are respectively coupled to the base-emitter paths of power transistors Q.sub.3 and Q.sub.4 in parallel for detecting currents IQ.sub.3 and IQ.sub.4 which flow through the power transistors Q.sub.3 and Q.sub.4. Thus, if a ratio of the emitter area of transistor Q.sub.3 to that of transistor Q.sub.5 is N, and the ratio of the emitter area of the transistor Q.sub.4 to that of the transistor Q.sub.6 is M, currents IQ.sub.5 and IQ.sub.6 flowing through transistors Q.sub.5 and Q.sub.6 are respectively related by equations (1) and (2):

IQ.sub.5 =1/N.multidot.IQ.sub.3 (1) IQ.sub.6 =1/M.multidot.IQ.sub.4 (2)

These currents IQ.sub.5 and IQ.sub.6 are combined and arithmetically operated upon by an operating circuit 16 comprising the transistors Q.sub.7, Q.sub.8, Q.sub.9 and Q.sub.10. The PNP transistor Q.sub.7 is connected between transistor Q.sub.5 and power source terminal 18, and the NPN transistor Q.sub.8 is connected between transistor Q.sub.6 and power source terminal 18. Thus, the currents IQ.sub.5 and IQ.sub.6 respectively flow through transistors Q.sub.7 and Q.sub.8. The forward base-emitter voltages V.sub.BE (Q.sub.7) and V.sub.BE (Q.sub.8) respectively of transistors Q.sub.7 and Q.sub.8 vary in accordance with the currents, IQ.sub.5 and IQ.sub.6, and are related by equations (3) and (4): ##EQU1## where K is Boltzman's constant, q is an electron charge, T is an absolute temperature, I.sub.SP is a reverse saturation current of a PNP transistor, and I.sub.SN is a reverse saturation current of an NPN transistor.

The transistor Q.sub.7 is connected at the collector to both its own base and to the base of transistor Q.sub.8, so that the emitter potential P.sub.E (Q.sub.8) of transistor Q.sub.8 becomes the sum of both base-emitter voltages V.sub.BE (Q.sub.7) and V.sub.BE (Q.sub.8). Accordingly, the emitter potential P.sub.E (Q.sub.8) is related by equation (5):

P.sub.E (Q.sub.8)=V.sub.BE (Q.sub.7)+V.sub.BE (Q.sub.8) (5)

The base of PNP transistor Q.sub.9 is connected to the emitter of the transistor Q.sub.8. The emitter of transistor Q.sub.9 is connected to power source 18 through NPN transistor Q.sub.10, and the base of transistor Q.sub.10 is also connected to power source terminal 18, so that the sum of forward base-emitter voltages V.sub.BE (Q.sub.9) and V.sub.BE (Q.sub.10) of the series transistors Q.sub.9 and Q.sub.10 is provided by the emitter potential P.sub.E (Q.sub.8) of transistor Q.sub.9, as shown by equation (6):

P.sub.E (Q.sub.8)=V.sub.BE (Q.sub.9)+V.sub.BE (Q.sub.10) (6) From the equations (5) and (6), the following equation is obtained: V.sub.BE (Q.sub.9)+V.sub.BE (Q.sub.10)=V.sub.BE (Q.sub.7)+V.sub.BE (Q.sub.8) (7) Thus, the sum of the base-emitter voltages V.sub.BE (Q.sub.9) and V.sub.BE (Q.sub.10) varies in accordance with a variation of the emitter potential P.sub.E (Q.sub.8). The base-emitter voltages V.sub.BE (Q.sub.9) and V.sub.BE (Q.sub.10) are respectively given by equations (8) and (9) in relation to a current I.sub.f flowing through the series transistors Q.sub.9 and Q.sub.10 : ##EQU2##

The equation (7) is rewritten as following, using the equations (3), (4), (8) and (9): ##EQU3##

From the equation (10), the following equations are obtained: ##EQU4##

The current I.sub.f flows into a diode-connected NPN transistor Q.sub.11 which is connected in a current mirror circuit 22 with an NPN transistor Q.sub.12, so that a current equal to the current I.sub.f is obtained in the circuit of the transistor Q.sub.12. This current I.sub.f is drawn out from the junction 20 of resistors R.sub.6, R.sub.7 and R.sub.8 and works as a feedback signal for controlling the pre-amplification stage 10.

Referring to voltage drops by the current I.sub.f and other currents, the following equation (13) is obtained: ##EQU5## where V.sub.CC is the power source potential; V.sub.BE Q.sub.3 is the voltage drop between base and emitter of the transistor Q.sub.3 ; IQ.sub.1 and IQ.sub.2 are currents respectively flowing in transistors Q.sub.1 and Q.sub.2.

In the equation (14), V.sub.CC, V.sub.BE Q.sub.3, IQ.sub.1 and IQ.sub.2 can be set by circuit design, so that the current I.sub.f is easily set to a constant value. This means that the product of IQ.sub.3.IQ.sub.4 is usually held at a constant, not zero. Accordingly, one of the power transistors Q.sub.3 and Q.sub.4 is kept in a non-cutoff condition while the other increases to a large value. Moreover, the other is prevented from excessively increasing because the former is kept at a value not zero.

FIG. 2 shows the response characteristcs of the currents IQ.sub.3, IQ.sub.4 and I.sub.C, referring to the output voltage Vout at output terminal 14. The currents IQ.sub.3 and IQ.sub.4 respectively take the same defined current values I.sub.C when no input signal is given to the input terminal 24 and, therefore, the output voltage Vout is zero. The current I.sub.C is given by equation (15), and is defined as a control current at non-input signal time: ##EQU6##

From the equations (15) and (14), it is understood that the control current I.sub.C is easily established to the desired value. Then, the currents IQ.sub.3 and IQ.sub.4 increase and decrease inversely to each other in accordance with the polarity of the input signal. The current variations of currents IQ.sub.3, IQ.sub.4 are shown by the unbroken lines in FIG. 2.

According to the first embodiment of this invention described above, the power amplifier of which the output stage is constructed with NPN transistors without an inverse Darlington connection by a PNP-NPN pair is easily obtained, and the first embodiment is especially suitable for an I.sub.C circuit technique because the output stage can be constructed with NPN transistors only. Thus, an amplifier with high power efficiency is obtained by reason of no resistors being necessary between the output terminal and the output transistors for producing idling currents. Furthermore, both output transistors are always kept in an ON condition so that the output signal has no clipping or crossover distortion.

The first embodiment described above may be modified as shown in FIG. 3. This modification is an amplifier in which a driver stage 26 in a differential amplifier with a pair of NPN transistors Q.sub.13, Q.sub.14 is employed, and the output stage 12' is constructed by two pairs of Darlington connections by NPN transistors Q.sub.15, Q.sub.3 ' and Q.sub.16, Q.sub.4 '. The current I.sub.f ' is directly fed back to the junction 20' without using a current mirror circuit. The preamplification stage 10' is constructed by PNP transistors.

In this modification, similar effects as those of the first embodiment are obtained, and a larger output power than that of the first embodiment is obtained.

Referring now to FIG. 4, there is shown an amplifier of which an output stage is constructed in a complementary SEPP amplifier configuration with two emitter-grounded amplifier sections.

A preamplifier stage 10" is in the form of a push-pull amplifier including two differential amplifier sections, each having a pair of NPN transistors Q.sub.1a, Q.sub.1b and a pair of PNP transistors Q.sub.2a, Q.sub.2b. Stage 10" drives an output stage 12". The output stage 12" includes two emitter-grounded amplifier sections each constructed by a Darlington connection by transistor pairs Q.sub.3a, Q.sub.3b and Q.sub.4a, Q.sub.4b. Collectors of the PNP power transistor Q.sub.3b and the NPN power transistor Q.sub.4b are directly connected to the common output terminal 14", and output stage 12" drives the load L" through the output terminal 14". A feedback through resistors R.sub.1 " and R.sub.2 " provides an operating point stabilization of the voltage drops across the power transistors Q.sub.3b and Q.sub.4b, in the same manner as in the first embodiment.

The input coupling network containing resistor R.sub.4 " and the input impedances of the transistors Q.sub.1a and Q.sub.2a connected at the bases in parallel determines the low frequency roll-off of the amplifier since the remainder of the amplifier is essentially direct-coupled. Specifically, the collectors of transistors Q.sub.1a and Q.sub.2a are respectively direct-coupled to the bases of transistors Q.sub.3a and Q.sub.4a in the output stage 12".

Circuits which include transistors Q.sub.1c, Q.sub.2c, diodes D.sub.1, D.sub.2, D.sub.3 and D.sub.4 and resistors R.sub.9, R.sub.10, operate the constant current supplying circuits for the differential amplifier sections in the preamplification stage 10". Resistors R.sub.11 and R.sub.12, respectively, operate as collector load resistors of the transistors Q.sub.1a and Q.sub.2a.

Determining idling currents for the power transistors Q.sub.3b and Q.sub.4b is achieved by further circuits including transistors Q.sub.5 ", Q.sub.6 ", Q.sub.7 ", Q.sub.8 ", Q.sub.9" and Q.sub.10 " connected between the bases of the power transistors Q.sub.3b and Q.sub.4b and the preamplification stage 10". Base-emitter paths of PNP transistor Q.sub.5 " and NPN transistor Q.sub.6 " are respectively coupled to the base-emitter paths of the power transistors Q.sub.3b and Q.sub.4b in parallel for detecting currents IQ.sub.3b and IQ.sub.4b which flow through the power transistors Q.sub.3a and Q.sub.3b. Thus, if each ratio of the emitter area of the transistors Q.sub.3b, Q.sub.4b to that of the transistors Q.sub.5 ", Q.sub.6 " is N, currents IQ.sub.5 " and IQ.sub.6 " flowing through the transistors Q.sub.5 " and Q.sub.6 " are respectively related by equations (16) and (17). ##EQU7##

These currents IQ.sub.5 " and IQ.sub.6 " are combined and arithmetically operated upon in operating circuit 16" comprising transistors Q.sub.7 ", Q.sub.8 ", Q.sub.9 " and Q.sub.10 ". NPN transistor Q.sub.7 " is connected between transistor Q.sub.5 " and ground, and PNP transistor Q.sub.8 " is connected between transistor Q.sub.6 " and ground. The currents IQ.sub.5 " and IQ.sub.6 ", respectively, flow through transistors Q.sub.7 " and Q.sub.8 ", and raise the base-emitter voltages V.sub.BE (Q.sub.7 ") and V.sub.BE (Q.sub.8 ") at the transistors Q.sub.7 " and Q.sub.8 ". These base-emitter voltages V.sub.BE (Q.sub.7 ") and V.sub.BE (Q.sub.8 "), respectively, vary in accordance with the currents IQ.sub.5 " and IQ.sub.6 ", and are related by equations (18) and (19). ##EQU8##

Transistors Q.sub.7 " and Q.sub.8 " are, respectively, connected at their collectors to their own bases and to the bases of transistors Q.sub.9 " and Q.sub.10 ", respectively. Transistors Q.sub.9 " and Q.sub.10 " are connected at their emitters to each other and are respectively connected at their collectors to the junctions 20a and 20b of the emitters of transistors Q.sub.1c, Q.sub.2c and the resistors R.sub.9, R.sub.10. Referring to the voltage drops between the bases of transistors Q.sub.9 " and Q.sub.10 ", the equation (20) is obtained. ##EQU9##

Now, the current I.sub.f " flowing through the transistors Q.sub.9 " and Q.sub.10 " in series from the junction 20b to the junction 20a has following the relations (21) and (22) to the base-emitter voltages V.sub.BE (Q.sub.9 ") and V.sub.BE (Q.sub.10 "): ##EQU10##

Using the equations (18), (19), (21) and (22), the equation (20) is rewritten as below: ##EQU11## From the equation (23), the following equation is obtained: ##EQU12## This current I.sub.f " is drawn out from the junction 20b and poured into the junction 20a and works as a feedback signal for controlling the preamplification stage 10". Referring to the voltage drops by the current I.sub.f " and other currents, the following equations (25) and (26) are obtained. ##EQU13## where, V.sub.D is each forward voltage drop of diodes D.sub.1, D.sub.2, D.sub.3 and D.sub.4, R.sub.A is each resistance of resistors R.sub.9 and R.sub.10, I.sub.o is each current flowing through transistors Q.sub.2c and Q.sub.1c, and is one half the current flowing through transistors Q.sub.2a, Q.sub.2b and Q.sub.1a, Q.sub.1b constituting the differential amplifier sections, Rc is each resistance of resistors R.sub.11 and R.sub.12, and V.sub.BE is each base-emitter voltage of transistors Q.sub.1c, Q.sub.2c, Q.sub.3a, Q.sub.4a and Q.sub.4b.

From the equations (25) and (26) the following equation (27) is obtained: ##EQU14## In equation (27), V.sub.D and V.sub.BE are considered as constant, and R.sub.A and R.sub.C can be set by circuit design, so that the current may easily be established at a constant value. This means that the product IQ.sub.3b IQ.sub.4b is usually held at a constant value, not zero. Accordingly, one of the power transistors Q.sub.3b and Q.sub.4b is kept in a non-cutoff condition in its non-operating time. Moreover, the other is prevented from excessively increasing condition because the current through the former is kept at a value not zero.

When the input signal at the input terminal 24" is zero and the output voltage Vout at the output terminal 14" is zero, the currents IQ.sub.3b and IQ.sub.4b respectively take the same defined value I.sub.C ". This current value I.sub.C " is given by equation (28), and defined as an idling current at a non-input signal time: ##EQU15## It is understood that idling current I.sub.C " is easily established to the desired value from the equations (28) and (27). Then, the currents IQ.sub.3b and IQ.sub.4b increase and decrease inversely to each other in accordance with the polarity of the input signal. These current variations show similar characteristics of I.sub.C, IQ.sub.3, and IQ.sub.4 shown by FIG. 2.

According to the second embodiment of this invention described above, a basic circuit is obtained to establish an idling current for an SEPP amplifier which comprises at the output stage two emitter-grounded amplifier sections coupled to a common output terminal. Furthermore, the output transistors are always kept in an ON condition so that the output signal has no crossover distortion.

Referring to FIG. 5, there is shown as amplifier of which an output stage is constructed in a complementary SEPP amplifier with conventional emitter-follower type amplifier sections connected to a common output terminal.

A preamplifier stage 10"' in the form of a differential amplifier including NPN transistors Q.sub.1 "' and Q.sub.2 "' drives a driver stage 26"' having a PNP transistor Q.sub.13 "'. Driver stage 26"' drives an output stage 12"'. Current mirror load circuit 28 comprises diodes D.sub.1 "', D.sub.2 "' and D.sub.5, resistors R.sub.13 and R.sub.14, and transistor Q.sub.17. The emitter of transistor Q.sub.17 is coupled to terminal 30"' by resistor R.sub.13, and the collector of transistor Q.sub.17 is coupled to the collector of transistor Q.sub.13 "' by the series connection of diode D.sub.5 and resistor R.sub.14. The base of transistor Q.sub.17 is coupled to ground, with the series connection of diodes D.sub.1 "' and D.sub.2 "' also coupling the base of Q.sub.17 to terminal 30"'.

Output stage 12"' includes an NPN power transistor Q.sub.3 "' and a PNP power transistor Q.sub.4 "' which are directly coupled at their emitters to a common output terminal 14"' and form a complementary SEPP type amplifier for driving a load L"' through common output terminal 14"'. Each power transistor Q.sub.3 "' and Q.sub.4 "' is connected in the form of an emitter-follower configuration. A feedback network, an input coupling network and a common emitter resistor are constructed in nearly the same arrangement as in the first embodiment (FIG. 1).

Determining the control current for the power amplifier is achieved by further circuits having transistors Q.sub.5 "', Q.sub.6 "', Q.sub.7 "', Q.sub.8 "', Q.sub.9 "', Q.sub.10 "', Q.sub.11 "' and Q.sub.12 "' connected between the bases of the power transistors Q.sub.3 "', Q.sub.4 "' and the driver stage 26"'. Base-emitter paths of the NPN transistor Q.sub.5 "' and the PNP transistor Q.sub.6 "' are respectively coupled to the base-emitter paths of the same conductivity type power transistors Q.sub.3 "', Q.sub.4 "' in parallel for detecting currents IQ.sub.3 "' and IQ.sub.4 "' which flow through the power transistors Q.sub.3 "' and Q.sub.4 "'. So, if an emitter area ratio of NPN power transistor Q.sub.3 "' to NPN transistor Q.sub.5 "' is N and that of PNP power transistor Q.sub.4 "' to PNP transistor Q.sub.6 "' is M, currents IQ.sub.5 "' and IQ.sub.6 "' flowing through the transistors Q.sub.5 "' are respectively related by equations (29) and (30): ##EQU16##

These currents IQ.sub.5 "' and IQ.sub.6 "' are combined and arithmetically operated upon by operating circuit 16"' comprising transistors Q.sub.7 "', Q.sub.8 "', Q.sub.9 "' and Q.sub.10 "'. NPN transistor Q.sub.7 "' is connected with its emitter-collector path positioned between transistor Q.sub.5 "' and the power source terminal 18"'. The emitter-collector path of PNP transistor Q.sub.8 "' is connected in series with the emitter-collector path of transistor Q.sub.12 "' between terminals 18"' and 30"'. The base of Q.sub.8 "' is connected to the collector of Q.sub.8 "' and to the base of Q.sub.7 "'. A current mirror circuit comprises a diode-connected NPN transistor Q.sub.11 "' and transistor Q.sub.12 "' with the emitter-collector path of Q.sub.11 "' coupling the collector of Q.sub.6 "' to terminal 30"', with the bases of Q.sub.11 "' and Q.sub.12 "' coupled together and to the collector of Q.sub.6 "'.

The currents IQ.sub.5 "' and IQ.sub.6 "' thus respectively flow through transistors Q.sub.7 "'and Q.sub.8 "', and raise the forward base-emitter voltages V.sub.BE (Q.sub.7 "') and V.sub.BE (Q.sub.8 "') at transistors Q.sub.7 "' and Q.sub.8 "'. These forward base-emitter voltages V.sub.BE (Q.sub.7 "') and V.sub.BE (Q.sub.8 "'), respectively, vary in accordance with the currents IQ.sub.5 "' and IQ.sub.6 "', and are related by equations (31) and (32). ##EQU17##

The transistor Q.sub.8 "' is connected at the collector to its own base and to the base of transistor Q.sub.7 "', so that the emitter potential Pe(Q.sub.7 "') of transistor Q.sub.7 "' becomes the sum of both forward base-emitter voltages V.sub.BE (Q.sub.7 "') and V.sub.BE (Q.sub.8 "'). Accordingly, the emitter potential Pe(Q.sub.7) is related by equation (33): ##EQU18##

To the emitter of the transistor Q.sub.7 "', the base of the PNP transistor Q.sub.9 "' is connected. The emitter of transistor Q.sub.9 "' is connected to the power source terminal 18"' through the NPN transistor Q.sub.10 "' of which the base is connected to power source terminal 18"', so that the sum of forward base-emitter voltages V.sub.BE (Q.sub.9 "') and V.sub.BE (Q.sub.10 "') of the series transistors Q.sub.9 "' and Q.sub.10 "' is provided by the emitter potential Pe(Q.sub.7 "'). Accordingly, the equation (34) is obtained: ##EQU19##

As a result, the sum V.sub.Be (Q.sub.9 "')+V.sub.BE (Q.sub.10 "') varies in accordance with the potential Pe(Q.sub.7 "') or the sum V.sub.BE (Q.sub.7 "')+V.sub.BE (Q.sub.8 "'). A current I.sub.f "' flowing through the series transistors Q.sub.9 "' and Q.sub.10 "' to a junction 20"' of an NPN transistor Q.sub.17 "' and a resistor R.sub.13 "' (which comprises current mirror load 28 for the driver transistor Q.sub.13 "') also varies in accordance with the potential Pe(Q.sub.7 "'). The base-emitter voltages V.sub.BE (Q.sub.9 "') and V.sub.BE (Q.sub.10 "') are respectively given by equations (35) and (36) in relation to the current I.sub.f "': ##EQU20##

Equation (34) may be rewritten as follows, using the equations (31), (32), (35) and (36): ##EQU21## From the equation (37), the following equation is obtained: ##EQU22##

The current I.sub.f "' flows into junction 20"' and works as a feedback signal for controlling driver stage 26"'. Referring to the voltage drops by the current I.sub.f "' and other currents, the following equations (39) and (40) are obtained: ##EQU23## where, V.sub.D is each forward voltage drop (=0.7 V) of the diodes D.sub.1 "', D.sub.2 "', and D.sub.5 in the current mirror load 28, R.sub.A is a resistance of the resistor R.sub.13, I.sub.o is a current flowing through the driver transistor Q.sub.13 "' and transistor Q.sub.17, V.sub.BE is each forward base-emitter voltage of the transistors Q.sub.3 "' and Q.sub.4 "', and R.sub.C is a resistance of resistor R.sub.14.

From the equations (39) and (40), the following equation (41) is obtained: ##EQU24## In this equation, V.sub.D and V.sub.BE are considered as constant, and R.sub.A and R.sub.C can be set by circuit design. Accordingly, current I.sub.f "' is also established at a constant value.

Thus, power transistors Q.sub.3 "' and Q.sub.4 "' are prevented from becoming cutoff or from having excessively increasing current.

An idling current I.sub.C "' for keeping the power transistors Q.sub.3 "' and Q.sub.4 "' non-cutoff condition in a non-operating condition is also given by equation (42) as was the case in the above mentioned embodiments: ##EQU25## Idling current I.sub.C "' is easily established to the desired value, and then the variations of currents IQ.sub.3 "', IQ.sub.4 "' can be shown as the same as in FIG. 2. Accordingly, also in the third embodiment of this invention there is shown a circuit to establish the idling current for power transistors and to keep the power transistors in a non-cutoff condition at anytime or prevent the currents flowing through the power transistors excessively increasing. Moreover, resistors connected between the power transistors and the output terminal in the conventional SEPP amplifier for flowing the idling currents are not necessary in this embodiment, so the power efficiency is higher than in conventional amplifiers.

Additional advantages and modifications will readily occur to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant's general inventive concept.

Claims

1. A power amplifier comprising:

(a) a preamplification stage;

(b) an output stage driven by said preamplification stage and having power transistors each coupled to a common output terminal;

(c) current detecting transistors connected in parallel at their base-emitter paths to the base-emitter paths of said power transistors for detecting currents flowing through said power transistors, respectively;

(d) an operating circuit coupled to said current detecting transistors, said operating circuit generating a feed back current which has a function related to the product of the respective currents through said power transistors; and

(e) means for feeding back said feed back current from said operating circuit to said preamplification stage for keeping said feed back current constant.

2. A power amplifier according to claim 1, further comprising a driver stage between said preamplification stage and said output stage.

3. A power amplifier according to claim 1 or 2, wherein said output stage comprises a pair of one conductivity type power transistors in which one of said power transistors is wired in a form of emitter-follower configuration and the other of said power transistors is wired in a form of grounded-emitter configuration.

4. A power amplifier according to claim 3, wherein said one conductivity type power transistors are NPN power transistors.

5. A power amplifier according to claim 3, wherein said power transistors are each composite transistors each connected in a Darlington configuration.

6. A power amplifier according to claim 5, wherein said composite transistors are each NPN transistors.

7. A power amplifier according to claim 1 or 2, wherein the output stage comprises a pair of complementary power transistors each coupled in a grounded-emitter amplifier configuration.

8. A power amplifier according to claim 7, wherein said power transistors are each composite transistors each connected in a Darlington configuration.

9. A power amplifier according to claim 1 or 2, wherein said output stage is constructed by a pair of complementary power transistors each wired in an emitter-follower amplifier.

10. A power amplifier according to claim 1 or 2, wherein said operating circuit comprises:

(a) first and second transistors connected with emitter-collector path in series, respectively, to the emitter-collector paths of said current detecting transistors;

(b) first means for connecting the base-emitter paths of said first and second transistors in series;

(c) third and fourth transistors;

(d) second means for connecting the base-emitter paths of said third and fourth transistors in series circuit and for connecting the series base-emitter paths of third and fourth transistors in parallel with said base-emitter paths of said first and second transistors; and

(e) third means for connecting at least one of the collectors of said third and fourth transistors to said feedback means.

11. A power amplifier according to claim 10 wherein:

(a) said first transistor is a first conductivity type transistor connected at the collector to one of said current detecting transistors and to its own base and connected at the emitter to a power source terminal;

(b) said second transistor is an opposite conductivity type transistor connected at the emitter to the other one of said current detecting transistors at the collector to said power terminal;

(c) said first means is a connection between the bases of said first and second transistors;

(d) said third transistor is a transistor of said first conductivity type;

(e) said fourth transistor is a transistor of said opposite conductivity type and is connected at the collector to both said power source terminal and to its own base; and

(f) said second means is a connection between the emitters of said third and fourth transistors and between the emitter of said second transistor and the base of said third transistor.

12. A power amplifier according to claim 10 wherein

(a) said first and second transistors are opposite conductivity type transistors respectively connected at their collectors to one of said current detecting transistors and to their own base;

(b) said first means is a connection between emitters of said first and second transistors;

(c) said third and fourth transistors are opposite conductivity type transistors; and

(d) said second means is a connection between the bases of said third and fourth transistors and further is a connection between the bases of said first and third transistors and between bases of said second and fourth transistors.