Patent Grant
8963611
I. Field
The present disclosure relates generally to electronics, and more specifically to measurement circuits for a wireless communication device.
II. Background
A wireless communication device typically includes a transmitter to support data transmission. The transmitter may have a power amplifier to amplify a radio frequency (RF) signal and provide high output power. The power amplifier may be designed to drive a particular load impedance (e.g., 50 Ohms) and to have the best possible efficiency at a maximum output power level. The power amplifier may observe a variable load impedance, which may change due to various reasons described below. Furthermore, the power amplifier may operate over a wide range of output power levels, and the efficiency of the power amplifier may decrease at lower output power levels. It may be desirable to improve the operation of the power amplifier.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs.
Power and impedance measurement circuits that may be used to measure power and/or impedance are described herein. These measurement circuits may be used for various electronics devices such as wireless communication devices, cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, Bluetooth devices, consumer electronics devices, etc. For clarity, the use of the measurement circuits in a wireless communication device is described below.
Within wireless device 100, processors 110 process data to be transmitted and provide an analog output signal to transmitter 120. Within transmitter 120, transmitter circuits 130 amplify, filter, and upconvert the analog output signal and provide an input RF signal, VIN. A power amplifier 140 amplifies the input RF signal to obtain the desired output power level and provides an amplified RF signal, VAMP. A tunable matching circuit 150 is coupled to the output of power amplifier 140, performs output impedance matching for power amplifier 140, and provides an output RF signal, VOUT, to an antenna 158.
A sensor 160 receives the amplified RF signal from power amplifier 140 and the output RF signal from tunable matching circuit 150. Sensor 160 may measure the voltage, current, power and/or other parameters of the amplified RF signal and/or the output RF signal. A computation unit 170 receives the measurements from sensor 160 and determines the power and/or impedance of a load observed by matching circuit 150. Sensor 160 and computation unit 170 collectively form a power and impedance measurement circuit 172 for wireless device 100. A control unit 180 may receive an envelope signal for the input RF signal, information indicative of an average output power level, and/or information for other parameters affecting the operation of power amplifier 140. Control unit 180 may also receive the measured power and/or impedance from computation unit 170. Control unit 180 may generate a first control to adjust tunable matching circuit 150 to achieve good performance, e.g., to improve the efficiency of power amplifier 140. Control unit 180 may also generate a second control to adjust power amplifier 140 to achieve good performance.
Processors/controllers 110 may perform various functions for wireless device 100, e.g., processing for data being transmitted. Processors/controllers 110 may also control the operation of various circuits within wireless device 100. Memory 112 may store program codes and data for processors/controllers 110. Processors/controllers 110, memory 112, computation unit 170, and control unit 180 may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.
Referring back to
To improve performance, matching circuit 150 may provide tunable impedance matching for power amplifier 140. The tunable impedance matching may be dynamically varied based on the impedance of load 260, the power delivered to load 260, and/or other parameters. These parameters may be determined by sensor 160 and computation unit 170.
where ω is the frequency of interest, in units of radian/second,
L is the inductance of inductor 310, and
ZP is the impedance of reactive element 312.
Series circuit 250a delivers an output current of ILOAD to load 260, which may be expressed as:
ILOAD=ILOAD
where ILOAD
φ is a phase that is dependent on the impedance of load 260, and
exp( ) denotes the natural exponent.
If the ZS impedance is inductive, then the ILOAD current would lag the VAMP voltage by 90° or π/2. Phase φ may be dependent on mismatch between matching circuit 150 and the load and may be close to 0 degrees with good matching.
Within sensor 160a, a programmable attenuator 316 receives the amplified RF signal and provides a first input signal. A programmable attenuator 318 receives the output RF signal and provides a second input signal. Programmable attenuators 316 and 318 may provide variable amounts of attenuation depending on the output power level in order to reduce the dynamic range of the input signals provided to the circuits within sensor 160a. A fixed-gain amplifier 320 receives the first input signal at an inverting input and the second input signal at a non-inverting input and provides a first sensed signal, VS1. The VS1 signal may be indicative of the voltage drop VIND across series circuit 250a and may be expressed as:
VS1≈VIND=ILOAD·ZS=ILOAD
A buffer (Buf) 322 receives the first input signal and provides a second sensed signal, VS2, which may be indicative of the VAMP signal. A phase shifter 324 receives and shifts the second sensed signal by 90° at the frequency of interest and provides a phase-shifted signal, VSHIFTED. The amplified RF signal and the phase-shifted signal may be expressed as:
VS2≈VAMP=VAMP
VSHIFTED≈VAMP
where VAMP
A multiplier 326 multiplies the phase-shifted signal from phase shifter 324 with the first sensed signal from amplifier 322 and provides a multiplier output, YMULT, which may be expressed as:
As shown in equation (6), the multiplier output includes a high frequency component at twice the frequency of interest and a low frequency component with the load-dependent phase φ. A lowpass filter 328 receives the multiplier output, filters out the high frequency component, and provides a sensor output, YOUT, which may be expressed as:
YOUT=VAMP
Within computation unit 170a, a unit 330 divides the sensor output by the magnitude of impedance ZS and provides the delivered power, POUT, which may be expressed as:
POUT=VAMP
In the exemplary design shown in
In another exemplary design not shown in
The magnitude of the series impedance, |ZS|, may be determined in various manners. In one design, |ZS| may be determined via computer simulation, empirical measurement, or by other means. In another design, |ZS| may be calibrated ahead of time. For example, the sensor output YOUT may be measured for a known output power, and |ZS| may be determined based on the known output power and the measured sensor output. |ZS| may also be determined in other manners.
The amplified RF signal from power amplifier 140 may be expressed as:
VAMP=VAMP
where VAMP
A voltage signal across series circuit 250 may be expressed as:
VIND=VIND
where VIND
θL is the phase of load 260.
A voltage signal across load 260 may be expressed as:
VLOAD=VLOAD
where VLOAD
An output current provided to load 260 may be expressed as:
ILOAD=ILOAD
where ILOAD
Within sensor 160b, a programmable (Prog.) attenuator 430 receives the amplified RF signal from power amplifier 140 and provides a first input signal. A programmable attenuator 440 receives the output RF signal at the load and provides a second input signal. A fixed-gain amplifier 432 receives the first input signal at an inverting input and the second input signal at a non-inverting input. Amplifier 432 provides a first sensed signal, VS1, which may be approximately equal to the VIND signal across series circuit 250. Amplifier 432 provides the first sensed signal to a first input of a switch 438 and also to a phase shifter 434. Phase shifter 434 shifts the first sensed signal by θP and provides a first phase-shifted signal to a limiter 436 and also to a third input of switch 438. θP may be zero degrees or some other value. Limiter 436 amplifies and clips the first phase-shifted signal and provides a first limited signal to a second input of switch 438. Switch 438 couples one of the three inputs to an output, which provides a first mixer input signal to a mixer 450.
A buffer 442 receives and buffers the second input signal and provides a second sensed signal, VS2, which may be approximately equal to the VLOAD signal at load 260. Buffer 442 provides the second sensed signal to a first input of a switch 448 and also to a phase shifter 444. Phase shifter 444 shifts the second sensed signal by θP and provides a second phase-shifted signal to a limiter 446. Limiter 446 amplifies and clips the second phase-shifted signal and provides a second limited signal to a second input of switch 448. Switch 448 couples one of the two inputs to an output, which provides a second mixer input signal to mixer 450. Mixer 450 mixes the first mixer input signal from switch 438 with the second mixer input signal from switch 448 provides a mixer output signal. A lowpass filter 452 filters the mixer output signal and provides a sensor output signal, VSENSE.
Multiple measurements may be made with switches 438 and 448 in different positions. Table 1 lists five switch configurations 1 through 5 for switches 438 and 448 and provides the sensor output for each switch configuration. In Table 1, the first column provides the switch configuration, the second column provides the input selected by switch 438, the third column provides the input selected by switch 448, the fourth column provides the sensor output with an arbitrary phase shift θP, and the fifth column provides the sensor output with a phase shift of zero, or θP=0. Sensor outputs VA through VE may be obtained for switch configurations 1 through 5, respectively.
Mixer 450 may operate as a multiplier when both input signals are not limited or as a downconverter when at least one input signal is limited. An input signal that is limited can act as a local oscillator (LO) signal that can switch a differential pair within mixer 450 to achieve downconversion. Since the limited input signal is used only for switching, the amplitude of the limited input signal is not reflected in the mixer output signal. Mixer 450 thus operates differently than multiplier 326 in
Computation unit 170 receives measurements from sensor 160b and computes various quantities of interest. As shown in Table 1, the phase of the load may be determined by selecting switch configuration 4 and obtaining measurement VD. The magnitude of the load impedance, |ZL|, may be determined based on measurements VA and VB with θP=0 and may be computed as follows:
The impedance ZS of series circuit 250 may be known or can be ascertained.
The load impedance ZL may be computed as follows:
ZL=|ZL|·[cos(θL)+j sin(θL)] , Eq (15)
where cos (θL) and sin (θL) may be determined based on measurement VD.
The peak output voltage VLOAD
The peak output current ILOAD
The power PL delivered to load 260 may be computed as follows:
Each quantity in the right hand side of equation (18) may be determined as described above.
Switch configuration 5 may be used as a root-mean-square (RMS) power detector. With θL=90°, measurement VE may be expressed as:
VE=VVLOAD
Other measurements may also be obtained with other switch configurations for sensor 160b in
The capacitance or reactance of capacitor 266 may be known or can be ascertained.
Within sensor 160c, a programmable attenuator 530 receives the VAMP signal and provides a first input signal. A programmable attenuator 540 receives the VLOAD signal and provides a second input signal. A fixed-gain amplifier 532 receives the first input signal at an inverting input and the second input signal at a non-inverting input and provides a first sensed signal, VS1, to a limiter 534 and also to a mixer 536. Limiter 534 amplifies and clips the first sensed signal and provides a first limited signal to a mixer 546. A buffer 542 receives and buffers the second input signal and provides a second sensed signal, VS2, to a limiter 544 and also to mixer 546. Limiter 544 amplifies and clips the second sensed signal and provides a second limited signal to mixer 536. Mixer 536 mixes the first sensed signal from amplifier 532 with the second limited signal from limiter 544 and provides a first mixer output signal. A lowpass filter 538 filters the first mixer output signal and provides a first sensor output signal, V1. Similarly, mixer 546 mixes the second sensed signal from buffer 542 with the first limited signal from limiter 534 and provides a second mixer output signal. A lowpass filter 548 filters the second mixer output signal and provides a second sensor output signal, V2. The V1 and V2 sensor outputs may be expressed as:
V1=VIND
V2=VLOAD
Computation unit 170 receives the V1 and V2 sensor outputs from sensor 160c for a first measurement with switch 268 opened and also for a second measurement with switch 268 closed. Computation unit 170 computes various quantities of interest based on the first and second measurements.
The magnitude of the load impedance |ZL1| may be determined based on measurements V1 and V2 with switch 268 opened. The magnitude of the load impedance |ZL2| may be determined based on measurements V1 and V2 with switch 268 closed. |ZL1| and |ZL2| may be computed as follows:
with V1 and V2 obtained with switch 268 opened, Eq (23)
with V1 and V2 obtained with switch 268 closed. Eq (24)
The following quantities may be defined:
The shunt reactance XL and the shunt resistance RL may be determined based on equations (25) and (26), as follows:
The load impedance ZL1 may be determined based XL and RL, as shown in equation (20). The phase of the load may be computed as follows:
where Re{ } denotes the real part and Im{ } denotes the imaginary part.
The peak output voltage VLOAD
The power delivered to load 260 may be computed as shown in equation (18). Other quantities may also be computed based on various measurements available from sensor 160c.
A buffer 542 receives and buffers the second input signal and provides a second sensed signal, VS2, to conditioning circuits 644 and 646 and also to mixer 672. Conditioning circuits 644 and 646 process the second sensed signal and provide their output signals to mixers 662 and 652, respectively. Mixer 652 mixes the first sensed signal from amplifier 532 with an output signal from circuit 646 and provides a first mixer output signal. A lowpass filter 654 filters the first mixer output signal and provides a first sensor output signal, VX. Mixer 662 mixes an output signal from circuit 636 with an output signal from circuit 644 and provides a second mixer output signal. A lowpass filter 664 filters the second mixer output signal and provides a second sensor output signal, VY. Mixer 672 mixes an output signal from circuit 634 with the second sensed signal from buffer 642 and provides a third mixer output signal. A lowpass filter 674 filters the third mixer output signal and provides a third sensor output signal, VZ.
Each conditioning circuit may comprise one of the following:
Multiple conditioning circuits may also share a circuit element. For example, conditioning circuits 634 and 636 may share a phase shifter or a limiter. Various exemplary designs may be obtained with conditioning circuits 634, 636, 644 and 646 implemented with different circuits.
In a first exemplary design, conditioning circuit 634 includes a limiter, conditioning circuit 636 includes a limiter and a phase shifter providing 90° phase shift, conditioning circuit 644 includes a wire, and conditioning circuit 646 includes a limiter and a phase shifter providing −90° phase shift. The VX, VY and VX signals may then be expressed as shown in Table 2 for the first design.
For the first exemplary design, the magnitude of the load impedance |ZL| may be determined based on measurements VX and VY as follows:
The phase of the load impedance may be computed as follows:
The load impedance ZL may be computed as shown in equation (15). The peak output voltage VLOAD
where sin(θL) and cos(θL) may be determined based on the load phase θL obtained from equation (32).
The peak output current ILOAD
The power delivered to load 260 may be computed as shown in equation (18). Other quantities may also be computed based on the measurements available from sensor 160d.
In a second exemplary design, conditioning circuit 634 includes a limiter and a phase shifter providing 90° phase shift, conditioning circuit 636 includes a wire, conditioning circuit 644 includes a limiter, and conditioning circuit 646 includes a limiter and a phase shifter providing −90° phase shift. The VX, VY and VX signals may be expressed as shown in Table 2 for the second design.
In a third exemplary design, conditioning circuit 634 includes a limiter and a phase shifter providing 90° phase shift, conditioning circuit 636 includes a limiter, conditioning circuit 644 includes a wire, and conditioning circuit 646 includes a limiter. The VX, VY and VX signals may be expressed as shown in Table 2 for the third design.
In a fourth exemplary design, conditioning circuit 634 includes a limiter, conditioning circuit 636 includes a phase shifter providing 90° phase shift, and conditioning circuits 644 and 646 share a limiter. The VX, VY and VX signals may be expressed as shown in Table 2 for the fourth design.
In a fifth exemplary design, conditioning circuits 634 and 636 share a limiter, and conditioning circuits 644 and 646 also share a limiter. The VX, VY and VX signals may be expressed as shown in Table 2 for the fifth design.
In a sixth exemplary design, conditioning circuits 634 and 636 share a limiter and a phase shifter providing 90° phase shift, conditioning circuit 644 includes a limiter, and conditioning circuit 646 includes a limiter and a phase shifter providing −90° phase shift. The VX, VY and VX signals may be expressed as shown in Table 2 for the sixth design.
Other exemplary designs may also be implemented with other circuits for conditioning circuits 634, 636, 644 and 646. For each exemplary design described above, various quantities such as the magnitude of the load impedance |ZL|, the phase of the load θL, the load impedance ZL, the peak output voltage VLOAD
In the exemplary design shown in
In the exemplary designs shown in
The magnitude of the input impedance, |ZIN|, may be determined based on measurements VA and VB with θP=0 and may be computed as follows:
The input impedance ZIN may be computed as follows:
ZIN=|ZIN|·[cos(θIN)+j sin(θIN)], Eq (36)
where cos(θIN) and sin(θIN) may be determined based on measurement VD.
The peak amplified voltage VAMP PK may be determined based on measurements VB and VD and may be computed as follows:
The peak output current ILOAD
The power delivered by power amplifier 140 may be computed as follows:
Each quantity in the right hand side of equation (39) may be determined as described above.
The input impedance ZIN1 with switch 278 opened and the input impedance ZIN2 with switch 278 closed may be expressed as:
ZIN1=RLS+j(XS+XLS)=RLS+j XIN, and Eq (40)
ZIN2=RLS+j(XS+XLS+XCEQ)=RLS+j(XIN+XCEQ), Eq (41)
where XIN=XS+XLS, and Eq (42)
Sensor 160f includes all circuit components in sensor 160c in
V1=VIND
V2=VAMP
The magnitude of input impedance |ZIN1| may be determined based on measurements V1 and V2 with switch 278 opened. The magnitude of load impedance |ZIN2| may be determined based on measurements V1 and V2 with switch 278 closed. |ZIN1| and |ZIN2| may be computed as follows:
with V1 and V2 obtained with switch 278 opened, Eq (46)
with V1 and V2 obtained with switch 278 closed. Eq (47)
The following quantities may be defined:
|ZIN1|2=RLS2+XIN2, and Eq (48)
|ZIN2|2=RLS2+(XIN+XCEQ)2. Eq (49)
The input reactance XIN and the load impedance ZL may be determined as follows:
The power delivered by power amplifier 140 may be computed as follows:
The VX, XY and XZ sensor outputs are dependent on the circuits used for conditioning circuits 634, 636, 644 and 646. For the first exemplary design described above, conditioning circuit 634 includes a limiter, conditioning circuit 636 includes a limiter and a phase shifter providing 90° phase shift, conditioning circuit 644 includes a wire, and conditioning circuit 646 includes a limiter and a phase shifter providing −90° phase shift. The VX, VY and VX sensor outputs may then be expressed as:
VX=VIND
VY=VAMP
VZ=VAMP
The magnitude of the input impedance |ZIN| may be determined based on measurements VX and VY as follows:
The phase of the input impedance may be computed as follows:
The input impedance ZIN may be computed as shown in equation (36). The peak amplified voltage VAMP
where sin(θIN) and cos(θIN) may be determined based on the input phase θIN obtained from equation (59).
The peak amplified current ILOAD
The power delivered by power amplifier 140 may be computed as shown in equation (54). Other quantities may also be computed based on the measurements available from sensor 160g.
Other exemplary designs may also be implemented with other circuits for conditioning circuits 634, 636, 644 and 646, as described above for
Sensors 160a through 160g are thus different from other sensors that measure quantities in polar coordinate, which defines a complex value by a peak value and a phase. This is in contrast to sensors 160a through 160g, which provide quantities in Cartesian coordinate using inphase and quadrature components. Sensor 160 may also be implemented in other manners.
A shunt capacitor 1022 is coupled between node B and circuit ground and is a fixed capacitor that is always selected. M switchable capacitors 1024a through 1024m are coupled in series with M switches 1026a through 1026m, respectively, where M may be any integer value. The M series combinations of capacitor 1024 and switch 1026 are coupled between node B and circuit ground. Each switchable capacitor 1024 may be selected or deselected via the associated switch 1026.
For geometric weighting, capacitors 1014a through 1014n may have progressively greater capacitance (e.g., by a factor of two for binary weighting), and capacitors 1024a through 1024m may also have progressively greater capacitance. For thermometer decoding, capacitors 1014a through 1014n may have the same capacitance, and capacitors 1024a through 1024m may also have the same capacitance. For both types of weighting, capacitors 1014 may be designed to provide the desired range of capacitance for the series path, and capacitors 1024 may be designed to provide the desired range of capacitance for the shunt path. Capacitors 1012 and 1014 provide a variable capacitance of CVAR1. Capacitors 1022 and 1024 provide a variable capacitance of CVAR2. Different impedance matching settings may be obtained with different combination of values for CVAR1 and CVAR2.
In general, any number of fixed and switchable capacitors may be used for the series path and also for the shunt path. Furthermore, each fixed or switchable capacitor may have any suitable value. Different impedance matching settings may be obtained with different combinations of switchable capacitors being selected. For example, eight different impedance matching settings ranging from C to 8C may be obtained with eight different switching states for three switchable capacitors 1014 with binary weighting.
Switches 1016 and 1026 may be implemented with metal oxide semiconductor (MOS) transistors or some other semiconductor devices. Multiple MOS transistors may be stacked together for each switch, so that only a fraction of the signal swing appears across each MOS transistor, which may improve reliability.
Inductor 1010 and capacitors 1012 and 1014 may be part of series circuit 250 in
Capacitors 1012 and 1014 provide a variable capacitance of CVAR1. Capacitors 1022 and 1024 provide a variable capacitance of CVAR2. Capacitors 1032 and 1034 provide a variable capacitance of CVAR3. Capacitors 1042 and 1044 provide a variable capacitance of CVAR4. Different impedance matching settings may be obtained with different combinations of values for CVAR1, CVAR2, CVAR3 and CVAR4. Two stages may provide more degree of freedom to tune the impedance matching.
In one design, the voltage at node B may be sensed by sensor 160, e.g., provided to buffer 442, 542 or 642 in
Capacitor 1052 provides AC coupling. Switch 1058 may be selected/closed to provide a smaller attenuated input signal, and switch 1056 may be selected/closed to provide a larger attenuated input signal. More than two signal levels may also be obtained with (i) more resistors coupled in series and between node E and circuit ground and (ii) more switches coupled to these resistors to select one of the signals at the resistors.
Capacitor 1072 provides AC coupling and forms the top part of a capacitive divider. Capacitors 1074 and 1076 form the bottom part of the capacitive divider. Different divider ratios, and hence different signal levels for the attenuated input signal, may be obtained by selecting different combinations of capacitors 1076a through 1076k.
A second power amplifier 140b amplifies a second input RF signal, VIN2, and provides a second amplified RF signal, VAMP2. A tunable matching circuit 150b is coupled to the output of power amplifier 140b, performs output impedance matching and filtering for power amplifier 140b, and provides a second output RF signal, VOUT2, to a switch 152b. Switch 152b provides the VOUT2 signal to either a duplexer 154b or tunable matching circuit 150c. Duplexer 154b routes the VOUT2 signal to a second input of antenna switch 156 and also routes a received RF signal from antenna switch 156 to a receiver for band 2 (not shown in
Transmitter 122 may support a number of modes. In a first mode, power amplifier 140a may be enabled, and power amplifier 140b may be disabled. The VIN1 signal may be amplified by power amplifier 140a and routed through tunable matching circuit 150a, switch 152a, duplexer 154a, and switch 156 to antenna 158. In a second mode, power amplifier 140b may be enabled, and power amplifier 140a may be disabled. The VIN2 signal may be amplified by power amplifier 140b and routed through tunable matching circuit 150b, switch 152b, duplexer 154b, and switch 156 to antenna 158. In a third mode, power amplifiers 140a and 140b may both be enabled. A common input RF signal may be amplified to obtain the VIN1 and VIN2 signals, which may be amplified by power amplifiers 140a and 140b and routed through tunable matching circuits 150a and 150b, and combined by tunable matching circuit 150c. The VOUT3 signal from tunable matching circuit 150c may be routed through switch 156 to antenna 158. The first mode may support Code Division Multiple Access (CDMA) 1× and/or Wideband CDMA (WCDMA) for the first band, e.g., cellular band or PCS band. The second mode may support CDMA 1× and/or WCDMA for the second band, e.g., GSM 900 or IMT-2000 band. The third mode may support Global System for Mobile Communications (GSM) for both bands.
Switches 162a and 162b may couple the outputs of power amplifiers 140a and 140b, respectively, to a first input of measurement circuit 172. Switches 164a and 164b may couple the outputs of tunable matching circuits 150a and 150b, respectively, to a second input of measurement circuit 172. Measurement circuit 172 may make various measurements that may be used to determine the load impedance, the output power, and/or other parameters at the output of tunable matching circuit 150a when switches 162a and 164a are closed and switches 162b and 164b are opened. Measurement circuit 172 may make various measurements that may be used to determine the load impedance, the output power, and/or other parameters at the output of tunable matching circuit 150b when switches 162a and 164a are opened and switches 162b and 164b are closed. The load impedance, the output power, and/or other parameters may be used to generate Controls 1, 2 and 3 to adjust tunable matching circuits 150a, 150b and 150c, respectively.
Transmitters 122 and 124 may operate in low band (e.g., below 1 gigahertz (GHz)) or high band (e.g., near 2 GHz). A transmitter may support operation in both low band and high band. The transmitter may include a first set of power amplifiers, tunable matching circuits, switches, and duplexers for low band and a second set of power amplifiers, tunable matching circuits, switches, and duplexers for high band. An antenna switch may couple to the duplexers and tunable matching circuits for both low band and high band. The output of the antenna switch may be coupled to the antenna or to tunable matching circuit 150d. A pair of switches 162 and 164 may couple each transmit signal path to measurement circuit 172, e.g., as shown in
In general, a transmitter may include any number of power amplifiers and any number of tunable matching circuits. The power amplifiers may have the same or different gains and the same or different maximum output power levels. The transmitter may also support any number of modes and any number of bands. Measurement circuit 172 may make measurements at any point within the transmitter. The measurements may be used to determine the load impedance, the output power, and/or other parameters that may be used to adjust one or more tunable matching circuits.
Adaptive load matching to dynamically adjust a tunable matching circuit may be achieved in various manners. In one exemplary design, the load impedance ZL may be measured, e.g., with sensor 160b in
In another exemplary design, adaptive load matching may be performed as follows. The power PL delivered to the load and the load impedance ZL may be measured as described above. A reflection coefficient ρ may be computed based on the load impedance, as follows:
where ZO may be 50 Ohms or some other value.
A voltage standing wave ratio (VSWR) may be computed based on the reflection coefficient, as follows:
VSWR is a ratio of the maximum voltage to the minimum voltage of a signal. VSWR may be used to protect power amplifier 140 from excessively large output voltage.
The load power may be referred to as radiated power and may be expressed as:
PL=PRADIATED=PINCIDENT−PREFLECTED, Eq (64)
where PRADIATED is the power radiated by antenna 158,
PINCIDENT is the power provided by power amplifier 140, and
PREFLECTED is the reflected power due to mismatch at the load.
The incident power, the radiated power, and the reflected power may be expressed as:
PINCIDENT=PRADIATED+PREFLECTED, Eq (65)
PRADIATED=(1−|ρ|2)·PINCIDENT, and Eq (66)
PREFLECTED=|ρ|2·PINCIDENT. Eq (67)
A mismatch loss may be computed as follows:
Mismatch loss=10·log10(1−ρ2). Eq (68)
In an exemplary design, an apparatus may comprise a sensor and a computation unit, e.g., as shown in
In an exemplary design, the sensor may include first and second programmable attenuators, an amplifier, a buffer, a phase shifter, a multiplier, and a lowpass filter, e.g., as shown in
The apparatus may further include a tunable matching circuit coupled to the power amplifier. The tunable matching circuit may comprise the series circuit and may be adjusted based on the power delivered to the load.
In another exemplary design, an apparatus may comprise a sensor and a computation unit, e.g., as shown in any of
In an exemplary design, the second end of the series circuit may be coupled to the load, e.g., as shown in
In an exemplary design, the first version of the first sensed signal may be the first sensed signal, and the second version of the second sensed signal may be the second sensed signal. The second version of the first sensed signal may be a limited version, or a phase shifted version, or a limited and phase shifted version of the first sensed signal. The first version of the second sensed signal may be a limited version, or a phase shifted version, or a limited and phase shifted version of the second sensed signal. The various versions of the first and second sensed signals may be obtained with limiters, phase shifters, etc. The computation unit may determine the impedance and/or the delivered power in different manners (e.g., based on different equations and/or measurements) depending on how the different versions of the first and second sensed signals are defined.
In an exemplary design, the first sensor output may be indicative of inphase or quadrature component of the first voltage signal. The second sensor output may be indicative of inphase or quadrature component of the second voltage signal. The first or second sensor output may also be indicative of the phase of the impedance.
In an exemplary design, the sensor may include first and second programmable attenuators, an amplifier, and a buffer. The first programmable attenuator may be coupled to the first end of the series circuit and may provide a first input signal. The second programmable attenuator may be coupled to the second end of the series circuit and may provide a second input signal. The amplifier may receive the first and second input signals and provide the first sensed signal. The buffer may receive the second input signal and provide the second sensed signal.
In an exemplary design, the sensor may further include first and second switches, a mixer, and a lowpass filter, e.g., as shown in
In another exemplary design, the sensor may further include first and second mixers and first and second lowpass filters, e.g., as shown in
In another exemplary design, the sensor may further include a third mixer and a third lowpass filter, e.g., as shown in
In an exemplary design, the load may comprise a reactive element coupled in series with a switch and to the second end of the series circuit, e.g., as shown in
The apparatus may further include a power amplifier coupled to a tunable matching circuit. The tunable matching circuit may comprise the series circuit and may be adjusted based on the impedance and/or the delivered power.
In another exemplary design, a wireless device may include a first power amplifier (e.g., power amplifier 140a in
The wireless device may further include a second power amplifier (e.g., power amplifier 140b) and a second tunable matching circuit (e.g., tunable matching circuit 150b). The second power amplifier may amplify a second input RF signal and provide a second amplified RF signal. The second tunable matching circuit may provide output impedance matching and filtering for the second power amplifier, may receive the second amplified RF signal, and may provide a second output RF signal. The measurement circuit may further measure second impedance and/or delivered power at the output of the second tunable matching circuit, which may be adjusted based on the measured second impedance or delivered power. The wireless device may further include a third tunable matching circuit (e.g., tunable matching circuit 150c) coupled to the first and second tunable matching circuits. The third tunable matching circuit may receive and combine the first and second amplified RF signals and provide a third output RF signal. The measurement circuit further may measure third impedance and/or delivered power at the output of the third tunable matching circuit, which may be adjusted based on the measured third impedance or delivered power.
The power and impedance measurement circuits described herein may enable adaptive load matching for a power amplifier and may provide various advantages, such as:
Power and/or impedance measurements may be used to adjust a tunable matching circuit, as described above. The power and/or impedance measurements may also be used for other purposes. For example, the power measurements may be used to adjust the transmit power of a wireless device for power control, to sense overload conditions and reduce the gain and/or transmit power of the power amplifier, etc.
The power and impedance measurement circuits described herein may be used for a transmitter in a wireless device, as described above. The power and impedance measurement circuits may also be used in other electronics devices to measure power and/or impedance. In
The power and impedance measurement circuits described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronics device, etc. The measurement circuits may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.
An apparatus implementing the measurement circuits described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The present Application for Patent claims priority to Provisional U.S. Application Ser. No. 61/218,836, entitled “POWER AND/OR IMPEDANCE MEASUREMENT CIRCUITS FOR A WIRELESS COMMUNICATION DEVICE,” filed Jun. 19, 2009 assigned to the assignee hereof, and expressly incorporated herein by reference.
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