BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram schematically showing the architecture of the compiler system according to the present invention.
FIG. 2 is a flowchart of the power-aware compiling method according to the present invention.
FIG. 3 is a diagram showing that the power-aware compiling method of the present invention is expressed by pseudo codes.
FIG. 4 is a diagram showing one embodiment of the present invention, wherein a portion of the program codes is processed with the power-aware compiling method of the present invention.
FIG. 5 to FIG. 7 are diagrams showing the power consumptions in executing various instructions when the original program codes and the rescheduled and optimized program codes output by the power-aware compiling method of the present invention are respectively tested with the standard benchmarks, including: the SPEC2000, the Mediabench and the Dspstone.
FIG. 8 to FIG. 10 are diagrams showing the performances of executing various instructions when the original program codes and the rescheduled and optimized program codes output by the power-aware compiling method of the present invention are respectively tested with the standard benchmarks, including: the SPEC2000, the Mediabench and the Dspstone.
DETAILED DESCRIPTION OF THE INVENTION
The present invention is to provide a power-aware compiling method, which achieves the powerawareness of a compiled application program via rescheduling the program codes of the application program and modifying the voltage used therein.
Refer to FIG. 1 a diagram showing the architecture of the compiler system according to the present invention. As shown in FIG. 1, the method of the present invention is simulated in a SUIF2 compiler system. Firstly, an application program 10, such the program codes written with C language, is provided. Next, the application program 10 enters into a compiler 20, and then, a low power pass process is undertaken. The first portion of the low power pass process is undertaken in a SUIF2 system 22 and includes: the optimization procedure of the SUIF2 system 22, the high-level SUIF procedure and the low-level SUIF procedure, which are used to undertake the analyses of the internal procedures of the application program 10, such as the global alias analysis, the specialization analysis and the data flow chart analysis.
The second portion of the low power pass process is undertaken in a machine SUIF system 24. Refer to FIG. 2 a flowchart showing the steps of the second portion of the low power pass process. Firstly, the machine SUIF system 24 analyzes a functional-unit database and an optimization interface to establish the control flow graph and the data flow graph of the application program 10 (Step S10). Next, an optimization procedure is undertaken; the control flow graph and the data flow graph are analyzed to establish the power model of the application program 10; the control flow graph is divided into a plurality of basic blocks B (blocks) according to the usage of the functional units, and each basic block is composed of a plurality of regions R, and each region includes at least one functional unit; the functional unit may be an adder or multiplier for integer operation and floating point operation (Step S12). Next, each functional unit is assigned a power mode according to the power model; as the functional units will not be executed synchronically, the idle function units are turned off (Step S14). Next, a judgment is performed to determine whether the same functional units among the idle functional units are dependent (Step S16). Next, two basic blocks with the same idle functional units are merged into a new basic block if none dependency exists between the same idle functional units, and an appropriate power mode is assigned to the new basic block (Step S18). Next, the basic blocks with the same power modes are merged together (Step S20). Then, the steps from Step S16 to Step S20 are repeated until no further merging can be performed.
After the rescheduling process of the application program 10 is completed, the rescheduled and optimized application program is compiled with a system program 26. The system program may be an Alpha simulation program and can perform a cross compilation under the Alpha Linux system. The compiled application program is linked to a run-time library to execute the application program and generate the codes executable in a simulator 30. The simulator 30 may be a Wattch simulator, which can perform a loop-type simulation to determine the power consumption of a CPU under different parameters and the power models under different infrastructures.
Refer to FIG. 3 for the rescheduling method for the program codes, which is written in pseudo codes, wherein N(B) is the execution count of one basic block B; FU(B) is the functional unit executed in one basic block B; FU(R) is the functional unit executed in one region R; fmem is the memory-accessing rate of all the instructions of one basic block B; Tper(R) is the proportion of the execution time of one basic block B; f(B) is the power model of one basic block B; and f(R) is the power model of one region R. The application program is divided into a plurality of regions. If FU(Ri)=FU(Rj) and D(Ri, Rj)=ø, regions Ri and Rj are merged into a new region, wherein FU(Ri)=FU(Rj) denotes that the regions Ri and Rj use the same functional units, and D(Ri, Rj)=ø denotes that those two regions are independent. There are three parameters γ, α and β in the pseudo codes, wherein γ is the threshold value to turn on/off one functional unit; α and β are the threshold values to assign a power mode to one region. The value of Tper(R) determines whether to turn off the functional unit in one region R.
In the normal mode of the Wattch simulator used in the present invention, the voltage is 1.5V, and the clock frequency is 600 MHz; in the low-voltage mode fdown, the voltage is 0.3V, and the clock frequency is 300 MHz. In the pseudo codes shown in FIG. 3, two steps thereof involve the decision of the power mode. In the first one, according to α value, each region R is assigned a power mode; then, a judgment is performed to determine whether f(Ri)=f(Rj) and D(Ri, Rj)=ø; if the result is yes, regions Ri and Rj are merged into a new region; and the abovementioned steps will be repeated until no further merging can be performed. In the second one, each basic block B is assigned a power mode according to β value.
Below, the embodiment shown in FIG. 4 is to exemplify the power-aware compiling method of the present invention. In this embodiment, there are two “for” loops and two “temp” expressions. As those two loops use the same function units but are independent, and as those two expressions use the same functional units but are independent, those two loops and those two expressions are respectively merged into two regions. Next, the multiplier in the loop region is turned off, and the adder in the expression region is also turned off. Then, the region including two loops is set to operate in the low-voltage mode, and the region including two expressions is set to operate in the normal mode. Via comparing the original program codes with the rescheduled and optimized program codes, it is observed: in the latter one, the adder and the multiplier are respectively merged to two different regions. As the adder will be repeatedly executed many times in the loop, the power mode is set to be the low-voltage mode. In executing the loop, as the multiplier is idle, it is turned off. In executing the expression, as the adder is idle, it is turned off. Therefore, the rescheduled and optimized program codes are more power-efficient than the original program codes.
Refer to from FIG. 5 to FIG. 7 diagrams showing the power consumptions in executing various instructions when the original program codes and the rescheduled and optimized program codes output by the power-aware compiling method of the present invention are respectively tested with the standard benchmarks, including: the SPEC2000, the Mediabench and the Dspstone. As shown in FIG. 5, the power consumption by the matrix instruction of the original program codes is more 2 times that of the rescheduled and optimized program codes. In fact, except the irr_biquad_one_section instruction, all the other instructions after the rescheduling and optimization are more power-efficient than those before the rescheduling and optimization. Similarly, in the tests with the Mediabench and the Dspstone, the power-aware efficacy of the present invention can also be obviously observed. Refer to from FIG. 8 to FIG. 10 diagrams showing the performances of executing various instructions when the original program codes and the rescheduled and optimized program codes output by the power-aware compiling method of the present invention are respectively tested with the standard benchmarks, including: the SPEC2000, the Mediabench and the Dspstone. As the change in the lengths of the program codes before and after the rescheduling and optimization by the method of the present invention is small, the change in the performances of them is not obvious.
In summary, the present invention proposes a power-aware compiling method, wherein the switching activities of functional units and the transitions between different power modes are decreased via merging identical but independent idle functional units of different basic blocks into a new basic block, and thereby, the power consumption can be reduced; via the verifications by the SPEC2000, the Mediabench and the Dspstone, it is proved that the present invention can averagely save the power consumption by 26% without obvious performance degradation under the background of the DVS (Dynamic Voltage Scaling) technology.
Those described above are only preferred embodiments to clarify the present invention; however, it is not intended to limit the scope of the present invention. Any equivalent modification and variation according to the spirit of the present invention is to be also included within the scope of the claims of the present invention.
Patent Application
20070300214
