Patent Application
20190042331
Portions of the disclosure of this patent document may contain material that is subject to copyright protection. The copyright owner has no objection to the reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The copyright notice applies to all data as described below, and in the accompanying drawings hereto, as well as to any software described below: Copyright © 2018, Intel Corporation, All Rights Reserved.
Packet processing applications typically provision a number of “worker” processing threads running on processor cores (called “worker cores”) to perform the processing work of the applications. Worker cores consume packets from dedicated queues which in some scenarios is fed by one or more network interface controllers (NICs) or by input/output (I/O) threads. The number of worker cores provisioned is usually a function of the maximum predicted throughput. However, real packet traffic varies widely both in short durations (e.g., seconds) and over longer periods of time (for example, many networks experience significantly less traffic at night or on a weekend).
This gives rise to opportunities for efficiency. Power savings can be obtained if some worker cores can be put in a low power state when the traffic load allows. Alternatively, worker cores that are not required can be redirected to other tasks (e.g., used in other execution contexts) and only recalled when required. Some existing approaches allow applications to be temporarily dropped to a lower power state or use a wait semantic to sleep on the next queue entry. Context switching between the work context and some background context is also possible using interrupt schemes. These techniques can be applied irrespective of the entity that is writing to the queue.
However, it is problematic to vary the number of worker cores. Lookup tables have to be modified and some packets inflight at the time of the change may be lost or go out of order as a result. Packet distribution schemes assume all worker cores are always available which has drawbacks. Worker cores can transition to a low power state when they have no work available, but the time spent transitioning to/from the low power state (or another execution context) can be significant, especially for deeper power states. Cores that transition too frequently risk spending too many cycles on the transition itself, and are therefore not efficient. Schemes that allow all processing cores to transition are more likely to be susceptible to this problem. Latency is incurred for packets that have to wait for a core to wake or switch context. With waiting schemes, it is difficult for processing cores to guarantee low power state residency (since the next packet may wake the core) and intermittent traffic may cause a core to spend its time bouncing in and out of low power states. CPUs that support multiple concurrently operating (hyper)threads complicate issues further. To save significant power, it is usually necessary to have all sibling hyper-threads in a core in a low power state. Without the ability to vary the number of worker cores it is difficult to maximize the likelihood of this occurring. This disadvantage becomes more significant as the number of hyper-threads per core increases.
Embodiments of the present invention provide an approach for power aware load balancing (PALB) of processing cores. This approach leverages a load balancing capability of a hardware queue manager (HQM) to efficiently and dynamically scale the number of enabled worker cores in a computing platform to match a varying workload in an efficient manner while maintaining performance (e.g., throughput, latency) requirements. As well as being power efficient, embodiments can be used in deploying “cloudified” applications in data center systems that can scale up and down in size.
Embodiments of the present invention leverage a load balancing capability of the HQM to dynamically scale the number of enabled worker cores used to process a time variant workload to improve efficiency while maintaining performance (e.g., throughput, latency) requirements. A worker thread is a consumer from the HQM and work is distributed evenly amongst the worker threads on the worker cores. Activity is monitored by a process which dynamically adjusts the number of enabled worker cores in response to changes in the traffic level or based at least in part on external factors and/or conditions. Worker cores that are not in use enter sleep states for overall power reduction, or they context switch to other tasks.
In embodiments of the present invention, worker cores that have been removed from the pool of enabled worker cores do not repeatedly transition between wake and sleep states. Short bursts of high level traffic are buffered in the HQM without necessarily causing new worker cores to be activated. Thus, unused worker cores can enter deep sleep states and save considerable power without causing an impact to system packet latency. Embodiments can be tailored to add/remove sibling hyper-threads simultaneously on multithreaded systems to improve power savings.
Embodiments of the present invention can provide an increase in a low power state sleep occupation time (depending on state transition time) compared to previous approaches. This corresponds to an equivalent saving of active power for the worker cores. Embodiments also demonstrate better deterministic (e.g., lower maximum) latency than other approaches. Embodiments also provide better efficiency and latency when context switching via interrupts.
Although the description contained herein references worker cores, embodiments of the present invention are also applicable to worker threads running on worker cores. That is, worker threads can also be activated and deactivated dynamically according to embodiments of the present invention.
According to some examples, computing platform 101, as shown in
In some examples, computing platform 101, includes but is not limited to a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, a laptop computer, a tablet computer, a smartphone, or a combination thereof. In one example, computing platform 101 is a disaggregated server. A disaggregated server is a server that breaks up components and resources into subsystems. Disaggregated servers can be adapted to changing storage or compute loads as needed without replacing or disrupting an entire server for an extended period of time. A server could, for example, be broken into modular compute, I/O, power and storage modules that can be shared among other nearby servers.
Circuitry 120 having processing cores 122-1 to 122-m may include various commercially available processors, including without limitation Intel® Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon® or Xeon Phi® processors, ARM processors, and similar processors. Circuitry 120 may include at least one cache 135 to store data.
Uncore 182 describe functions of a processor that are not in processing cores 122-1, 122-2, . . . 122-m, but which are closely connected to the cores to achieve high performance. Cores contain components of the processor involved in executing instructions, including the arithmetic logic unit (ALU), the floating-point unit (FPU) and level one and level two caches. In contrast, in various embodiments, uncore 182 functions include interconnect controllers, a level three cache, a snoop agent pipeline, an on-die memory controller, and one or more I/O controllers. In an embodiment, uncore 182 is resident in circuitry 120. In an embodiment, uncore 182 includes last level cache 135.
According to some examples, primary memory 130 may be composed of one or more memory devices or dies which may include various types of volatile and/or non-volatile memory. Volatile types of memory may include, but are not limited to, dynamic random-access memory (DRAM), static random-access memory (SRAM), thyristor RAM (TRAM) or zero-capacitor RAM (ZRAM). Non-volatile types of memory may include byte or block addressable types of non-volatile memory having a 3-dimensional (3-D) cross-point memory structure that includes chalcogenide phase change material (e.g., chalcogenide glass) hereinafter referred to as “3-D cross-point memory”. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magneto-resistive random-access memory (MRAM) that incorporates memristor technology, spin transfer torque MRAM (STT-MRAM), or a combination of any of the above. In another embodiment, primary memory 130 may include one or more hard disk drives within and/or accessible by computing platform 101.
Computing platform 101 includes hardware queue manager (HQM) 180 to assist in managing queues of data units. In an embodiment, the data units are packets transmitted to and/or received from network I/O device 110, and packets transferred between cores. In another embodiment, the data units include timer events. In an embodiment, HQM 180 is part of circuitry 120. In another embodiment, HQM 180 is part of uncore 182.
In an embodiment, uncore 182 includes a plurality of consumer queues CQ 1204, CQ 2206, . . . CQ N 208, where N is a natural number, stored in cache 135. Each consumer queue stores zero or more blocks of metadatas. In an embodiment, a block of metadata is a packet descriptor including information describing a packet. In one embodiment, there is a one to one correspondence between each worker core and a consumer queue. For example, worker core 1210 is associated with CQ 1204, worker core 2212 is associated with CQ 2206, and so on until worker core N 214 is associated with CQ N 208. However, in other embodiments there may be a plurality of consumer queues per worker core. In yet another embodiment, at least one of the worker cores is not associated with a consumer queue. The sizes of the consumer queues may all be the same or may be different in various embodiments. The sizes of the consumer queues are implementation dependent. In at least one embodiment, the consumer queues store metadata describing packets, but not the packets themselves (since the packets are stored in one or more of primary memory 130, cache 135, and storage devices 165 while being processed after receipt from network I/O device 110).
HQM 180 distributes packet processing tasks to enabled worker cores 210, 212, . . . 214 by adding packet descriptors to consumer queues CQ 1204, CQ 2206, . . . CQ N 208 in uncore 182. HQM 180 acts as a traffic buffer smoothing out spikes in traffic flow. HQM 180 performs load balancing while considering flow affinity. Disabled worker cores are not allocated any traffic when disabled and can enter low power states semi-statically, or be switched to other duties.
In an embodiment, processing proceeds as follows. DSI core 216 enqueues packet descriptors to HQM 180 via uncore 182. HQM 180 distributes (i.e., load balances) packet descriptors to active consumer queues CQ1204, CQ 2206, . . . CQ N 208 in uncore 182. Worker cores 210, 211, . . . 214 get packet descriptors from corresponding consumer queues for packet processing. Worker cores with nothing to do (i.e., there are no packet descriptors in their consumer queues to be processed), go to sleep.
In an embodiment, a control flow proceeds as follows. Within a predetermined interval DSI core 216 counts a number of received packets injected into computing platform 101. In an embodiment, a system of credit is used manage load balancing. Worker cores return credits back to DSI core 216 periodically so DSI core 216 knows both a packet injection rate and a packet consumption rate of the system. A process executing in DSI core 216 computes a required number of enabled worker cores needed to balance power savings and system performance. DSI core 216 sends updated worker core status information to HQM 180. To stop using a worker core, HQM 180 stops inserting packet descriptors into the worker core's consumer queue. To start using a worker core, HQM 180 starts inserting packet descriptors into the worker core's consumer queue. In the context switch case, HQM 180 delivers an interrupt to bring the worker core back to work.
The power aware load balancing approach of embodiments of the present invention rely on a capability of HQM 180 to allow the number of worker cores to be modified transparently to application 160. This capability can be applied at a physical core level such that sibling threads on any given worker core are likely to have a high correlation of sleep state residency.
At block 704, DSI core 216 instructs HQM 180 to adjust the number of active consumer queues in response to the newly computed number of required enabled worker cores. In an embodiment, HQM 180 adjusts the set of active consumer queues by feeding or starving consumer queues in sufficient number to match the newly computed number of required enabled worker cores. Thus, if the number of required enabled worker cores has gone down from the previous computation by a number of cores (for example, there were ten enabled worker cores, but now only eight enabled worker cores are needed), HQM 180 stops adding packet descriptors to consumer queues 204, 206, . . . 208 for the same number of cores (for example, two consumer queues are no longer being fed). If the number of required enabled worker cores has gone up from the previous computation by a number of cores (for example, there were eight enabled worker cores, but now ten enabled worker cores are needed), HQM 180 starts adding packet descriptors to consumer queues 204, 206, . . . 208 for the same number of cores (for example, two additional consumer queues are no longer being starved and instead are now being fed).
At block 706, each worker queue independently polls the worker core's associated consumer queue (or consumer queues, if a worker core is associated with multiple consumer queues). If the consumer queue is not empty at block 708, the worker core gets and processes the next packet descriptor (i.e., a new packet descriptor) in the consumer queue. Processing loops back to block 708. If the consumer queue is empty at block 708, the worker core enters a low power state at block 712 to pend on a next available (e.g., new) consumer queue entry. That is, the worker core will not process any more packet descriptors until a next available packet descriptor is added to the worker core's consumer queue by HQM 180. In an embodiment, the worker core enters a low power state by executing a MWAIT instruction. In an embodiment, instead of entering a low power state, the worker core is switched to tasks other than processing packet descriptors from the worker core's consumer queue, and sets up an interrupt to trigger on an addition of a new packet descriptor to the worker core's consumer queue. Note that consumer queues can be empty even when they are activated, so in these embodiments the worker core can sleep (or switch) even when enabled. Regardless, the next write to the worker core's consumer queue brings the worker core back to the task of processing packet descriptors. When the worker core is in a low power state, computing platform 101 uses less power. Processing loops back to block 708.
At block 806, each worker queue independently polls the worker core's associated consumer queue (or consumer queues, if a worker core is associated with multiple consumer queues), regardless of enable/disable status. If at block 808 the consumer queue is empty and the worker core's disable flag is set, the worker core enters a low power state at block 812 to pend on a next available (i.e. new packet descriptor) consumer queue entry. That is, the worker core will not process any more packet descriptors until a next available packet descriptor is added to the worker core's consumer queue by HQM 180. In an embodiment, the worker core enters a low power state by executing a MWAIT instruction. In an embodiment, instead of entering a low power state, the worker core is switched to tasks other than processing packet descriptors from the worker core's consumer queue, and sets up an interrupt to trigger on an addition of a new packet descriptor to the worker core's consumer queue. When the worker core is in a low power state, computing platform 101 uses less power. Processing loops back to block 808. If at block 808 the consumer queue is not empty or the consumer queue is empty but the worker core's disable flag is not set (i.e., the worker core is still enabled), then the worker core gets and processes the next packet descriptor (if there is one) in the consumer queue at block 810. Processing loops back to block 708. In this embodiment, implementation of the disable flag for each worker core results in worker cores polling so long as they (and their associated consumer queues) are enabled, regardless of whether the worker core's consumer queue is empty. This prevents worker cores from bouncing in and out of low power states due to temporary empty consumer queues.
In an embodiment, the process for adjusting the number of enabled worker cores is dynamic and transparent to application 160. The process compares the injected packet rate with the packet consumption rate. If the system processes packets at a slower rate than the packet inject rate, additional worker cores are enabled to boost the packet consumption rate and vice versa.
An example of pseudo code of a process for adjusting the number of active worker cores is shown below. Other implementations within the scope of embodiments of the present invention can be designed.
The parameters can be adjusted to trade off latency for power efficiency according to system requirements. In the example pseudo code, the variable “pkts” determines the frequency of adjusting the number of enabled worker cores, balancing response time (maximum latency) and efficiency. In an embodiment, latency is defined as the time from when a packet enters the system until the packet is finished processing by a worker core. Maximum, average, and minimum latencies can be determined. [o066] For applications with varying traffic loads, embodiments of the present invention provide better power savings (e.g., a higher percentage of worker cores in a lower power state) than a static distribution approach.
Variations to the power aware load balancing approach of embodiments of the present invention may be used. In one embodiment, a time of day (TOD) process could be applied, whereby the maximum number of enabled worker cores is adjusted every hour (for example) based on expected traffic and some of the worker cores are transitioned in and out of deep sleep states (or to other activities). Worker cores excluded by the TOD process would not be available for the dynamic process described above (outside of exception paths). [o068]
According to some examples, processing component 1002 may execute processing operations or logic for instructions stored on storage medium 900. Processing component 1002 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. Examples of software elements may include software components, programs, applications, computer programs, application programs, device drivers, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given example.
In some examples, other platform components 1004 may include common computing elements, such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input/output (I/O) components (e.g., digital displays), power supplies, and so forth. Examples of memory units may include without limitation various types of computer readable and machine readable storage media in the form of one or more higher speed memory units, such as read-only memory (ROM), random-access memory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), types of non-volatile memory such as 3-D cross-point memory that may be byte or block addressable. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level PCM, resistive memory, nanowire memory, FeTRAM, MRAM that incorporates memristor technology, STT-MRAM, or a combination of any of the above. Other types of computer readable and machine-readable storage media may also include magnetic or optical cards, an array of devices such as Redundant Array of Independent Disks (RAID) drives, solid state memory devices (e.g., USB memory), solid state drives (SSD) and any other type of storage media suitable for storing information.
In some examples, communications interface 1006 may include logic and/or features to support a communication interface. For these examples, communications interface 1006 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links or channels. Direct communications may occur via use of communication protocols or standards described in one or more industry standards (including progenies and variants) such as those associated with the PCIe specification. Network communications may occur via use of communication protocols or standards such those described in one or more Ethernet standards promulgated by IEEE. For example, one such Ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications such as the OpenFlow Switch Specification.
The components and features of computing platform 1000, including logic represented by the instructions stored on storage medium 900 may be implemented using any combination of discrete circuitry, ASICs, logic gates and/or single chip architectures. Further, the features of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic” or “circuit.”
It should be appreciated that the exemplary computing platform 1000 shown in the block diagram of
Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASIC, programmable logic devices (PLD), digital signal processors (DSP), FPGA, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and/or software elements may vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints, as desired for a given implementation.
Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, API, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.
Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.
Included herein are logic flows or schemes representative of example methodologies for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may, in accordance therewith, occur in a different order and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.
A logic flow or scheme may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow or scheme may be implemented by computer executable instructions stored on at least one non-transitory computer readable medium or machine readable medium, such as an optical, magnetic or semiconductor storage. The embodiments are not limited in this context.
Some examples are described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
