Claims
- 1. A method to reduce intermodulation distortion of a power amplifier, comprising:
providing a signal to a power amplifier; and boosting the voltage source power to the power amplifier to reduce intermodulation distortion.
- 2. The method of claim 1, wherein boosting the voltage source power comprises:
configuring a power booster to boost the voltage source power to the power amplifier.
- 3. The method of claim 1, wherein boosting the voltage source power comprises:
boosting the voltage source above 27 Volts DC.
- 4. The method of claim 1, wherein boosting the voltage source power comprises:
boosting the voltage source by 1 to 15 Volts DC.
- 5. The method of claim 1, wherein boosting the voltage source power comprises:
boosting the voltage source by 2 to 8 Volts DC.
- 6. The method of claim 1, further comprising:
sampling the power amplifier's output.
- 7. The method of claim 6, wherein boosting the voltage source power comprises:
adaptively boosting the power booster based on the sampling of the power amplifier's output.
- 8. The method of claim 1, wherein boosting of the voltage source power is done only when the power amplifier is operating within twenty percent of its maximum power output.
- 9. The method of claim 1, wherein the power amplifier is a radio-frequency linear power amplifier.
- 10. The method of claim 1, wherein the power amplifier comprises lateral diffusion metal oxide semiconductor transistors.
- 11. An apparatus to reduce intermodulation distortion of a power amplifier, comprising:
a power amplifier; a power booster comprising:
a first port coupled to a power source; and a second port coupled to the amplifier and provide voltage source power to the power amplifier; wherein the power booster increases the voltage from the first port to the second port.
- 12. The apparatus of claim 11, further comprising:
a sampling device to sample the power amplifier's output signal.
- 13. The apparatus of claim 12, wherein the sampling device comprises a root-mean-square detector.
- 14. The apparatus of claim 12, further comprising:
a microprocessor coupled to the sampling device and coupled to the power booster to configure the power booster based on the measured sample of the power amplifier's output.
- 15. The apparatus of claim 11, wherein the power booster comprises:
a third and a fourth port to configure the power booster.
- 16. The apparatus of claim 15, further comprising:
an adjustment component coupled between to the third port and fourth port of the power booster to configure the power output of the booster.
- 17. The apparatus of claim 15, wherein the adjustment component comprises a potentiometer.
- 18. The apparatus of claim 15, further comprising:
a reference voltage source coupled to the fourth port, the third port coupled to the second port of the power booster to configure the power output of the booster.
- 19. The apparatus of claim 11, wherein the power amplifier comprises a radio-frequency linear power amplifier.
- 20. The apparatus of claim 11, wherein the power amplifier comprises a plurality of transistors.
- 21. The apparatus of claim 20, wherein the power transistors comprise lateral diffusion metal oxide semiconductor transistors.
- 22. An apparatus to reduce intermodulation distortion of a power amplifier, comprising:
a power amplifier; and means for boost the source voltage of the power amplifier so as to reduce intermodulation distortion.
- 23. The apparatus of claim 22, further comprising:
means for configuring a power booster to boost the voltage source power to the power amplifier.
- 24. The apparatus of claim 22, further comprising:
means for sampling the power amplifier's output.
- 25. The apparatus of claim 22, wherein boosting the voltage source power comprises:
means for adaptively configuring the power booster based on the sampling of the power amplifier's output.
- 26. The apparatus of claim 22, wherein the power amplifier comprises lateral diffusion metal oxide semiconductor transistors.
- 27. A machine-readable medium comprising at least one instruction to boost the source power of a power amplifier, which when executed by a processor, causes the processor to perform operations comprising:
configuring a power booster to provide an increased source voltage to the power amplifier.
- 28. The machine-readable medium of claim 27, further comprising at least one instruction for configuring the power booster to provide a decreased source voltage to the power amplifier.
- 29. The machine-readable medium of claim 27, further comprising at least one instruction to obtain a sample of the power amplifier's output.
- 30. The machine-readable medium of claim 29, further comprising at least one instruction to adaptively configure the power booster to increase or decrease the source voltage to the power amplifier based on the sample of the power amplifier's output.
- 31. A system to boost the source power of a power amplifier, comprising:
a first sub-system to configure a power booster to provide an increased source voltage to the power amplifier.
- 32. The system of claim 31, wherein the first sub-system can configure the power booster to provide a decreased source voltage to the power amplifier.
- 33. The system of claim 31, further comprising:
a second sub-system to obtain a sample of the power amplifier's output.
- 34. The system of claim 31, further comprising:
a second sub-system to configure the power booster to increase or decrease the source voltage to the power amplifier.
RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/181,345 filed on Feb. 9, 2000 (Attorney Docket No. 004711.P001Z) and U.S. Provisional Patent Application Ser. No. 60/185,311 filed on Feb. 28, 2000 (Attorney Docket No. 004711.P002Z).
Provisional Applications (2)
|
Number |
Date |
Country |
|
60181345 |
Feb 2000 |
US |
|
60185311 |
Feb 2000 |
US |