Patent Application
20150333709
The present invention relates to a power combining circuit and a power combining method, and more particularly to a power combining circuit and a power combining method for use in a high frequency band such as a VHF band or a UHF band, for instance, a power combining circuit and a power combining method for use in operating high frequency power units such as a power amplifier, a power distributor, a power combiner, and a filter circuit in a TV transmitter, an FM transmitter, or the like in parallel.
As a conventional art relating to a power combining circuit configured to combine high frequency powers obtained by operating high frequency power units in a TV transmitter, an FM transmitter, or the like in parallel and to output the combined powers, there is known a technique described in Patent Literature 1 i.e. Japanese Patent Publication No. 2,639,032 entitled “Energy-Coupling Device”. The power combining circuit described in Patent Literature 1 is provided with a plurality of amplifiers; a 3 dB-hybrid circuit which distributes the signals from each of the amplifiers to two signals having a phase difference of 90 degrees from each other; two couplers which couple the signals, among the distributed signals in phase with each other; and a back-end positioned 3 dB-hybrid circuit which distributes the coupled two signals to two signals so that one of the two signals is output to an antenna, and the other of the two signals is terminated at a terminator. The power combining circuit has a simplified configuration, without a filter for removing a spurious component generated in the amplifiers.
Japanese Patent Publication No. 2,639,032 (pages 2-4)
Therefore, in the conventional art described in Patent Literature 1, when power of a high frequency signal is amplified, the signal waveform may be distorted by non-linearity of the amplifiers, and a harmonics may be generated at a frequency of an integral multiple (2-times, 3-times, 4-times, . . . ) of a fundamental frequency.
Further, in the out-of-band region near an intended wave, a spurious component known as intermodulation distortion (IM) may be generated by non-linearity of the amplifiers. Generally, a filter such as a low-pass filter or a band-pass filter is used in order to output signals, in which a spurious component in the out-of-band region is removed. However, when a spurious component generated in the amplifiers is reflected on the filter and the reflected component returns to the amplifiers, troubles such as a failure of the amplifiers may occur.
The present invention has been made in view of the above, and an object of the present invention is to provide a power combining circuit and a power combining method that is capable of suppressing and absorbing a spurious component generated by power amplification.
In order to solve the above problem, a power combining circuit and a power combining method according to the present invention mainly include the following distinguishing configuration.
(1) A power combining circuit according to the present invention is a power combining circuit for combining high frequency powers having arbitrary frequencies. The power combining circuit is provided with at least an amplifier which amplifies an input high frequency power; a 3 dB-hybrid circuit which distributes an output from the amplifier to two signals having a phase difference of 90 degrees from each other; two filters which remove a spurious component included in each of the two signals from the 3 dB-hybrid circuit; and a back-end positioned hybrid circuit which power-combines the signals from the two filters for output.
(2) A power combining method according to the present invention is a power combining method for use in a power combining circuit for combining high frequency powers having arbitrary frequencies. The power combining method is provided with at least, after distributing an output from an amplifier to two signals having a phase difference of 90 degrees from each other by a 3 dB-hybrid circuit, filtering the two signals for removing a spurious component included in each of the two signals in order to remove the spurious component generated when an input high frequency power is amplified by the amplifier.
According to the power combining circuit and the power combining method of the present invention, the following advantageous effects are obtained.
As a first advantageous effect, newly providing the filters makes it possible to securely impart the filter effect for removing a spurious component in power combining, and to securely prevent an unwanted spurious component from being output to an antenna.
As a second advantageous effect, it is possible to suppress and absorb a spurious component generated in the amplifier by a terminator, without reflection on the filters and without returning to the amplifier. Thus, the above configuration is advantageous in securely preventing failure of the amplifier.
Hereinafter, a preferred exemplary embodiment of a power combining circuit and a power combining method according to the present invention is described referring to the accompanying drawings.
Prior to description of an exemplary embodiment of the present invention, an outline of the features of the present invention is described. The present invention is an invention particularly relating to a power combining circuit and a power combining method for use in a high frequency band such as a VHF band or a UHF band, for instance, a power combining circuit and a power combining method for use in operating high frequency power units such as a power amplifier, a power distributor, a power combiner, and a filter circuit in a TV transmitter, an FM transmitter, or the like in parallel. The main features of the invention are such that it is possible to impart the characteristics of a filter to the power combining circuit, and it is possible to absorb a spurious signal component signal reflected on the filter by a terminator, without returning to an amplifier (an amplifier constituted of e.g. an FET (Field Effect Transistor) circuit).
More specifically, the invention includes the following configuration. Each of the signals to be output from 1st to n-th amplifiers PA1 to PAn (where n is a positive integer of 2 or more) constituting a power combining circuit is distributed to two signals by 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn, each of which has a coupling degree of 3 dB. In distributing the signals, each of the signals is distributed to two signals with the same amplitude. However, in comparison with the phase of a signal to be output to one of the terminals (e.g. a terminal 3), the phase of a signal to be output to the other one of the terminals (e.g. a terminal 4) has a −90 degree phase delay.
Subsequently, two signals obtained by combining powers in phase with each other in a signal group having a 0-degree phase component, and in a signal group having a −90 degree phase delay component are respectively input to filters newly provided for removing a spurious component. After removal of a spurious component, the two signals that have passed through the respective filters are power-combined by a 0th hybrid circuit HYB0 having a coupling degree of 3 dB for outputting to an antenna.
The filters for removing a spurious component are disposed at positions where impedance transformation is necessary when signals of the branching number n (where n is a positive integer of 2 or more), which are in phase with each other, are power-combined. Further, it is possible to configure a filter having an impedance transformation function, in which the impedance of an input port of the filter is set to (ZΩ/n), and the impedance of an output port of the filter is adjusted to ZΩ (where Z is a constant that is arbitrarily set in advance as a matching impedance value).
Next, an example of an internal configuration of the power combining circuit capable of suppressing and absorbing a spurious component, as an exemplary embodiment of the present invention, is described using the block configuration illustrated in
The power combining circuit illustrated in
In the power combining circuit illustrated in
Further, 13-th, 23-th, . . . , and n3-th output terminals 13, 23, . . . , and n3 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn for use in outputting a 0-degree phase signal are mutually connected to each other at the first coupler C1. A characteristic impedance of the line at the position of the first coupler C1 is set to (Z/n)Ω (where Z is a constant that is arbitrarily set in advance as a matching impedance value, e.g., “50”). However, the characteristic impedance is transformed to the matching impedance ZΩ at a final stage via the first impedance transformation line TR1. Thus, the first coupler C1 is connected to the first filter FILTER1. Likewise, 14-th, 24-th, . . . , and n4-th output terminals 14, 24, . . . , and n4 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn for use in outputting a −90 degree phase delay signal are mutually connected to each other at the second coupler C2. The characteristic impedance of the line at the position of the second coupler C2 is transformed to the matching impedance ZΩ at a first stage via the second impedance transformation line TR2, as well as the case of the first impedance transformation line TR1. Thus, the second coupler C2 is connected to the second filter FILTER2.
After the impedance transformation into the matching impedance ZΩ, e.g. 50Ω, via the respective first and second impedance transformation lines TR1 and TR2, the respective signals are input to the first and second filters FILTER1 and FILTER2 having the same electrical characteristics. The output terminals of the first and second filters FILTER1 and FILTER2 are respectively connected to 01-th and 02-th input terminals 01 and 02 of the back-end positioned hybrid circuit i.e. the 0th hybrid circuit HYB0 having a coupling degree of 3 dB.
A 03-th isolation terminal 03 of the 0th hybrid circuit HYB0 is connected to the back-end positioned terminator i.e. the 0th terminator DL0 for terminating an unwanted signal component to be output from the first and second filters FILTER1 and FILTER2. A 04-th output terminal 04, which combines the signal components to be output from the first and second filters FILTER1 and FILTER2 for output, is connected to the antenna ANT.
According to the internal configuration as described above, the power combining circuit illustrated in
Next, an operation to be performed by the power combining circuit illustrated in
As illustrated in the schematic diagram of
Each of the high frequency signals input from the 1st, 2nd, . . . , and n-th amplifiers PA1, PA2, . . . , and PAn is distributed to two signals, and the respective two signals are output, as output signals of the same amplitude, to the 13-th, 23-th, . . . , and n3-th output terminals 13, 23, . . . , and n3 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn, and to the 14-th, 24-th, . . . , and n4-th output terminals 14, 24, . . . , and n4 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn. When the signals are output, the phases of the signals to be output to the 14-th, 24-th, . . . and n4-th output terminals 14, 24, . . . , and n4 respectively have a −90 degree phase delay with respect to the phases of the signals to be output to the 13-th, 23-th, . . . , and n3-th output terminals 13, 23, . . . , and n3 (sequence Seq2).
The signals distributed to the 13-th, 23-th, . . . , and n3-th output terminals 13, 23, . . . , and n3 are guided to the first coupler C1. The characteristic impedance of the line at the position of the first coupler C1 is set to (Z/n)Ω. However, impedance transformation is performed until the matching impedance ZΩ is obtained by the line of the first impedance transformation line TR1 before the signal reaches the input terminal of the first filter FILTER1 from the first coupler C1 (sequence Seq3). Thereafter, the signal that has passed through the first filter FILTER1 for removing a spurious component is guided to a 01-th input terminal 01 of the back-end positioned hybrid circuit i.e. the 0th hybrid circuit HYB0 (sequence Seq4).
Further, the signals having a −90 degree phase delay distributed to the 14-th, 24-th, . . . , and n4-th output terminals 14, 24, . . . , and n4 are guided to the second coupler C2. The characteristic impedance of the line at the position of the second coupler C2 is set to (Z/n)Ω. However, as well as the case of the first coupler C1, impedance transformation is performed until the matching impedance ZΩ is obtained by the line of the second impedance transformation line TR2 before the signal reaches the input terminal of the second filter FILTER2 from the second coupler C2 (sequence Seq5). Thereafter, the signal that has passed through the second filter FILTER2 for removing a spurious component is guided to a 02-th input terminal 02 of the back-end positioned hybrid circuit i.e. the 0th hybrid circuit HYB0 (sequence Seq6).
A phase difference between the signal guided to the 01-th input terminal 01 of the back-end positioned hybrid circuit i.e. the 0th hybrid circuit HYB0, and the signal guided to the 02-th input terminal 02 of the 0th hybrid circuit HYB0 is 90 degrees (in other words, the signal on the 02-th input terminal 02 is a signal having a −90 degree phase delay with respect to the signal on the 01-th input terminal 01). Therefore, power combining is performed on the side of the 04-th output terminal 04 of the 0th hybrid circuit HYB0, which is connected to the antenna ANT, and a signal is output to the antenna ANT (sequence Seq7). On the other hand, the phase of combined power is reversed on the side of the 03-th isolation terminal 03, which is connected to the back-end positioned terminator i.e. the 0th terminator DL0 so that power is not output from the 0th terminator DL0 (sequence Seq8).
A spurious component that is unable to pass through the first and second filters FILTER1 and FILTER2 is respectively reflected on the first and second filters FILTER1 and FILTER2, and respectively returns to the first and second couplers C1 and C2 via the first and second impedance transformation lines TR1 and TR2 (sequence Seq9). Thereafter, the reflected spurious component respectively returns from the first coupler C1 and the second coupler C2 to the 13-th, 23th, . . . , and n3-th output terminals 13, 23, . . . , and n3 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn, and to the 14-th, 24-th, . . . , and n4-th output terminals 14, 24, . . . , and n4 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn (sequence Seq10).
A phase difference between a reflected signal with respect to the 13-th, 23-th, . . . , and n3-th output terminals 13, 23, . . . , and n3 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn, and a reflected signal with respect to the 14-th, 24-th, . . . , and n4-th output terminals 14, 24, . . . , and n4 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn is 90 degrees. The phase of reflected power is reversed on the side of the 11-th, 21-th, . . . , and n1-th input terminals 11, 21, . . . , and n1 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn to which the 1st, 2nd, . . . , and n-th amplifiers PA1, PA2, . . . , and PAn are respectively connected so that power of the reflected spurious component is not output (sequence Seq11).
On the other hand, on the side of the 12-th, 22-th, . . . , and n2-th isolation terminals 12, 22, . . . , and n2 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn to which the 1st, 2nd, . . . , and n-th terminators DL1, DL2, . . . , and DLn are respectively connected, a reflected spurious component is output to the 1st, 2nd, . . . , and n-th terminators DL1, DL2, . . . , and DLn; and power is absorbed by the 1st, 2nd, . . . , and n-th terminators DL1, DL2, . . . , and DLn (sequence Seq12).
According to the aforementioned operation, the power combining circuit illustrated in
It is needless to say that, also in the exemplary embodiment, the isolation function between a plurality of amplifiers (amplifiers each constituted of e.g. an FET (Field Effect Transistor) circuit) provided in a conventional power combining circuit (in other words, a function to absorb power from an amplifier by a terminator and to prevent returning of reflected power to the other amplifiers, even if a failure occurs in the amplifier) is implemented substantially in the same manner by the 1st, 2nd, . . . , and n-th terminators DL1, DL2, . . . , and DLn respectively connected to the 12-th, 22-th, . . . , and n2-th isolation terminals 12, 22, . . . , and n2 of the 1st, 2nd, . . . , and n-th hybrid circuits HYB1, HYB2, . . . , and HYBn.
Further, it is also needless to say that the first and second filters FILTER1 and FILTER2 for removing a spurious component are not limited to a band-pass filter configured to pass only a signal component in an intended frequency band. The same configuration as described above is also applicable to a low-pass filter configured to pass a low frequency signal component in a frequency band equal to or lower than an intended frequency band, and to a high-pass filter configured to pass a high frequency signal component in a frequency band equal to or higher than an intended frequency band.
Further, it is possible to provide a circuit configuration as illustrated in
Further, the power combining circuit illustrated in
The exemplary embodiment has overcome the drawbacks of the conventional power combining circuit, and provides the following advantageous effects.
As a first advantageous effect, providing the first and second filters FILTER1 and FILTER2 is advantageous in securely imparting the filter effect for removing a spurious component in power combining, and in securely preventing an unwanted spurious component from being output to the antenna ANT.
As a second advantageous effect, it is possible to suppress and absorb a spurious component generated in the 1st, 2nd, . . . , and n-th amplifiers PA1, PA2, . . . , and PAn by the 1st, 2nd, . . . , and n-th terminators DL1, DL2, . . . , and DLn, without reflection on the first and second filters FILTER1 and FILTER2, and without returning to the 1st, 2nd, . . . , and n-th amplifiers PA1, PA2, . . . , and PAn. Thus, it is possible to securely prevent failure of the 1st, 2nd, . . . , and n-th amplifiers PA1, PA2, . . . , and PAn.
The configuration of a preferred embodiment of the present invention has been described as above. Note that the exemplary embodiment is merely an example of the present invention, and does not limit the invention. It is to be easily understood that various changes and modifications will be apparent to those skilled in the art depending on a purpose of use, as far as such changes and modifications do not depart from the gist of the invention.
This application claims the priority based on Japanese Patent Application No. 2012-204214 filed on Sep. 18, 2012, and all of the disclosure of which is hereby incorporated.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-204214 | Sep 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/002431 | 4/10/2013 | WO | 00 |
