Patent Application
20080309306
The present invention relates to power control circuits such as those used in liquid crystal displays (LCDs), and more particularly to a power control circuit configured for controlling power sequence of gate drivers of an LCD. The present invention also relates to an LCD employing the power control circuit.
A typical LCD has the advantages of portability, low power consumption, and low radiation. Therefore the LCD has been widely used in various portable information products, such as notebooks, personal digital assistants (PDAs), video cameras, and the like.
The LCD typically includes gate drivers for outputting gate signals to control switch elements of a liquid crystal display panel. For example, when the gate signals are high-level voltage signals, the switch elements of the liquid crystal display panel are turned on. When the gate signals are low-level voltage signals, the switch elements of the liquid crystal display panel are turned off. Thus the LCD needs a power control circuit for providing a power voltage, a high-level voltage, and a low-level voltage to enable the gate drivers to function.
Typically, time delays of electronic elements of the power control circuit are different, yet the power voltage, the high-level voltage, and the low-level voltage are in effect almost simultaneously applied to the gate drivers. As a result, the functioning of electronic elements (not shown) in the gate drivers is uncertain. That is, the gate drivers may operate improperly. When this happens, the LCD employing the power control circuit may display images incorrectly.
What is needed, therefore, is a power control circuit that can overcome the above-described deficiencies, and an LCD employing the power control circuit.
A power control circuit includes a scaler circuit configured for outputting a control signal, a voltage converter configured for converting a received voltage into a plurality of desired voltages, a first control unit, a second control unit, and a coupling circuit. The first control unit is configured for controlling whether a first voltage is applied to the voltage converter. The second control unit is configured for controlling whether to transmit a second voltage applied thereto. The coupling circuit is between the first and second control units. The coupling circuit enables the second control unit to function ahead of the voltage converter according to the control signal.
Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Reference will now be made to the drawings to describe preferred and exemplary embodiments in detail.
The liquid crystal display panel 22 includes a number of gate drivers 25 for driving gate lines (not shown) of the liquid crystal display panel 22. The PCB 21 includes a power control circuit 24 for controlling power sequence of the gate drivers 25.
Referring also to
The first control unit 28 is provided for controlling whether a voltage received from the first input terminal 240 is applied to the voltage converter 27 according to a controlling signal output by the scaler circuit 245. The second control unit 29 is provided for controlling whether a voltage received from the second input terminal 241 is applied to the third output terminal 243. The voltage converter 27 is provided for converting the voltage received from the first input terminal 240 into two desired voltages. The two voltages are respectively provided as the high-level and low-level voltages of gate signals output by the gate drivers 25. The voltage output by the third output terminal 243 is applied to the gate drivers 25 as a power voltage. In the present embodiment, the high-level and low-level voltages of the gate signals are respectively +27V and −6V. The power voltage of the gate drivers 25 is +3.3V.
The first control unit 28 generally includes a first transistor 280, a second transistor 281, and a third transistor 282. In the present embodiment, the first transistor 280 is a negative-positive-negative (NPN) bipolar junction transistor, the second transistor 281 is a P-channel enhancement-mode metal-oxide-semiconductor field-effect transistor (P-MOSFET), and the third transistor 282 is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor (N-MOSFET). An output terminal (not labeled) of the scaler circuit 245 is connected to a base electrode (not labeled) of the first transistor 280 via a base bias resistor 283. An emitter electrode (not labeled) of the first transistor 280 is grounded. A collector electrode (not labeled) of the first transistor 280 is connected to a gate electrode (not labeled) of the second transistor 281.
A source electrode (not labeled) of the second transistor 281 is connected to the first input terminal 240. A drain electrode (not labeled) of the second transistor 281 is connected to an input terminal (not labeled) of the voltage converter 27. A first voltage-dividing resistor 284 is connected between the source and gate electrodes of the second transistor 281. A gate electrode (not labeled) of the third transistor 282 is connected to the gate electrode of the second transistor 281 via a gate resistor 285. A source electrode (not labeled) of the third transistor 282 is grounded. A drain electrode (not labeled) of the third transistor 282 is connected to the drain electrode of the second transistor 281 via a drain resistor 286. Two output terminals of the voltage converter 27 are respectively connected to the first and second output terminals 242, 244 of the power control circuit 24.
The second control unit 29 includes a fourth transistor 291, a second voltage-dividing resistor 292, and a third voltage-dividing resistor 293. In the present embodiment, the fourth transistor 291 is a positive-negative-positive (PNP) bipolar junction transistor. A base electrode (not labeled) of the fourth transistor 291 is connected to the gate electrode of the second transistor 281 via the coupling circuit 26. An emitter electrode (not labeled) of the fourth transistor 291 is connected to the second input terminal 241 of the power control circuit 24 via the second voltage-dividing resistor 292. A collector electrode (not labeled) of the fourth transistor 291 is connected to the third output terminal 243 of the power control circuit 24. The third voltage-dividing resistor 293 is connected between the emitter and base electrodes of the fourth transistor 291.
In operation, a +5V direct current voltage is applied to the first input terminal 240, and a +3.3V direct current voltage is applied to the second input terminal 241. Thereby, the first, second, and fourth transistors 280, 281, 291 are turned off and the third transistor 282 is turned on. The input terminal of the voltage converter 27 is grounded via the drain resistor 286 and the third transistor 282. As a result, the low-level voltage, the high level-voltage, and the power voltage cannot be applied to the gate drivers 25 via the first, second, and third output terminals 242, 244, 243.
In this instance, a voltage difference U1 applied to the two electrodes (not labeled) of the coupling capacitor 263 is expressed by the following equation:
where V1, V2 respectively represent the direct current voltages applied to the first and second input terminals 240, 241; R1, R3, R4 respectively represent resistances of the first, second, and third voltage-dividing resistors 284, 292, 293; and R2 represents a resistance of the coupling resistor 261. In the present embodiment, because V1>V2, the voltage applied to one electrode of the coupling capacitor 263 connected to the gate electrode of the second transistor 281 is greater than that applied to the other electrode of the coupling capacitor 263 connected to the base electrode of the fourth transistor 291.
If the gate drivers 25 need power, the scaler circuit 245 outputs an enable signal to the base electrode of the first transistor 280 via the base bias resistor 283. Thereby, the first transistor 280 is turned on, and low-level voltages are applied to the gate electrodes of the second and third transistors 281, 282. As a result, the second transistor 281 is turned on and the third transistor 282 is turned off. The +5V direct current voltage is applied to the voltage converter 27, and is converted into +27V, −6V direct current voltages therein. The 27V, −6V direct current voltages are then respectively applied to each of the gate drivers 25 via the second and first output terminals 244, 242.
Moreover, once the first transistor 280 is turned on, the voltage applied to the electrode of the coupling capacitor 263 connected to the gate electrode of the second transistor 281 is 0V. In this instance, according to the principle of charge conservation, the voltage difference between the two electrodes of the coupling capacitor 263 is maintained as U1. That is, the voltage U2 applied to the base electrode of the fourth transistor 291 is expressed by the following equation:
As a result, the voltage difference U3 between the emitter and base electrodes of the fourth transistor 291 is expressed by the following equation:
In contrast, consider a voltage difference U4 between the emitter and base electrodes of the fourth transistor 291 in the case where there is no coupling circuit 26. U4 is expressed by the following equation:
Compared to such voltage difference U4, the voltage difference U3 is increased. That is, a larger electrical current flows through the base electrode of the fourth transistor 291 so as to turn on the fourth transistor 291 more quickly. Thereby, the third output terminal 243 provides power voltage to the gate drivers 25 ahead of the low-level and high-level voltages output by the first and the second output terminals 242, 244. Therefore, normal functioning of electronic elements (not shown) in the gate drivers 25 is ensured. As a result, the gate drivers 25 can operate normally, and the LCD 20 employing the gate drivers 25 can display images correctly.
It is to be further understood that even though numerous characteristics and advantages of the present embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and that changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007100750493.3 | Jun 2007 | CN | national |
