Patent Application
20240281014
The disclosure herein relates to a power control device and a power supply device.
Conventionally, power control devices have been developed that have a function of feeding information on an output current back to a driver.
An example of known technology related to what has just been mentioned is seen in Patent Document 1 identified below.
Patent Document 1: WO2020/090551
The output transistor M1 is connected between an input terminal for the input voltage Vin and an output terminal for the output voltage Vout and is driven according to a gate driving signal G1.
The source of the output transistor M1 is connected to the input terminal for the input voltage Vin. The drain of the output transistor M1 is connected to the output terminal for the output voltage Vout. The gate of the output transistor M1 is connected to an application terminal for the gate driving signal G1. The on-resistance Ron1 of the output transistor M1 is variably controlled according to the gate driving signal G1.
As the gate driving signal G1 increases, the gate-source voltage Vgs1 of the output transistor M1 decreases; thus the on-resistance Ronl of the output transistor M1 increases and an output current Iout passing through the output transistor M1 decreases. In contrast, as the gate driving signal G1 decreases, the gate-source voltage Vgs1 of the output transistor M1 increases; thus the on-resistance Ron1 of the output transistor M1 decreases and the output current Iout out passing through the output transistor M1 increases.
The resistors R1 and R2 are connected in series with each other between the output terminal for the output voltage Vout and a ground terminal. The resistors R1 and R2 function as a voltage divider circuit that outputs from the connection node between them a feedback voltage Vfb (={R2/(R1+R2)}×Vout) corresponding to the output voltage Vout. In a case where the output voltage Vout is within the input dynamic range of the error amplifier A1, the resistors R1 and R2 may be omitted, in which case the output voltage Vout can be fed directly to the error amplifier A1.
The capacitor C1 is connected in series between the output terminal for the output voltage Vout and the grounded terminal. The capacitor C1 functions as a smoothing means for the output voltage Vout.
The reference voltage generation circuit REF generates a predetermined reference voltage Vref from the input voltage Vin. Suitably used as the reference voltage generation circuit REF is, for example, a band-gap reference voltage source with flat input voltage dependence and temperature dependence.
The error amplifier A1 generates an error signal ERR between the feedback voltage Vfb, which is fed to its non-inverting input terminal (+), and the reference voltage Vref, which is fed to its inverting input terminal (−), to output the error signal ERR as the gate driving signal G1. Thus, the gate driving signal G1 lowers when the feedback voltage Vfb is lower than the reference voltage Vref, and rises when the feedback voltage Vfb is higher than the reference voltage Vref. The error amplifier A1 can be understood as one example of an output feedback circuit configured to receive the output voltage Vout or the feedback voltage Vfb corresponding to it to generate the gate driving signal G1 for the output transistor M1.
The current feedback signal generation circuit IFB generates a current feedback signal Ifb for adjusting the phase characteristics of the output feedback circuit (in particular, the error amplifier A1) according to the output current Iout out of the power supply device 1.
Of the circuit elements described above, the output transistor M1, the reference voltage generation circuit REF, the error amplifier A1, the resistors R1 and R2, and the current feedback signal generation circuit IFB may be integrated in a power control device 10 (a semiconductor device that serves as the principal controlling agent in the power supply device 1; what is called a power control IC). The output transistor M1 and the resistors R1 and R2 may be externally connected to the power control device 10.
With reference still to
The mirror transistor M21 is driven by the gate driving signal G1, which it shares with the output transistor M1, to generate a mirror current Im that increases and decreases in a similar manner as the output current Iout.
The source of the mirror transistor M21 is connected to the input terminal for the input voltage Vin. The drain of the mirror transistor M21 (i.e., an output terminal for the mirror current Im) is connected to the drain of the transistor M22. The gate of the mirror transistor M21 is connected to the application terminal for the gate driving signal G1. The on-resistance Ron21 of the mirror transistor M21 is variably controlled according to the gate driving signal G1.
As the gate driving signal G1 increases, the gate-source voltage Vgs21 of the mirror transistor M21 decreases; thus the on-resistance Ron21 of the mirror transistor M21 increases and the mirror current Im passing through the mirror transistor M21 decreases. In contrast, as the gate driving signal G1 decreases, the gate-source voltage Vgs21 of the mirror transistor M21 increases; thus the on-resistance Ron21 of the mirror transistor M21 decreases and the mirror current Im passing through the mirror transistor M21 increases.
The size of the transistor M21 is smaller than the size of the output transistor M1. Thus, the mirror current Im is smaller than the output current Iout.
The drain of the transistor M22 is, as described above, connected to the drain of the mirror transistor M21 (i.e., the output terminal for the mirror current Im). The gates of the transistors M22 and M23 are both connected to the drain of the transistor M22. The sources of the transistors M22 and M23 are both connected to the ground terminal. The drain of the transistor M23 (i.e., an output terminal for the current feedback signal Ifb) is connected to the output feedback circuit (in particular, to the error amplifier A1).
So connected, the transistors M22 and M23 function as a current mirror that, by mirroring the mirror current Im in a predetermined mirror ratio a, generates the current feedback signal Ifb (=α×Im).
The output feedback circuit that receives the current feedback signal Ifb controls the characteristics of the error amplifier A1 according to the current feedback signal Ifb so as to obtain desired frequency characteristics. For example, the error amplifier A1 can be configured so as to, as the current feedback signal Ifb (and hence the output current Iout) increases, decrease the gain, shift the zero-crossing frequency lower, decrease the drive current, or control a pole or zero point.
In the power supply device 1 of the above comparative example, while it is easy to obtain desired frequency characteristics, there is room for further improvement in load response characteristics.
Based on the above discussion, the following description presents a novel embodiment that provides desired frequency characteristics without sacrificing load response characteristics.
The delay circuit DLY1 is a circuit block configured to delay a change in the current feedback signal Ifb in response to a change in the output current Iout, and includes a resistor R21 and a capacitor C21.
The resistor R21 is connected between the application terminal for the gate driving signal G1 and the gate of the mirror transistor M21. The capacitor C21 is connected between the gate and the source of the mirror transistor M21.
Thus connected, the resistor R21 and the capacitor C21 function as an RC filter that gives the gate driving signal G1 a delay and thereby generates a delayed driving signal G1d to feed it to the gate of the mirror transistor M21.
As indicated by the broken lines in the diagram, in the comparative example (FIG. 1) described previously, the current feedback signal Ifb is made to follow without delay a load variation (an increase in the output current Iout in the diagram) with a view to, for example, lowering the gain of the error amplifier A1. While this helps stabilize the phase characteristics, degraded load response characteristics causes a large variation (a drop in the diagram) in the output voltage Vout.
By contrast, as indicated by the solid lines in the diagram, in this embodiment (
Like the delay circuit DLY1 described previously, the delay circuit DLY2 is a circuit block configured to delay a change in the current feedback signal Ifb in response to a change in the output current Iout, and includes a resistor R22 and a capacitor C22.
The resistor R22 and the capacitor C22 are connected in series with each other between the drain of the transistor M22 and the drain of the transistor M23, that is, between the input terminal and the output terminal of the current mirror.
So connected, the resistor R22 and the capacitor C22 function as an RC filter that delays a change in the current feedback signal Ifb output from the current mirror in response to a change in the mirror current Im input to the current mirror.
While the power supply device 1 of this embodiment includes both the delay circuits DLY1 and DLY2, a configuration is also possible where the delay circuit DLY1 is omitted and only the delay circuit DLY2 is included.
The delay circuit DLY3 is, like the delay circuit DLY1 described previously, a circuit block configured to delay a change in the current feedback signal Ifb in response to a change in the output current Iout, and includes a resistor R23 and a capacitor C23.
The resistor R23 is connected between the gate of the transistor M22 and the gate of the transistor M23. The capacitor C23 is connected between the gate of the transistor M23 and the ground terminal (one example of a constant potential terminal).
So connected, the resistor R23 and the capacitor C23, like the delay circuit DLY2 described previously, function as an RC filter that delays a change in the current feedback signal Ifb output from the current mirror in response to a change in the mirror current Im input to the current mirror.
While the power supply device 1 of this embodiment includes both the delay circuits DLY1 and DLY3, a configuration is also possible where the delay circuit DLY1 is omitted and only the delay circuit DLY3 is included. Or, a configuration is also possible where the delay circuits DLY2 and DLY3 are both included or the delay circuits DLY1 to DLY3 are all included.
Specifically, an output stage of the power supply device 1 includes, in addition to the output transistor M1 described previously, a rectifier diode D1 and an inductor L1. The rectifier diode D1 can be replaced with a synchronous rectification transistor.
The output feedback circuit in the power supply device 1 includes a controller CTRL that performs PWM (pulse-width modulation) control for the output transistor M1 according to the error signal ERR output from the error amplifier A1.
Also the power supply device 1 of this embodiment has introduced in it the current feedback signal generation circuit IFB and the delay circuit DLY described previously.
In this way, the delay circuit DLY, which delays a change in the current feedback signal Ifb in response to a change in the output current Iout, can be introduced not only in LDO regulators but also in switching regulators.
The switching regulator is not limited to a buck type; it may instead be of a boost type, of a boost/buck type, or of an inverting type.
To follow is an overview of the various embodiments described above.
For example, according to one aspect of what is disclosed herein, a power control device is configured to serve as a main controlling agent in a power supply device which generates an output voltage from an input voltage using an output transistor. The power control device includes: an output feedback circuit configured to receive the output voltage or a feedback voltage corresponding to it to generate a driving signal for the output transistor; a current feedback signal generation circuit configured to generate a current feedback signal for adjusting the phase characteristics of the output feedback circuit according to the output current of the power supply device; and a delay circuit configured to delay a change in the current feedback signal in response to a change in the output current. (A first configuration.)
In the power control device according to the first configuration described above, preferably, the current feedback signal generation circuit includes: a mirror transistor configured to be driven according to the driving signal so as to generate a mirror current corresponding to the output current; and a current mirror configured to generate the current feedback signal from the mirror current. (A second configuration.)
In the power control device according to the second configuration described above, preferably, the delay circuit gives the driving signal a delay to generate a delayed driving signal and feeds it to the control terminal of the mirror transistor. (A third configuration.)
In the power control device according to the third configuration described above, preferably, the delay circuit includes a first resistor and a first capacitor. The first resistor may be connected between an application terminal for the driving signal and the control terminal of the mirror transistor, and the first capacitor may be connected between the control terminal of the mirror transistor and a main electrode of the mirror transistor. (A fourth configuration.)
In the power control device according to any of the second to fourth configurations described above, preferably, the delay circuit delays a change in the current feedback signal output from the current mirror in response to a change in the mirror current input to the current mirror. (A fifth configuration.)
In the power control device according to the fifth configuration described above, preferably, the delay circuit includes a second resistor and a second capacitor, and the second resistor and the second capacitor are connected in series between the input terminal and the output terminal of the current mirror. (A sixth configuration.)
In the power control device according to the fifth or sixth configuration described above, preferably, the current mirror includes a first transistor and a second transistor, and the delay circuit includes a third resistor and a third capacitor. The third resistor may be connected between the control terminal of the first transistor and the control terminal of the second transistor, and the third capacitor may be connected between the control terminal of the second transistor and a constant potential terminal. (A seventh configuration.)
In the power control device according to any of the first to seventh configurations described above, preferably, the output feedback circuit includes an error amplifier configured to generate an error signal corresponding to the difference between the output voltage or the feedback voltage and a predetermined reference voltage. (An eighth configuration.)
In the power control device according to the eighth configuration described above, preferably, the output feedback circuit controls the characteristics of the error amplifier according to the current feedback signal. (A ninth configuration.)
For example, according to another aspect of what is disclosed herein, a power supply device includes the power control device according to any of the first to ninth configurations described above. (A tenth configuration.)
With the disclosure herein, it is possible to provide a power control device and a
power supply device with enhanced load response characteristics.
The various technical features disclosed herein may be implemented in any other manners than in the embodiments described above, and allow for any modifications made without departure from their technical ingenuity. For example, any bipolar transistor may be replaced with a MOS field-effect transistor and vice versa; the logic levels of any signal may be inverted. That is, the embodiments described above should be taken to be in every aspect illustrative and not restrictive, and the technical scope of the present disclosure is understood to be defined not by the description of the embodiments given above but by the appended claims and encompass any modifications within a scope and sense equivalent to those claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-187647 | Nov 2021 | JP | national |
This nonprovisional application is a continuation application of International Patent Application No. PCT/JP2022/037788 filed on Oct. 11, 2022, which claims priority Japanese Patent Application No. 2021-187647 filed on Nov. 18, 2021, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/037788 | Oct 2022 | WO |
| Child | 18654104 | US |
