Patent Application
20120062752
1. Technical Field
The disclosure generally relates to power conversion circuits, and more particularly relates to a power conversion circuit used in an internet protocol (IP) camera.
2. Description of the Related Art
IP cameras are commonly employed for surveillance, and send and receive data via a computer network and the internet. An IP camera typically includes a system on chip (SOC)/central processing unit (CPU), image processing chips, audio chips, and system power, which are electrically located on a main board of the IP camera. Moreover, image sensors, such as complementary metal oxide semiconductor (CMOS) sensors or charge coupled device (CCD) sensors, and a sub-power source are usually electrically located on a sub-board of the IP camera. The system power provides operating voltage for the sub-power source.
However, when assembling different types of image sensors on the sub-board, the power circuits on the main board may need to be accordingly changed and relocated to provide suitable operating voltage for the relocated image sensors. The relocation and disassembly may increase design complexity and layout difficulty of the main board.
Therefore, there is room for improvement within the art.
Many aspects of an exemplary power conversion circuit and internet protocol camera employing the same can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the exemplary power conversion circuit and internet protocol camera employing the same. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.
The SOC 222 is electrically located on the main board 220, and is capable of reading and processing application programs directing the IP camera 200 to output and provide video signals. The system power 224 is electrically located on the main board 220, and is electrically connected to the SOC 222. The system power 224 is capable of providing corresponding operating voltages for the electronic components on the main board 220 and the sub-board 240.
The sub-board 240 includes a photo detection unit 242 and a sub-power 244. The photo detection unit 242 can be a complementary metal oxide semiconductor (CMOS) sensor or a charge coupled device (CCD) sensor. The photo detection unit 242 is electrically connected to the SOC 222 and is operable for directly converting optical signals into corresponding digital signals to acquire, store, transmit, and process the video images.
The sub-power 224 is electrically connected to the photo detection unit 242, and provides operating voltage for the photo detection unit 242. The voltage of the sub-power 224 is accordingly changed with output voltage of the power conversion circuit 100.
The power conversion circuit 100 is electrically connected to the system power 224 and the sub-power 244, and is capable of receiving an output voltage from the system 224, and adjusting and converting the output voltage to provide a corresponding stable voltage for the sub-power 244. The power conversion circuit 100 includes a voltage conversion circuit 10, a divider circuit 20, and an analog to digital converter (ADC) 30.
Also referring to
The linear voltage regulator 12 includes an input port VIN, an output port VOUT, and a feedback port FB. The input port VIN is electrically connected to the system power 224 to receive direct current (DC), and the DC is output to the output port VOUT after direct current to direct current (DC/DC) conversion. The feedback port FB is operable for receiving feedback voltage Vfb from the divider circuit 20.
The input port VIN is further electrically connected to ground through the first capacitor C1, and the output port VOUT is further electrically connected to the ground through the second capacitor C2. The first capacitor C1 and the second capacitor C2 are capable of filtering noise to stabilize the input voltage of the input port VIN and the output voltage of the output port VOUT.
The divider circuit 20 is electrically positioned on the sub-board 240 and provides the feedback voltage Vfb for the linear voltage regulator 12. The divider circuit 20 includes a first divider resistance 22, a second divider resistance 24, and a third capacitor C3. In this exemplary embodiment, an end of the first divider resistance 22 is electrically connected to the sub-power 244, the ADC 30, the third capacitor C3 and the output port VOUT of the linear voltage regulator 12. Another end of the first divider resistance 22 is electrically connected to an end of the second divider resistance 24. The other end of the second divider resistance 24 is electrically connected to ground. The feedback port FB of the linear voltage regulator 12 is electrically connected between the first divider resistance 22 and the second divider resistance 24, forming a node A. The third capacitor C3 can be a filter capacitor and is electrically connected to ground.
Further referring to
In use, if the output voltage of the output port VOUT is set as V, the resistances of the first divider resistance 22 and the second divider resistance 24 are respectively set as R1 and R2. Accordingly, the feedback voltage Vfb of the feedback port FB is obtained by the following formula: Vfb=VR2/(R1+R2). The linear voltage regulator 12 compares the Vfb with the predetermined reference voltage Vref, and accordingly adjusts the output voltage V of the output port VOUT until the feedback voltage Vfb is substantially equal to the reference voltage Vref. The output voltage V of the output port VOUT then can be calculated by the following formula: V=Vfb*(1+R1/R2)=Vref*(1+R1/R2), where the Vref is a constant. Thus, the output voltage V can be obtained by correspondingly adjusting or changing the first divider resistance R1 and/or the second divider resistance R2, and is provided for the photo detection unit 242 as the operating voltage.
The first divider resistance 22 and the second divider resistance 24 can be slide rheostats, or passive components, such as capacitors and inductors.
Moreover, the sub-power 244 can be omitted, and the output port VOUT of the linear voltage regulator 12 directly and electrically connected to and providing operating voltage for the ADC 30 and the photo detection unit 242.
In summary, in the power conversion circuit 100 and the IP camera 200 as disclosed, the linear voltage regulator 12 outputs and provides operating voltages for the photo detection unit 242 by adjusting the first divider resistance 22 and/or the second divider resistance 24. Thus, there is no need to relocate the matchable circuits on the main board 220, optimizing ease of use, versatility, and universality of the main board 220.
It is to be understood, however, that even though numerous characteristics and advantages of the exemplary disclosure have been set forth in the foregoing description, together with details of the structure and function of the exemplary disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of exemplary disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 99130771 | Sep 2010 | TW | national |
