(1) Electric power conversion control circuit and LSI for electric power conversion control that can obtain the control accuracy equal with the case controlled according to reference signal by using low clock frequency, when the electric power is converted.
(2) Difference detecting circuit that can detect difference of two voltage signals as digital value of high resolution accuracy,
(3) Signal generation circuit for the pulse width control that can generate pulse width signal of high resolution accuracy corresponding to time concerned set value according to time given by integer value.
Digital LSI including the microprocessor is being used for the electric power conversion control circuit (in this detailed statement, it is said, “electric power conversion control circuit”) such as the DC/DC converter for the following reasons.
(1)The influence by the temperature change is a little. (2) Various parameters can be set to programmable.
So far, a electric power conversion control circuit is known. This electric power conversion control circuit replaces the difference between output voltage EO and the reference voltage EREF of the controlled object (target value voltage) with the time amount and detect it, and decides the duty of the control signal (rectangular wave) based on the time amount. This electric power conversion control circuit can control high accuracy by detecting the time amount by using the clock generator of the frequency of about 50 MHz or more.
Therefore, the clock generator with a high price is necessary to be controlled by the frequency of 50 MHz or more.
The purpose of the present invention is to offer electric power conversion control circuit and LSI for the electric power conversion control that can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.
Other purpose of this invention is to offer difference detection circuit that can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.
Other purpose of this invention is to offer pulse width control signal generation circuit can obtain detection accuracy equal with control according to reference signal with high clock frequency by using standard clock signal with low frequency.
The present invention characterizes below.
(1) The electric power conversion control circuit that generates control signals corresponding to on-time (on period) of each switch element, comprising,
the first reference timing generation circuit that the first reference signal,
the time amount signal generation circuit that inputs the reference voltage and output voltage of power conversion circuit and generates the time amount signal corresponding to difference between standard said reference, and said output voltage synchronizing with said the first timing signal,
the phase shift signal generation circuit that inputs the reference clock signal, and generates the group that consists of n phase shift signals that the phase delays one by one by [one cycle of the reference clock signal]/n,
the count circuit that inputs n phase shift signals, counts these pulse numbers respectively synchronizing with the first reference timing signal, and outputs n count-values digitally when amount of signal of time is active,
the digital addition circuit that inputs said n count-values, adds these values, and outputs this adding value as a value corresponding to said time amount signal,
the switch element on-time deciding circuit that inputs said adding value, decides said on-time, and outputs as the integer value,
the second timing generation circuit that generates the second reference timing signal,
the control signal generation circuit that inputs said n phase shift signals synchronizing with said the second reference timing signal, generates the control signal of accuracy n time the reference clock signal corresponding to said on-time.
(2) The electric power conversion control circuit of (1) wherein, said phase shift signal generation circuit consists of the delay (n-1) circuits, and each delay circuit delays the phase one by one by [one cycle of the reference clock signal]/n, and generates said phase shift signal.
(3) The electric power conversion control circuit of (1) or (2), wherein, said count circuits have,
n AND-gates that input the said time amount signal input to the first terminal and said phase shift signal input to the second terminal, and output these logical product,
n counters that count the output pulse from said n AND gate respectively, and output each count value digitally.
(4) The electric power conversion control circuit of (1), (2) or (3), wherein, said control signal generation circuit has,
the distribute circuit that distributes said on-time value N2 n to integers N21, N22, N23, . . . , N2N,
time signal generation circuit that inputs a reference voltage and the output voltage of the electric power conversion circuit, and generates time amount signal corresponding to difference of said output voltage to said reference voltage synchronizing with said the first reference timing signal, so that the following requirement is met
N
21
+N
22
+. . . +N
2n
=N
2
N
21
≧N
22
≧. . . ≧N
2n
n counters that output the pulses of number corresponding to value that is preset for the phase to delay [one cycle of the reference clock signal]/n one by one,
the pulse synthesis circuit that synthesizes the output pulses of said counters, and outputs the synthesized signal as the control signal.
(5) The electric power conversion control circuit of (1), (2), (3), or 4, wherein, said electric power conversion circuit is the DC/DC converter.
(6). LSI for electric power conversion control that is packaged from the electric power conversion control circuit of (1), (2), (3), 4, or 5.
(7) The difference detecting circuit, comprising,
the reference timing generation circuit that generates the reference signal,
the time amount signal generation circuit that inputs voltage signals, and generates said output voltage synchronizing with said reference timing signal,
the phase shift signal generation circuit that inputs the reference clock signal, and generates the group that consists of n phase shift signals that the phase delays one by one by [one cycle of the reference clock signal]/n,
the count circuit that inputs n phase shift signals, counts these pulse numbers respectively synchronizing with the reference timing signal, and outputs n count-values digitally when amount of signal of time is active,
the digital addition circuit that inputs said n count-values, adds these values, and outputs this adding value as a value corresponding to said time amount signal.
(8) The pulse width control signal generation circuit, comprising, the reference timing generation circuit that the reference signal, the time amount signal generation circuit that inputs voltage signals, and generates said output voltage synchronizing with said reference timing signal,
the control signal generation circuit that inputs a time set value as an integral value, inputs n phase shift signals based on said reference clock signal synchronizing with the above-mentioned standard timing signal, and inputs said n phase shift signals synchronizing with said the second reference timing signal, generates the control signal of accuracy n time the reference clock signal corresponding to said time set value.
FIGS. 10(A),(B),(C) are the diagrams that show another embodiment for improving the high accuracy and the speed-up.
By using the electric power conversion control circuit and LSI for the electric power conversion control of the present invention, when the electric power is converted the control, the accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.
By using the difference detecting circuit of the present invention, the detection accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.
By using the pulse width control signal generation circuit of the present invention, the control accuracy equal with the control according to a reference signal with a high clock frequency can be obtained from the reference clock signal with low frequency.
The electric power conversion control circuit 1 is packaged in LSI for the electric power conversion control, and generates control signal S5 corresponding to on-time TON. The control signal S5 generated by the electric power conversion control circuit 1 is sent to the drive circuit 120, and the drive circuit 120 sends the driving signal DRV to the electric power conversion circuit 100.
In this embodiment the electric power conversion circuit 100 is possible to apply to the electric power conversion circuit output as direct current. The circuit 100 can be apply to the DC/DC converter typically, though the circuit 100 can be apply to AC/DC converter too.
The electric power conversion control circuit 1 has the timing generation circuit 11, the time amount circuit signal generation circuit 12, the phase-shift signal generation circuit 13, the counter circuit 14, the digital addition circuit 15, the switch element on-time decision circuit 16, and the control signal generation circuit 17.
The timing generation circuit 11 generates the reference timing signal S1. The cycle of on-off of the electric power conversion circuit 100 is decided depending on the reference timing signal S1.
The time amount signal generation circuit 12 inputs the reference voltage EREF and the voltage output EO of the electric power conversion circuit 100, and generates the time amount signal S3 corresponding to the difference of the output voltage EO to reference voltage EREF synchronizing with reference timing signal S1. The CR Circuits of two sets (Refer to
The phase-shift signal generation circuit 13 inputs the reference clock signal S0. And, the phase-shift signal generation circuit 13 generates the set of n phase-shift signal S41, S42, . . . , S4n that the phase delays only [one cycle T0 of the reference clock signal S0]/n one by one from the reference clock signal S0.
The counter circuit 14 inputs n phase-shift signal S41, S42, . . . , S4n when the time amount signal S3 is active, counts the pulse numbers respectively synchronizing with the reference timing signal S1, and outputs n count-values N11, N12, . . . , N1n digitally.
The digital addition circuit 15 inputs n count-values N11, N12, . . . , N1n, adds these values, and outputs the adding value ADD digitally as a value that corresponds to the time amount signal S3.
The switch element on-time decision circuit 16 inputs the adding value ADD, decides the on-time TON of the switch element (not shown in the figure) of the electric power conversion circuit 100, and outputs TON digitally as integral value N2.
The control signal generation circuit 17 inputs n phase-shift signal S41, S42, . . . , S4n synchronizing with reference timing signal S1, generates the control signal S5 n times accuracy of the reference clock signal S0 corresponding to on-time TON.
The DC/DC converter 101 consists of the transistor Tr for switching, the inductor L, the diode D, and the capacitor C. The transistor Tr and the inductor L are connected with the series between the input terminal a1 and the output terminal b1 (input terminal a2 and output terminal b2 are connected to the ground GND). The diode D is connected between the terminal on the inductor L side of the transistor Tr and the ground GND. The capacitor C is connected between the output terminal b1 and b2. In
The electric power conversion control circuit 1 inputs the output voltage EO of the DC/DC converter 101, outputs the control signal S5 to drive circuit 120, and the drive circuit 120 sends driving signal to the transistor Tr of the DC/DC converter 101.
In
The timing generation circuit 21 generates the reference timing signal S1.
T the time amount signal generation circuit 22 inputs 2 voltage signal EA and EB, and generates the time amount signal S3 corresponding to the difference (EB−EA) synchronizing with reference timing signal S1.
The phase-shift signal generation circuit 23 inputs the reference clock signal S0, and generates the set of n phase-shift signal S41, S42, . . . , S4n that the phase delays only [one cycle T0 of the reference clock signal S0]/n one by one from the reference clock signal S0.
The counter circuit 24 inputs the time amount signal S3 and n phase-shift signals S41, S42, . . . , S4n when the time amount signal S3 is active, counts these pulse numbers synchronizing with the reference timing signal respectively, and outputs n count-values N11, N12, . . . , N4n digitally.
The digital adding circuit 25 inputs, adds n count-values N11, N12, . . . , N4n, and outputs this adding value digitally as a value corresponding to the time amount signal.
In
The timing generation circuit 31 generates the reference timing signal S1.
The phase-shift signal generation circuit 32 inputs the reference clock signal S0, and generates n phase-shift signals S41, S42, . . . , S4n that each phase delays one by one by [one cycle T0 of the reference clock signal S0]/n from the reference clock signal S0. Moreover, the phase-shift signal generation circuit 32 consists of (n-1) delay circuits. Each delay circuit delays the phase one by one by [one cycle T0 of the reference clock signal S0]/n, and generates the phase-shift signals S41, S42, . . . , S4n.
The control signal generation circuit 33 inputs a time set value as integral value N2, inputs n phase-shift signals S41, S42, . . . , S4n based on reference clock signal S0 synchronizing with the reference timing signal S1, and generates the pulse width control signal Sp (corresponding to the TON time) of accuracy n time the reference clock signal corresponding to the time setting value (integer N2).
The composition and the operation of the electric power conversion control circuit 1 mentioned above are explained by the circuit diagrams of
The counter 111 generates the reference timing signal S1 corresponding to the preset value (the digital value PS that is the setting value of the switching frequency). The on/off frequency of the control signal S5 is decided by the frequency of the reference timing signal S1 (100 kHz order). Above on/off frequency is generated by the control signal generation circuit 17.
The reference timing signal S1 is generated from the reference clock signal S0 described later. The reference timing signal S1 is sent to the transistor switch Tr1 of the voltage input circuit 121 and the transistor switch Tr2 of the voltage input circuit 122. The voltage input circuit 121 inputs the output voltage Eo, and the voltage input circuit 122 inputs the reference voltage EREF. The counter 111 generates The counter 111 composes timing generation circuit 11 of
The voltage input circuit 121 consists of the input resistance r1, the capacitor C1, the transistor switch Tr1, and the comparator Cmp1. The output voltage EO is given to one side terminal of the input resistance r1. The capacitor C1 is connected between the other terminal and the ground. The reference voltage input circuit 122 consists of the input resistance r2, the capacitor C2, the transistor switch Tr2, and the comparator Cmp2. The reference voltage EREF is given to one side terminal of the input resistance r2. The capacitor C2 connects between the other terminal of the input resistance r1 and the ground GND. The comparator Cmp2 inputs the threshold value voltage VTB. The reference timing signal is given to the transistor switch Tr1 and Tr2. Moreover, the output terminal of comparator Cmp1 and the output terminal of the comparator Cmp2 are connected to EXOR gate 123.
When the reference timing signal S1 turns off the transistor switch Tr1 and Tr2, as shown in
The input circuit 121 and the reference voltage input circuit 122 can be composed of the voltage controlled oscillator (VCO) that acts according to the timing of S1. The input voltage is higher, so the voltage controlled oscillator (VCO) outputs the first pulse earlier. Therefore, the VCO that the oscillation cycle is large can be operated as well as the above integration circuit. Moreover, the output of EXOR gate 123( time amount signal S3) outputs the time difference between the down edge of the signal S21 and the down edge of S22 as shown in
The signal S21 and S22 are input to the digital filter 161 described later, and the digital filter 161 detects a time relation of the down edge of signal S21 and the down edge of S22. The voltage input circuit 121, the reference voltage input circuit 122, and the EXOR gate 123 compose the circuit 12 of the time amount generation signal in
Three delay circuits 13(1), 13(2), 13(3) delay the phase one by one by [one cycle of the reference clock signal S0]/4 to the reference clock signal S0 (in
The output signal of the EXOR gate 123 (the time amount signal S3) is input to one side input terminal of the AND gate (And1, And2, And3, and And4), and the phase-shift signals (S41, S42, S43, S44) are input to the other input terminal of the AND gate (And1, And2, and And3, And4) respectively.
The AND gate (And1, And2, And3, and And4) outputs the logical product of these input signals by the pulse respectively.
The counter (parallel conversion type) 14(1), 14(2), 14(3), 14(4) counts the output pulses from the AND gate (And1, And2, And3, and And4) respectively and outputs the count values (N11, N12, N13, N14) as digital signal respectively.
In
The digital filter 161 inputs the adding value ADD, decides the on-time TON of the switch elements of the DC/DC converter 101 (refer to
Moreover ,digital filter 161 can preset the offset value, the gain, and the cutoff frequency, etc.
In addition, the digital filter 161 inputs the signal S21 and S22 as mentioned above, and judges the time relation of the down edge of S21 and the down edge of the signal S22 (that is, the output voltage EO of the electric power conversion circuit 100 is whether larger or smaller than the reference voltage EREF).
For instance, the output of digital filter 161 (integer value N2) is a value corresponding to the control quantity like
[A/(1+Sτ)]×(EREF−EO)
(A: constant, s: Laplace operator, τ: time constant)
The output of the digital filter 161 corresponds to the on-time of the next cycle of the reference timing signal S1. The digital filter 161 composes the switch element on-time decision circuit 16 in
The distribution circuit 171 distributes the on-time Ton input to four integers N21, N22, N23,N24.
The four integers N21, N22, N23 satisfy the following expression,
N
21
+N
22
+N
23
+N
24
=N
2
N
21
≧N
22
≧N
23
≧N
24
In the present embodiment, when N2 is 22 (N2=22) it becomes N21=6, N22=6, N23=5, and N24=5 in as shown in
Four counters 172(1), 172(2), 172(3), 172(4) are down counters, integer N21, N22, N23, and N24 are preset in each counter. When the pulses of the number preset are input, each counter outputs the pulses that the phase delays [one cycle of the reference clock signal S0]/4 one by one.
The pulse synthesis circuit 173(flip-flop register FF) is set by the reference timing signal S1, outputs the rising edge (up edge) of the control pulse S5. The pulse synthesis circuit 173 outputs the down edge of the control signal S5 by the last pulse that counter s(172(1), 172(2), 172(3), 172(4)) output.
The distribution circuit 171, the counter (172(1), 172(2), 17(3), 172(4)), and the pulse synthesis circuit 173 compose the control signal generation circuit 17 in
It explains the embodiment of the present invention more in detail as follows.
As shown in
In the said example, the voltage deviation will be detected once in one cycle of the on-off of the transistor switch (the digital numerical value NRM to control the current control circuit 3 is detected once). However, the numerical value NRM digital may be detected two or more times in one cycle Te of the first clock Se as shown in
In
Number | Date | Country | Kind |
---|---|---|---|
2006-044498 | Feb 2006 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/JP2007/053711 | 2/21/2007 | WO | 00 | 11/20/2008 |