POWER CONVERSION DEVICE

TECHNICAL FIELD

The present invention relates to a power conversion device.

BACKGROUND ART

A modular multilevel converter (which will be referred to as an MMC converter below) in which a plurality of unit converters (which will be referred to as converter cells below) are cascaded can readily address a high voltage by increasing converter cells. The modular multilevel converter has widely been applied to power transmission and distribution systems as a high-capacity static var compensator or an alternating-current (AC)-direct-current (DC) power conversion device for high-voltage DC power transmission. The converter cell includes a plurality of switching elements and a power storage element (which may be referred to as a capacitor). Even when a converter cell fails in the MMC converter, the MMC converter can continue operating by bypassing the failed converter cell.

PTL 1 describes an operation method without requiring adjustment of a modulation factor of each arm by adjusting the number of operating converter cells in each arm in accordance with the number of failures in an arm largest in number of failed converter cells and increasing a capacitor voltage.

CITATION LIST
Patent Literature

PTL 1: Japanese Patent Laying-Open No. 2017-143619

SUMMARY OF INVENTION
Technical Problem

PTL 1, however, does not consider a harmonic component in an arm current that increases after bypass of the failed converter cell.

An output voltage from a converter cell in the MMC converter contains a harmonic component such as a switching frequency component, an integer-order component thereof, and a sideband wave component thereof (which will simply be referred to as a harmonic component below), in addition to a frequency component included in an arm voltage command value such as a fundamental wave component on an AC output side (simply a fundamental wave component below) and a DC component. The MMC converter adopting phase shift pulse width modulation (PWM) cancels a harmonic component in an output voltage from each converter cell by equally shifting a PWM reference phase for each converter cell in each arm. A switching frequency of the output voltage from the arm can thus be made higher.

When a converter cell fails and the failed converter cell is bypassed, however, an output voltage from the failed converter cell becomes zero. Since an amount of shift of the PWM reference phase is thus no longer equal, the harmonic component in the output voltage from each converter cell cannot be canceled. Consequently, the harmonic component in the output voltage from each converter cell remains in the output voltage from the arm. Energy of the harmonic component is thus concentrated in some converter cells. Consequently, capacitor voltages of some converter cells deviate from a protection level and the MMC converter may stop operating for a protection purpose.

Therefore, an object of the present invention is to provide a power conversion device capable of suppressing a harmonic component in an output voltage from an arm that increases after bypass of a failed converter cell.

Solution to Problem

A power conversion device according to the present invention includes a power converter including an arm in which a plurality of converter cells are connected in series, each of the plurality of converter cells including at least two switching elements, a power storage element, and a pair of output terminals, and a control device to control voltages of the plurality of converter cells by phase shift PWM control using a carrier signal for each converter cell. The converter cell includes a switch to have the converter cell bypassed. When the control device senses failure of a converter cell within the arm, the control device has a failed converter cell within the arm bypassed and rectifies uneven intervals among phases of the carrier signals of a plurality of normal converter cells within the arm caused by failure of the converter cell.

Advantageous Effects of Invention

According to the present invention, a harmonic component in an arm current that increases after bypass of a failed converter cell can be suppressed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic configuration diagram of a power conversion device 1 in an embodiment.

FIGS. 2(a) and (b) is a diagram showing a configuration of a converter cell 7 that makes up a power converter 2.

FIG. 3 is a diagram showing an internal configuration of a control device 3 in a first embodiment.

FIG. 4 is a diagram showing a configuration of a basic controller 502.

FIG. 5 is a diagram showing a configuration of an arm controller 503.

FIG. 6 is a diagram showing a configuration of an individual cell controller 202.

FIG. 7 is a diagram showing a carrier reference phase θ1 before failure of a converter cell 7_2 and a carrier reference phase θ2 after failure of converter cell 7_2 in a first specific example in the first embodiment.

FIG. 8 is a diagram showing carrier reference phase θ1 before failure of a converter cell 7_3 and carrier reference phase θ2 after failure of converter cell 7_3 in a second specific example in the first embodiment.

FIG. 9 is a diagram showing variation in carrier signal in the first specific example in FIG. 7.

FIG. 10 is a diagram showing an exemplary hardware configuration of control device 3.

FIG. 11 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_2 and carrier reference phase θ2 after failure of converter cell 7_2 in a first specific example in a second embodiment.

FIG. 12 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_3 and carrier reference phase θ2 after failure of converter cell 7_3 in a second specific example in the second embodiment.

FIG. 13 is a diagram showing variation in carrier signal in the first specific example in FIG. 11.

FIG. 14 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_2 and carrier reference phase θ2 after failure of converter cell 7_2 in a first specific example in a third embodiment.

FIG. 15 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_3 and carrier reference phase θ2 after failure of converter cell 7_3 in a second specific example in the third embodiment.

FIG. 16 is a diagram showing variation in carrier signal in the first specific example in FIG. 14.

FIG. 17 is a diagram showing a configuration of control device 3 in a fourth embodiment.

FIG. 18 is a diagram showing a configuration of a cell balancing circulating current controller 610.

FIG. 19 is a diagram showing a configuration of an arm voltage command generator 601 in the fourth embodiment.

FIG. 20 is a diagram showing a configuration of control device 3 in a fifth embodiment.

FIG. 21 is a diagram showing a configuration of a power conversion device 1A in a sixth embodiment.

FIG. 22 is a diagram showing a configuration of a part of power conversion device 1A.

FIG. 23 is a diagram showing a configuration of a part of a power conversion device 1B.

FIG. 24 is a diagram showing a configuration of a basic controller 502A in a modification.

DESCRIPTION OF EMBODIMENTS

Embodiments will be described below with reference to the drawings.

First Embodiment

(Overall Configuration of Power Conversion Device)

FIG. 1 is a schematic configuration diagram of a power conversion device 1 in an embodiment. Referring to FIG. 1, power conversion device 1 is configured of a modular multilevel converter which includes multiple converter cells connected in series. Note that the “converter cell” is also called a “sub-module,” SM, or a “unit converter.” Power conversion device 1 converts power between a DC circuit 14 and an AC circuit 12. Power conversion device 1 includes a power converter 2 and a control device 3.

Power converter 2 includes multiple leg circuits 4u, 4v, 4w (will be described as a leg circuit 4 when referred to collectively or when referring to any leg circuit) which are connected in parallel between a positive DC terminal (i.e., a high-potential-side DC terminal) Np and a negative DC terminal (i.e., a low-potential-side DC terminal) Nn.

Leg circuit 4 is provided for each of multiple phases constituting an alternating current. Leg circuit 4 is connected between AC circuit 12 and DC circuit 14, and converts power between the circuits. AC circuit 12 shown in FIG. 1 is a three-phase AC circuit which includes three leg circuits 4u, 4v, 4w corresponding to a U phase, a V phase, and a W phase, respectively.

AC input terminals Nu, Nv, Nw provided for respective leg circuits 4u, 4v, 4w are connected to AC circuit 12 via a transformer 13. AC circuit 12 is, for example, an AC power system which includes an AC power supply, etc. For ease of illustration, FIG. 1 does not show the connection between AC input terminals Nv, Nw and transformer 13.

High-potential-side DC terminal Np and low-potential-side DC terminal Nn, which are connected in common to each leg circuit 4, are connected to DC circuit 14. DC circuit 14 is, for example, a DC power system, including a DC power grid, or a DC terminal of other power conversion devices. In the latter case, a BTB (Back To Back) system for connecting different AC power systems having different rated frequencies is formed by coupling two power conversion devices.

AC input terminals Nu, Nv, Nw may be connected to AC circuit 12 via an interconnection reactor, instead of transformer 13 in FIG. 1. Furthermore, instead of AC input terminals Nu, Nv, Nw, a primary winding may be provided for each of leg circuits 4u, 4v, 4w, and leg circuits 4u, 4v, 4w may be connected to transformer 13 or an interconnection reactor in an AC manner via a secondary winding magnetically coupled to the primary winding. In this case, the primary winding may be reactors 8A, 8B described below. In other words, leg circuit 4 is electrically (i.e., a DC manner or an AC manner) connected to AC circuit 12 via the connector provided for each of leg circuits 4u, 4v, 4w, such as AC input terminals Nu, Nv, Nw or the above primary winding.

Leg circuit 4u includes an upper arm 5 from high-potential-side DC terminal Np to AC input terminal Nu, and a lower arm 6 from low-potential-side DC terminal Nn to AC input terminal Nu. AC input terminal Nu, which is the point of connection between upper arm 5 and lower arm 6, is connected to transformer 13. High-potential-side DC terminal Np and low-potential-side DC terminal Nn are connected to DC circuit 14. Leg circuits 4v, 4w have the same configuration as leg circuit 4u, and leg circuit 4u will thus be representatively described below.

Upper arm 5 includes multiple cascade-connected converter cells 7_1 to 7_Ncell and reactor 8A. Multiple converter cells 7 and reactor 8A are connected in series. Similarly, lower arm 6 includes multiple cascade-connected converter cells 7_1 to 7_Ncell and reactor 8B. Multiple converter cells 7 and reactor 8B are connected in series. In the description below, the number of converter cells 7 included in each of upper arm 5 and lower arm 6 is set to Ncell. Ncell is set to Ncell≥2. In the description below, converter cells 7_1 to 7_Ncell may also collectively be denoted as a converter cell 7. An index i to the converter cell is irrelevant to physical arrangement of the converter cell.

Reactor 8A may be inserted anywhere in upper arm 5 of leg circuit 4u. Reactor 8B may be inserted anywhere in lower arm 6 of leg circuit 4u. Multiple reactors 8A and multiple reactors 8B may be present. The reactors may have different inductance values. Furthermore, only reactor 8A of upper arm 5 may be provided, or only reactor 8B of lower arm 6 may be provided.

Reactors 8A, 8B are provided to prevent a rapid increase of a fault current in the event of a fault of AC circuit 12 or DC circuit 14, for example. However, reactors 8A, 8B having excessive inductance values result in reduced efficiency of power converter 2. Accordingly, preferably, all the switching elements of each converter cell 7 are stopped (turned off) as soon as possible in the event of a fault.

As detectors for measuring the electrical quantities (current, voltage, etc.) for use in the control, power conversion device 1 further includes an AC voltage detector 10, an AC current detector 16, DC voltage detectors 11A, 11B, and arm current detectors 9A, 9B. Arm current detectors 9A, 9B are provided for each leg circuit 4. Signals detected by these detectors are input to control device 3.

Note that, for ease of illustration, in FIG. 1, some of signal lines for the signals input from the detectors to control device 3 and signal lines for the signals input/output to/from control device 3 and each converter cell 7 are depicted collectively, but they are, in practice, provided for each detector and each converter cell 7. The signal lines may be provided separately for transmission and reception of the signals between each converter cell 7 and control device 3. For example, an optical fiber may be adopted as the signal line.

In the following, each detector is described in detail.

AC voltage detector 10 detects a U-phase AC voltage Vacu, a V-phase AC voltage Vacv, and a W-phase AC voltage Vacw of AC circuit 12. In the description below, Vacu, Vacv, and Vacw are collectively denoted as Vac.

AC current detector 16 detects a U-phase AC current Iacu, a V-phase AC current lacy, and a W-phase AC current Iacw of AC circuit 12. In the description below, Iacu, lacy, and Iacw are collectively denoted as Iac.

DC voltage detector 11A detects a DC voltage Vdcp of high-potential-side DC terminal Np connected to DC circuit 14. DC voltage detector 11B detects a DC voltage Vdcn of low-potential-side DC terminal Nn connected to DC circuit 14. A difference between DC voltage Vdcp and DC voltage Vdcn is defined as a DC voltage Vdc.

Arm current detectors 9A and 9B, included in leg circuit 4u for U phase, respectively detect an upper arm current Ipu flowing through upper arm 5 and a lower arm current Inu flowing through lower arm 6. Arm current detectors 9A and 9B, included in leg circuit 4v for V phase, detect an upper arm current Ipv and a lower arm current Inv, respectively. Arm current detectors 9A and 9B, included in leg circuit 4w for W phase, detect an upper arm current Ipw and a lower arm current Inw, respectively. In the description below, upper arm currents Ipu, Ipv, and Ipw are collectively denoted as an upper arm current Iarmp, lower arm currents Inu, Inv, and Inw are collectively denoted as a lower arm current Iarmn, and upper arm current Iarmp and lower arm current Iarmn are collectively denoted as Iarm.

(Converter Cell)

FIGS. 2(a) and (b) is a diagram showing a configuration of converter cell 7 that makes up power converter 2.

Converter cell 7 shown in FIG. 2(a) has a circuit configuration called a half-bridge configuration. This converter cell 7 includes a serial body formed by connecting two switching elements 31p and 31n to each other in series, a power storage element 32, a bypass switch 34, and a voltage detector 33. The serial body and power storage element 32 are connected in parallel.

Opposing terminals of switching element 31n are defined as input and output terminals P1 and P2. A voltage across ends of power storage element 32 and a zero voltage are provided as a result of switching operations by switching elements 31p and 31n. For example, when switching element 31p is turned on and switching element 31n is turned off, the voltage across ends of power storage element 32 is provided. When switching element 31p is turned off and switching element 31n is turned on, the zero voltage is provided.

Bypass switch 34 is connected between input and output terminals P1 and P2. By turning on bypass switch 34, converter cell 7 is short-circuited. As converter cell 7 is short-circuited, switching elements 31p and 31n included in converter cell 7 are protected against an overcurrent produced at the time of a fault.

Voltage detector 33 detects a voltage Vc across ends of power storage element 32.

Converter cell 7 shown in FIG. 2(b) has a circuit configuration called a full-bridge configuration. This converter cell 7 includes a first serial body formed by connecting two switching elements 31p1 and 31n1 to each other in series, a second serial body formed by connecting two switching elements 31p2 and 31n2 to each other in series, power storage element 32, bypass switch 34, and voltage detector 33. The first serial body, the second serial body, and power storage element 32 are connected in parallel.

A point intermediate between switching element 31p1 and switching element 31n1 and a point intermediate between switching element 31p2 and switching element 31n2 are defined as input and output terminals P1 and P2 of converter cell 7. The voltage across ends of power storage element 32 or the zero voltage is provided as a result of switching operations by switching elements 31p1, 31n1, 31p2, and 31n2.

Bypass switch 34 is connected between input and output terminals P1 and P2. By turning on bypass switch 34, converter cell 7 is short-circuited. As converter cell 7 is short-circuited, each element included in converter cell 7 is protected against an overcurrent produced at the time of a fault.

Voltage detector 33 detects voltage Vc across ends of power storage element 32.

In FIGS. 2(a) and (b), switching elements 31p, 31n, 31p1, 31n1, 31p2, and 31n2 are configured, for example, by connection of a freewheeling diode (FWD) in anti-parallel to a self-arc-extinguishing semiconductor switching element such as an insulated gate bipolar transistor (IGBT) and a gate commutated turn-off (GCT) thyristor.

In FIGS. 2(a) and (b), a capacitor such as a film capacitor is mainly employed as power storage element 32. Power storage element 32 may be referred to as a capacitor in the description below.

An example in which converter cell 7 has the half-bridge cell configuration shown in FIG. 2(a), a semiconductor switching element is employed as the switching element, and a capacitor is employed as the power storage element will be described below by way of example. Converter cell 7 included in power converter 2, however, may have the full-bridge configuration shown in FIG. 2(b). A converter cell in a configuration other than the configuration shown above, such as a converter cell to which a circuit configuration called a clamped double cell is applied, may be employed, and the switching element and the power storage element are not limited to the above either.

(Control Device)

FIG. 3 is a diagram showing an internal configuration of control device 3 in a first embodiment.

Control device 3 includes a switching controller 501 and a bypass controller 510.

Switching controller 501 controls on and off of switching elements 31p and 31n in converter cell 7.

When bypass controller 510 senses failure of converter cell 7 within the arm, it protects failed converter cell 7 within the arm against an overcurrent by turning on bypass switch 34 in failed converter cell 7.

Switching controller 501 includes a U-phase basic controller 502U, a U-phase upper arm controller 503UP, a U-phase lower arm controller 503UN, a V-phase basic controller 502V, a V-phase upper arm controller 503VP, a V-phase lower arm controller 503VN, a W-phase basic controller 502W, a W-phase upper arm controller 503WP, and a W-phase lower arm controller 503WN.

In the description below, U-phase basic controller 502U, V-phase basic controller 502V, and W-phase basic controller 502W are collectively denoted as a basic controller 502. U-phase upper arm controller 503UP, U-phase lower arm controller 503UN, V-phase upper arm controller 503VP, V-phase lower arm controller 503VN, W-phase upper arm controller 503WP, and W-phase lower arm controller 503WN are collectively denoted as an arm controller 503.

FIG. 4 is a diagram showing a configuration of basic controller 502.

Basic controller 502 includes an arm voltage command generator 601 and a capacitor voltage command generator 602.

Arm voltage command generator 601 calculates an arm voltage command value krefp for the upper arm and an arm voltage command value krefn for the lower arm. In the description below, krefp and krefn are collectively denoted as kref.

Capacitor voltage command generator 602 calculates a capacitor command voltage value Vcrefp for capacitors 32 in N converter cells 7 included in the upper arm. Capacitor voltage command generator 602 calculates a capacitor command voltage value Vcrefn for capacitors 32 in N converter cells 7 included in the lower arm. For example, an average voltage of capacitors 32 in converter cells 7 in the upper arm is defined as capacitor command voltage value Vcrefp and an average voltage of capacitors 32 in converter cells 7 in the lower arm is defined as capacitor command voltage value Vcrefn. In the description below, Vcrefp and Vcrefn are collectively denoted as Vcref.

Arm voltage command generator 601 includes an AC current controller 603, a circulating current calculator 604, a circulating current controller 605, and a command distributor 606.

AC current controller 603 calculates an AC control command value Vcp such that a difference between detected AC current Iac and a set AC current command value Iacref is set to 0.

Circulating current calculator 604 calculates a circulating current Iz that flows through one leg circuit 4 based on arm current Iarmp in the upper arm and arm current Iarmn in the lower arm. The circulating current is a current that circulates among a plurality of leg circuits 4. For example, circulating current Iz that flows through one leg circuit 4 can be calculated in accordance with an expression below.

Idc=(Ipu+Ipv+Ipw+Inu+Inv+Inw)/2 (1)

Iz=(Iarmp+Iarmn)/2−Idc/3 (2)

Circulating current controller 605 calculates a circulation control command value Vzp for controlling circulating current Iz to follow a set circulating current command value Izref such as 0.

Command distributor 606 receives AC control command value Vcp, circulation control command value Vzp, a DC voltage command value Vdcref, a neutral point voltage Vsn, and AC voltage Vac. Since an AC side of power converter 2 is connected to AC circuit 12 with transformer 13 being interposed, neutral point voltage Vsn can be calculated based on a voltage of a DC power supply of DC circuit 14. DC voltage command value Vdcref may be provided under DC output control or may be set to a constant value.

Based on these inputs, command distributor 606 calculates voltages to be supplied by the upper arm and the lower arm. Command distributor 606 determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from respective calculated voltages.

Determined arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm serve as output voltage commands to control AC current Iac to follow AC current command value Iacref, to control circulating current Iz to follow circulating current command value Izref, to control DC voltage Vdc to follow DC voltage command value Vdcref, and to feedforward-control AC voltage Vac.

Basic controller 502 provides arm current Iarmp of the upper arm, arm current Iarmn of the lower arm, arm voltage command value krefp for the upper arm, arm voltage command value krefn for the lower arm, capacitor command voltage value Vcrefp for the upper arm, and capacitor command voltage value Vcrefn for the lower arm.

FIG. 5 is a diagram showing a configuration of arm controller 503.

When arm controller 503 senses failure of a converter cell 7_j among converter cells 7_1 to 7_Ncell, it rectifies uneven intervals among phases of carrier signals of normal converter cells 7_i (i=1 to j−1 and j+1 to Ncell) within the arm caused by failure of failed converter cell 7_j.

Arm controller 503 includes Ncell individual cell controllers 202_1 to 202_Ncell and a carrier signal generator 203. In the description below, individual cell controllers 202_1 to 202_Ncell may also collectively be denoted as an individual cell controller 202.

Individual cell controller 202_i individually controls corresponding converter cell 7_i. Individual cell controller 202_i receives arm voltage command value kref, arm current Iarm, and capacitor command voltage value Vcref from basic controller 502. Individual cell controller 202_i receives a capacitor voltage Vc and cell normality determination signal cn from corresponding converter cell 7_i. The cell normality determination signal is set to “1” when converter cell 7 is normal, and the cell normality determination signal is set to “0” when converter cell 7 has failed. Individual cell controller 202_i receives a carrier signal CRi from carrier signal generator 203. Individual cell controller 202_i generates a gate signal ga for corresponding converter cell 7_i and provides the gate signal to corresponding converter cell 7_i.

Before failure of any converter cell 7 within the arm, carrier signal generator 203 sets reference phases of a plurality of carrier signals CR(i) (which may also be referred to as a carrier reference phase below) at intervals calculated by division of 360 degrees by the number Ncell of converter cells 7_i within the arm. The reference phase of carrier signal CR(i) refers to a difference between a phase of carrier signal CR(i) and a phase defined as the reference. The phase of a carrier signal CR(0) can be adopted as the phase to be defined as the reference.

Carrier signal generator 203 generates carrier signals CR(1) to CR(Ncell) each having the set carrier reference phase. Thus, a harmonic component in an output voltage from each converter cell 7 within the arm can be canceled and an equivalent switching frequency of the output voltage from one arm can be high.

It is assumed that any converter cell 7 within the arm fails and the failed converter cell is referred to as a failed converter cell 7_j. When the output voltage from failed converter cell 7_j becomes zero, the harmonic component in the output voltage from each converter cell 7 within the arm cannot be canceled. Consequently, the harmonic component in the output voltage from each converter cell 7 remains in the output voltage from the arm.

Therefore, in the present embodiment, carrier signal generator 203 rectifies uneven intervals among the carrier reference phases of the plurality of normal converter cells within the arm after failure of any converter cell 7 within the arm. Intervals among the plurality of carrier reference phases before failure of converter cell 7_j are calculated as 360°/Ncell (=ϕ). Failure of converter cell 7_j, however, leads to a difference of 2ϕ between the carrier reference phase immediately preceding the carrier reference phase of failed converter cell 7_j and the carrier reference phase immediately following the carrier reference phase of failed converter cell 7_j. Rectification of uneven intervals among the carrier reference phases of the plurality of normal converter cells within the arm means setting of the intervals among all carrier reference phases within the arm to be smaller than 2ϕ.

Preferably, carrier signal generator 203 sets the reference phases of the plurality of carrier signals at intervals calculated by division of 360 degrees by the number (Ncell−1) of normal converter cells 7_i within the arm. Carrier signal generator 203 sets again the carrier reference phases of the normal converter cells without performing a gate blocking operation to stop a switching operation by power converter 2. Carrier signal generator 203 generates carrier signals CR(1) to CR(j−1) and CR(j+1) to CR(Ncell) having the carrier reference phases set again.

FIG. 6 is a diagram showing a configuration of individual cell controller 202.

Individual cell controller 202 includes an individual cell balance controller 2021, an adder 2051, a PWM modulator 2022, and a signal switch 2023.

Individual cell balance controller 2021 provides an individual cell balance control output dkrefc such that capacitor voltage Vc matches with capacitor command voltage value Vcref based on capacitor command voltage value Vcref, capacitor voltage Vc of corresponding converter cell 7, and arm current Iarm. For example, individual cell balance controller 2021 can generate individual cell balance control output dkrefc based on a result of multiplication of a difference between Vcref and Vc by a gain K.

Adder 2051 adds arm voltage command value kref and individual cell balance control output dkrefc provided from individual cell balance controller 2021. A result of addition is provided as cell voltage command value krefc.

PWM modulator 2022 provides a PWM modulated signal by modulating cell voltage command value krefc and carrier signal CR(i) in accordance with phase shift PWM. PWM modulator 2022 performs modulation depending on a configuration of converter cell 7. Depending on the configuration of converter cell 7, the number n of provided PWM modulated signals also increases or decreases. For example, in the case of a half-bridge cell, n is set to n=2, and in the case of a full-bridge cell, n is set to n=4.

Signal switch 2023 receives the PWM modulated signal and a zero signal representing a zero voltage. Signal switch 2023 provides a signal selected depending on cell normality determination signal cn. When converter cell 7_i is normal, cell normality determination signal cn is set to “1” and the PWM modulated signal is provided. When converter cell 7_i fails, cell normality determination signal cn is set to “0” and the zero signal is provided. The signal provided from signal switch 2023 is sent to a gate driver for switching elements 31p and 31n in corresponding converter cell 7_i as gate signal ga to control switching of switching elements 31p and 31n in corresponding converter cell 7_i.

A method of setting of the carrier reference phase by carrier signal generator 203 will be described further in detail below.

In varying the carrier reference phase without gate blocking of power converter 2, it is important to lessen influence of variation in carrier reference phase. In the present embodiment, an amount of variation in carrier reference phase is minimized by setting an optimization problem and minimizing a cost function.

The carrier reference phase of converter cell 7_i (i=1 to Ncell) before occurrence of failure of the converter cell within the arm is denoted as θ1(i).

Carrier signal generator 203 sets carrier reference phase θ1(i) of converter cell 7_i (i=1 to Ncell) before occurrence of failure of converter cell 7_j within the arm as below.

θ1(i)=360×(i−1)/Ncell (1)

The carrier reference phase of converter cell 7_i (i=1 to j−1 and j+1 to Ncell) after failure of converter cell 7_j within the arm is denoted as θ2(i) and offset of the carrier reference phase is denoted as Of. Carrier signal generator 203 sets carrier reference phase θ2(i) of normal converter cell 7_i (i=1 to j−1 and j+1 to Ncell) after failure of converter cell 7_j within the arm as below.

θ2(i)=360×(i−1)/(Ncell−1)+θf(i<j) (2)

θ2(i)=360×(i−2)/(Ncell−1)+θf(i>j) (3)

An amount of variation in carrier reference phase of normal converter cell 7_i (i=1 to j−1 and j+1 to Ncell) before and after occurrence of failure of converter cell 7_j within the arm is denoted as Δθ(i). Δθ(i) is expressed as below.

Δθ(i)=θ2(i)−θ1(i)(i≠j) (4)

Carrier signal generator 203 minimizes a maximum value of absolute values of amounts of variation in carrier reference phases of the plurality of normal converter cells. In the first embodiment, the optimization problem is set as below, by further setting a condition of −180<θf≤180.

min{max(|Δθ(i)|)|, 1≤i≤Ncell, −180<θf≤180} (5)

In an optimal solution to the optimization problem above, for example, an absolute value |Δθ(j+1)| of the amount of variation in carrier reference phase of normal converter cell 7_j+1 on one adjacent side of failed converter cell 7_j and an absolute value |Δθ(j−1)| of the amount of variation in carrier reference phase of normal converter cell 7_j−1 on the other adjacent side of failed converter cell 7j are equal to each other.

By solving the optimization problem above, offset θf of the carrier reference phase is expressed as below.

θf=180×(Ncell−2×j+2)/(Ncell×(Ncell−1)) (6)

Carrier signal generator 203 calculates carrier reference phase θ2(i) of normal converter cell 7_i (i=1 to j−1 and j+1 to Ncell) after failure of converter cell 7_j within the arm by substituting offset θf of the carrier reference phase in the expression (6) into the expressions (2) and (3). Consequently, carrier signal generator 203 varies the carrier reference phase of normal converter cell 7_i as below. Carrier signal generator 203 varies to delay the reference phase advanced relative to carrier reference phase θ1(j) of failed converter cell 7_j, among carrier reference phases θ(i) of the plurality of normal converter cells 7_i. Carrier signal generator 203 varies to advance the reference phase delayed relative to carrier reference phase θ1(j) of failed converter cell 7_j, among carrier reference phases θ(i) of the plurality of normal converter cells 7_i.

More specifically, carrier reference phase θ2(i) has characteristics below.

A phase different by 180° from θ1(j) is referred to as a phase θ*.

When Ncell is an even number, phase θ* matches with any of carrier reference phases θ1(i) (i=1 to Ncell). The phase matching with phase θ* is defined as a carrier reference θ1(k).

Carrier reference phase θ1(k) is not varied, that is, a condition of θ2(k)=θ1(k) is satisfied. When phase θ* is set to a value delayed by 180° relative to θ1(j), carrier reference phase θ2 is obtained by varying (Ncell−2)/2 carrier reference phases θ1 advanced relative to θ* (closer to θ1(j)) to advance (to bring them closer to θ1(j)). When phase θ* is set to a value advanced by 180° relative to θ1(j), carrier reference phase θ2 is obtained by varying (Ncell−2)/2 carrier reference phases θ1 delayed relative to θ* (closer to θ1(j)) to delay (to bring them closer to θ1(j)).

When Ncell is an odd number, on the other hand, phase θ* matches with none of carrier reference phases θ(i) (i=1 to Ncell).

When phase θ* is set to a value delayed by 180° relative to θ1(j), carrier reference phase θ2 is obtained by varying (Ncell−1)/2 carrier reference phases θ1 advanced relative to θ* (closer to θ1(j)) to advance (to bring them closer to θ1(j)). When phase θ* is set to a value advanced by 180° relative to θ1(j), carrier reference phase θ2 is obtained by varying (Ncell−1)/2 carrier reference phases θ1 delayed relative to θ* (closer to θ1(j)) to delay (to bring them closer to θ1(j)).

When the expression (7) is satisfied for two phases θx and θy, phase θy is assumed as a phase obtained by varying phase θx to delay, and when the expression (8) is satisfied, phase θy is assumed as a phase obtained by varying phase θx to advance.

θx<θy<(θx+180°) (7)

(θx−180°)<θy<θx (8)

First Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=4 and converter cell 7_2 within the arm fails will be described.

FIG. 7 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_2 and carrier reference phase θ2 after failure of converter cell 7_2 in a first specific example in the first embodiment.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=90°, θ1(3)=180°, and θ1(4)=270° is set. Furthermore, based on the expression (6), a condition of θf=30° is set. By substituting θf=30° into the expressions (2) and (3), a condition of θ2(1)=30°, θ2(3)=150°, and θ2(4)=270° is set.

Phase θ* different by 180° from carrier reference phase θ1(2))(=90° before failure of converter cell 7_2 is 270° (=θ1(4)). Carrier reference phase θ1(4) before failure of converter cell 7_2 becomes θ2(4) without being varied by failure of converter cell 7_2. Carrier reference phase θ1(1) before failure of converter cell 7_2 becomes θ2(1) as being varied in a direction of delay due to failure of converter cell 7_2. Carrier reference phase θ1(3) before failure of converter cell 7_2 becomes θ2(3) as being varied in a direction of advance due to failure of converter cell 7_2.

Second Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=9 and converter cell 7_3 within the arm fails will be described.

FIG. 8 is a diagram showing carrier reference phase θ1 before failure of converter cell 7_3 and carrier reference phase θ2 after failure of converter cell 7_3 in a second specific example in the first embodiment.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=40°, θ1(3)=80°, θ1(4)=120°, θ1(5)=160°, θ1(6)=200°, θ1(7)=240°, θ1(8)=280°, and θ1(9)=320° is set. Furthermore, based on the expression (6), a condition of θf=12.5° is set. By substituting θf=12.5° into the expressions (2) and (3), a condition of θ2(1)=12.5°, θ2(2)=57.5°, θ2(4)=102.5°, θ2(5)=147.5°, θ2(6)=192.5°, θ2(7)=237.5°, θ2(8)=282.5°, and θ2(9)=327.5° is set.

Phase θ* different by 180° from carrier reference phase θ1(3))(=80° of converter cell 7_3 before failure of converter cell 7_3 is 220°. Carrier reference phases θ1(1), θ1(2), θ1(8), and θ1(9) before failure of converter cell 7_3 become θ2(1), θ2(2), θ2(8), and θ2(9) as being varied in the direction of delay due to failure of converter cell 7_3. Carrier reference phases θ1(4), θ1(5), θ1(6), and θ1(7) before failure of converter cell 7_3 become θ2(4), θ2(5), θ2(6), and θ2(7) as being varied in a direction of advance due to failure of converter cell 73.

FIG. 9 is a diagram showing variation in carrier signal in the first specific example in FIG. 7.

Carrier signals of converter cells 7_1, 7_2, 7_3, and 7_4 before failure of converter cell 7_2 are denoted as CR(1), CR(2), CR(3), and CR(4), respectively. Carrier signals of converter cells 7_1, 7_3, and 7_4 after failure of converter cell 7_2 are denoted as CR(1)′, CR(3)′, and CR(4)′, respectively.

According to the first specific example, the carrier reference phase of carrier signal CR(4) is not varied by failure of converter cell 7_2. The carrier reference phase of carrier signal CR(1) is varied in the direction of delay. The carrier reference phase of carrier signal CR(3) is varied in the direction of advance.

Carrier signal generator 203 does not vary the carrier reference phase of carrier signal CR(4). Carrier signal generator 203 advances the carrier reference phase of carrier signal CR(3) immediately after intersection of carrier signal CR(3) with cell voltage command value krefc for converter cell 7_3. Carrier signal generator 203 delays the carrier reference phase of carrier signal CR(1) at the peak (the maximum value or the minimum value) of carrier signal CR(1).

By making such transition, the carrier signal can be prevented from intersecting with the cell voltage command value at an inappropriate position. Defective switching can thus be prevented from occurring.

(Hardware Configuration of Control Device 3)

FIG. 10 is a diagram showing an exemplary hardware configuration of control device 3.

Control device 3 is configured similarly to what is called a digital relay device. Control device 3 includes an analog-digital (AD) converter unit 530, an arithmetic processing unit 535, an input and output (JO) unit 543, and a settling-and-display unit 547.

In a stage preceding AD converter unit 530, a plurality of transformers (not shown) to convert input signals from arm current detectors 9A and 9B, AC voltage detector 10, AC current detector 16, DC voltage detector 11B, and voltage detector 33 to a voltage level suitable for signal processing within control device 3 may be provided.

AD converter unit 530 includes an analog filter 531 and an AD converter 532. Analog filter 531 is a low-pass filter provided to remove an aliasing error in AD conversion. AD converter 532 converts the signal that has passed through analog filter 531 into a digital value.

While FIG. 10 representatively shows only one channel as the input to AD converter unit 530, AD converter unit 530, in practice, has a multiple-input configuration to receive the signals from the respective detectors. Accordingly, more specifically, AD converter unit 530 includes multiple analog filters 531, and a multiplexer (not shown) for selecting signals having passed through analog filters 531.

Arithmetic processing unit 535 includes a central processing unit (CPU) 536, a memory 537, bus interfaces 538, 539, and a bus 540 connecting these components. CPU 536 controls the entire operation of control device 3. Memory 537 is used as a primary storage for CPU 536. Furthermore, by including a nonvolatile memory, such as a flash memory, memory 537 stores programs, and settings values for the signal processing.

Note that arithmetic processing unit 535 may be configured of any circuit that has computing functionality, and is not limited to the example of FIG. 10. For example, arithmetic processing unit 535 may include multiple CPUs. Instead of the processor such as CPU, arithmetic processing unit 535 may be configured of at least one ASIC (Application Specific Integrated Circuit), or at least one FPGA (Field Programmable Gate Array). Alternatively, arithmetic processing unit 535 may be configured of any combination of the processor, ASIC, and FPGA.

IO unit 543 includes a communication circuit 544, a digital input circuit 545, and a digital output circuit 546. Communication circuit 544 generates an optical signal to be provided to each converter cell 7. The signal provided from communication circuit 544 is transmitted to converter cell 7 through an optical repeater 555. Digital input circuit 545 and digital output circuit 546 are interface circuits for communication between CPU 536 and external devices. For example, digital output circuit 546 provides a trip signal to AC circuit 12.

Settling-and-display unit 547 includes a touch panel 548 for inputting settling values and for display. Touch panel 548 is an input/output interface which is a combination of a visual display, such as a liquid crystal panel, and an input device, such as a touchpad. Touch panel 548 is connected to bus 540 via bus interface 539.

Second Embodiment

As in the first embodiment, carrier signal generator 203 minimizes a maximum value of absolute values of amounts of variation in carrier reference phases of a plurality of normal converter cells. Furthermore, in a second embodiment, an optimization problem is set as below, by setting a condition of 0≤θf<360.

min{max(|Δθ(i)|)|, 1≤i≤Ncell, 0≤θf<360} (9)

According to an optimal solution to the optimization problem above, for example, amount of variation θ(j+1) in carrier reference phase of normal converter cell 7_j+1 immediately following failed converter cell 7_j is 0.

By solving the optimization problem above, offset θf of the carrier reference phase is expressed as below.

θf=360×(Ncell−j)/(Ncell×(Ncell−1)) (10)

Carrier signal generator 203 calculates carrier reference phases θ2(i) of a plurality of normal converter cells 7_i (i=1 to j−1 and j+1 to Ncell) after failure of converter cell 7_j within the arm by substituting offset θf of the carrier reference phase in the expression (10) into the expressions (2) and (3).

Consequently, carrier signal generator 203 varies the carrier reference phases of the plurality of normal converter cells 7_i as below. Carrier signal generator 203 sets the minimum value of amounts of variation Δθ(i) in carrier reference phases of the plurality of normal converter cells 7_i to 0. More specifically, carrier signal generator 203 does not vary reference phase θ1(j+1) immediately following carrier reference phase θ1(j) of failed converter cell 7_j among carrier reference phases θ1(i) of the plurality of normal converter cells 7_i. Carrier signal generator 203 delays the reference phases other than reference phase θ1(j+1) immediately following carrier reference phase θ1(j) of failed converter cell 7_j among carrier reference phases θ1(i) of the plurality of normal converter cells 7_i.

More specifically, carrier reference phase θ2(i) has characteristics below. Carrier reference phase θ1(j+1) is not varied, that is, a condition of θ2(j+1)=θ1(j+1) is satisfied. Carrier reference phases θ2(i) are obtained by varying (Ncell−2) carrier reference phases θ1(i) (i=1 to j−1 and j+2 to Ncell) to delay.

First Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=4 and converter cell 7_2 within the arm fails will be described.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=90°, θ1(3)=180°, and θ1(4)=270° is set. Furthermore, based on the expression (10), a condition of θf=60° is set. By substituting θf=60° into the expressions (2) and (3), a condition of θ2(1)=60°, θ2(3)=180°, and θ2(4)=300° is set.

Carrier reference phase θ1(3) before failure of converter cell 7_2 becomes θ2(3) without being varied by failure of converter cell 7_2. Carrier reference phases θ1(1) and θ1(4) before failure of converter cell 7_2 become θ2(1) and θ2(4) as being varied in the direction of delay due to failure of converter cell 7_2.

Second Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=9 and converter cell 73 within the arm fails will be described.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=40°, θ1(3)=80°, θ1(4)=120°, θ1(5)=160°, θ1(6)=200°, θ1(7)=240°, θ1(8)=280°, and θ1(9)=320° is set. Furthermore, based on the expression (10), a condition of θf=30° is set. By substituting θf=30° into the expressions (2) and (3), a condition of θ2(1)=30°, θ2(2)=75°, θ2(4)=120°, θ2(5)=165°, θ2(6)=210°, θ2(7)=255°, θ2(8)=300°, and θ2(9)=345° is set.

Carrier reference phase θ1(4) of converter cell 7_4 before failure of converter cell 7_3 is not varied by failure of converter cell 7_3, that is, a condition of θ2(4)=θ1(4) is satisfied. Carrier reference phases θ1(1), θ1(2), θ1(5), θ1(6), θ1(7), θ1(8), and θ1(9) before failure of converter cell 7_3 become θ2(1), θ2(2), θ2(5), θ2(6), θ2(7), θ2(8), and θ2(9) varied in the direction of delay due to failure of converter cell 7_3.

FIG. 13 is a diagram showing variation in carrier signal in the first specific example in FIG. 11.

Carrier signals of converter cells 7_1, 7_2, 7_3, and 7_4 before failure of converter cell 7_3 are denoted as CR(1), CR(2), CR(3), and CR(4), respectively. Carrier signals of converter cells 7_1, 7_3, and 7_4 after failure of converter cell 7_2 are denoted as CR(1)′, CR(3)′, and CR(4)′, respectively.

According to the first specific example, the carrier reference phase of carrier signal CR(3) is not varied by failure of converter cell 7_2. The carrier reference phases of carrier signals CR(1) and CR(4) are varied in the direction of delay.

Carrier signal generator 203 does not vary the carrier reference phase of carrier signal CR(3). Carrier signal generator 203 delays the carrier reference phases of carrier signals CR(1) and CR(4) at the peak (the maximum value or the minimum value) of carrier signals CR(1) and CR(4).

In the present embodiment, need for control for detecting timing at which the cell voltage command value for the normal converter cell intersects with the carrier signal of the normal converter cell for varying the carrier reference phase can be obviated.

Third Embodiment

As in the first embodiment, carrier signal generator 203 minimizes a maximum value of absolute values of amounts of variation in carrier reference phases of a plurality of normal converter cells. Furthermore, in a third embodiment, an optimization problem is set as below, by setting a condition of −360<θf≤0.

min{max(|Δθ(i)|)|, 1≤i≤Ncell, −360<θf≤0} (11)

According to an optimal solution to the optimization problem above, for example, amount of variation θ(j−1) in carrier reference phase of normal converter cell 7_j−1 immediately preceding failed converter cell 7_j is 0.

By solving the optimization problem above, offset θf of the carrier reference phase is expressed as below.

(j=1)θf=360/(Ncell×(Ncell−1)) (12-1)

(j>1)θf=360×(j−2)/(Ncell×(Ncell−1)) (12-2)

Consequently, carrier signal generator 203 varies carrier reference phases θ1(i) of the plurality of normal converter cells 7_i as below. Carrier signal generator 203 sets the maximum value of amounts of variation Δθ(i) in carrier reference phases of the plurality of normal converter cells 7_i to 0. More specifically, carrier signal generator 203 does not vary reference phase θ1(j−1) immediately preceding carrier reference phase θ1(j) of failed converter cell 7_j among carrier reference phases θ1(i) of the plurality of normal converter cells 7_i. Carrier signal generator 203 advances the reference phases other than reference phase θ1(j−1) immediately preceding carrier reference phase θ1(j) of failed converter cell 7_j among carrier reference phases θ1(i) of the plurality of normal converter cells 7_i.

More specifically, carrier reference phase θ2(i) has characteristics below. Carrier reference phase θ1(j−1) is not varied, that is, a condition of θ2(j−1)=θ1(j−1) is satisfied. Carrier reference phases θ2(i) are obtained by varying (Ncell−2) carrier reference phases θ1(i) (i=1 to j−2 and j+1 to Ncell) to advance.

First Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=4 and converter cell 7_2 within the arm fails will be described.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=90°, θ1(3)=180°, and θ1(4)=270° is set. Furthermore, based on the expression (12), a condition of θf=0° is set. By substituting θf=0° into the expressions (2) and (3), a condition of θ2(1)=0°, θ2(3)=120°, and θ2(4)=240° is set.

Carrier reference phase θ1(1) before failure of converter cell 7_2 becomes θ2(1) without being varied by failure of converter cell 7_2. Carrier reference phases θ1(3) and θ1(4) before failure of converter cell 7_2 become θ2(3) and θ2(4) as being varied in the direction of advance due to failure of converter cell 7_2.

Second Specific Example

Carrier reference phases θ1 and θ2 when Ncell is set to Ncell=9 and converter cell 73 within the arm fails will be described.

Based on the expression (1), a condition of θ1(1)=0°, θ1(2)=40°, θ1(3)=80°, θ1(4)=120°, θ1(5)=160°, θ1(6)=200°, θ1(7)=240°, θ1(8)=280°, and θ1(9)=320° is set. Furthermore, based on the expression (12), a condition of θf=−5° is set. By substituting θf=−5° into the expressions (2) and (3), a condition of θ2(1)=)−5° (=355°, θ2(2)=40°, θ2(4)=85°, θ2(5)=130°, θ2(6)=175°, θ2(7)=220°, θ2(8)=265°, and θ2(9)=310° is set.

Carrier reference phase θ1(2) of converter cell 7_2 before failure of converter cell 7_3 is not varied by failure of converter cell 7_3, that is, a condition of θ2(2)=θ1(2) is satisfied. Carrier reference phases θ1(1), θ1(4), θ1(5), θ1(6), θ1(7), θ1(8), and θ1(9) before failure of converter cell 7_3 become θ2(1), θ2(4), θ2(5), θ2(6), θ2(7), θ2(8), and θ2(9) varied in the direction of advance due to failure of converter cell 7_3.

FIG. 16 is a diagram showing variation in carrier signal in the first specific example in FIG. 14.

According to the first specific example, the carrier reference phase of carrier signal CR(1) is not varied by failure of converter cell 7_2. The carrier reference phases of carrier signals CR(3) and CR(4) are varied in the direction of advance.

Carrier signal generator 203 does not vary the carrier reference phase of carrier signal CR(1). Carrier signal generator 203 advances the carrier reference phase of carrier signal CR(3) immediately after intersection of carrier signal CR(3) with cell voltage command value krefc for converter cell 7_3. Carrier signal generator 203 advances the carrier reference phase of carrier signal CR(4) immediately after intersection of carrier signal CR(4) with cell voltage command value krefc for converter cell 7_4.

Fourth Embodiment

It is when an AC output current and a DC output current from power converter 2 are low and an effective value of an arm current is small that there is a concern about imbalance in capacitor voltages in normal converter cells 7 due to increase in harmonic component of arm current Iarm when converter cell 7 fails.

Though individual cell balance control is sufficiently effective when the effective value of the arm current is large, it may not be sufficiently effective when the effective value of the arm current is small.

AC output power and DC output power, however, are determined by a higher-order command. Therefore, the AC output current and the DC output current cannot freely be set. Since a circulating current of a DC component and an AC fundamental wave component is basically used for controlling balance in average value of each phase of capacitor voltages of converter cells 7 or controlling balance in average value between the upper arm and the lower arm, there is no degree of freedom.

In a fourth embodiment, when the AC output current and the DC output current from power converter 2 are low to such an extent that the capacitor voltages of converter cells 7 within the arm are not balanced, a current at a frequency different from a frequency of a current provided from power converter 2 is circulated within power converter 2. Since the effective value of the arm current is thus larger, individual cell balance control is sufficiently effective and imbalance among converter cells 7 is rectified. The current at the frequency different from the frequency of the current provided from power converter 2 refers to a current other than a DC current and an AC current (a current of the fundamental wave) provided from AC circuit 12.

FIG. 17 is a diagram showing a configuration of control device 3 in the fourth embodiment.

Control device 3 in the fourth embodiment includes switching controller 501 and bypass controller 510 similarly to control device 3 in the first embodiment and includes a cell balancing circulating current controller 610.

When cell balancing circulating current controller 610 senses failure of converter cell 7 in any of the plurality of arms, it has a current circulated within power converter 2 in order to increase the effective value of arm current Iarm, the current having a frequency different from the frequency of the current provided from power converter 2.

FIG. 18 is a diagram showing a configuration of cell balancing circulating current controller 610.

Cell balancing circulating current controller 610 includes a first coordinate converter 611, a compensator 612, and a second coordinate converter 613.

First coordinate converter 611 converts circulating current components Izu, Izv, and Izw of three phases of U, V, and W onto a dq two-phase coordinate that rotates at a frequency θ different from the frequency of the current provided from power converter 2. Resultant Izd represents an effective component and Izq represents a reactive component, both of which represent a DC quantity.

Compensator 612 provides two-phase DC voltage command components Vzdref and Vzqref such that two-phase circulating current components Izd and Izq follow circulating current command components Izdref and Izqref converted to the two phases.

Second coordinate converter 613 converts two-phase DC voltage command components Vzdref and Vzqref calculated by compensator 612 to three-phase DC voltage command circulating current components Vdccu, Vdccv, and Vdccw. V DC voltage command circulating current components dccu, Vdccv, and Vdccw are sent to arm voltage command generators 601 of U-phase basic controller 502U, V-phase basic controller 502V, and W-phase basic controller 502W, respectively. In the description below, Vdccu, Vdccv, and Vdccw are collectively denoted as Vdcc.

FIG. 19 is a diagram showing a configuration of arm voltage command generator 601 in the fourth embodiment.

Command distributor 606 receives AC control command value Vcp, circulation control command value Vzp, DC voltage command value Vdcref, neutral point voltage Vsn, and AC voltage Vac as in the first embodiment and receives DC voltage command circulating current component Vdcc.

Command distributor 606 calculates based on these inputs, voltages to be supplied by the upper arm and the lower arm as in the first embodiment. Command distributor 606 determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from the calculated voltages.

Since the effective value of arm current Iarm increases according to the present embodiment, the fundamental wave that makes up the cell voltage command value is larger. Consequently, individual cell balance control is sufficiently effective and imbalance among converter cells 7 is rectified.

Fifth Embodiment

In the present embodiment, transformer 13 is defined as a transformer variable in transformation ratio. The transformer variable in transformation ratio is implemented, for example, by a transformer with a tap switching function.

Since AC output power and DC output power are determined by a higher-order command, the AC output current and the DC output current cannot freely be set.

Power conversion device 1 is interconnected to AC circuit 12 with transformer 13 being interposed. Therefore, by varying the transformation ratio of transformer 13, AC output current Vac can be varied without affecting AC output power and DC output power. Since the effective value of arm current Iarm can thus be increased, imbalance among converter cells 7 can be rectified.

FIG. 20 is a diagram showing a configuration of control device 3 in a fifth embodiment.

Control device 3 in the fifth embodiment includes switching controller 501 and bypass controller 510 as in the first embodiment and includes a transformer controller 504.

When transformer controller 504 senses failure of converter cell 7 in any of the plurality of arms, it varies the transformation ratio of transformer 13 in order to increase the effective value of arm current Iarm. Specifically, the AC current that flows from AC circuit 12 to power conversion device 1 is increased by lowering a ratio N (V2/V1) between a voltage V1 on a side of AC circuit 12 of transformer 13 and a voltage V2 on a side of power conversion device 1. Since the effective value of arm current Iarm thus increases, the fundamental wave that makes up the cell voltage command value is larger. Consequently, influence of a harmonic can be lessened.

Sixth Embodiment

FIG. 21 is a diagram showing a configuration of a power conversion device 1A in a sixth embodiment.

Power conversion device 1A in the sixth embodiment is different from power conversion device 1 in the first embodiment in that each arm in a power converter 2A of power conversion device 1A in the sixth embodiment includes a redundant converter cell (RSM) 7a. Redundant converter cell 7a is similar in configuration to converter cell 7 shown in FIGS. 2(a) and (b).

Redundant converter cell 7a in each arm is bypassed before occurrence of failure in any converter cell 7 within each arm. Therefore, during this period, redundant converter cell 7a does not perform a conversion operation.

Bypass of redundant converter cell 7a in each arm is canceled after occurrence of failure in any converter cell 7 within each arm. Therefore, during this period, redundant converter cell 7a performs the conversion operation instead of converter cell 7 that has failed.

Before any converter cell 7 within the arm fails, bypass controller 510 turns on bypass switch 34 of redundant converter cell 7a within that arm. After any converter cell 7 within the arm fails, bypass controller 510 turns off bypass switch 34 of redundant converter cell 7a within that arm.

As set forth above, in the present embodiment, after any converter cell 7 within each arm fails, redundant converter cell 7a performs the conversion operation instead of converter cell 7 that has failed. Thus, even when converter cell 7 fails, the number of converter cells that operate in one arm does not vary and a harmonic component in the output voltage from the converter cell can be canceled.

The number of redundant converter cells 7a within the arm is not limited to one but a plurality of redundant converter cells may be provided. Redundant converter cell 7a within the arm does not have to be fixed. A redundant converter cell may be selected every certain cycle, sequentially, or randomly, from among a plurality of converter cells that have not failed.

(Modification)

The present invention is not limited to the embodiments above but includes also modifications as below.

(1) Configuration of Power Converter 2

In the embodiment above, power converter 2 is in a configuration called a double star. Power converter 2 is mainly used as an AC-DC converter for high voltage direct current (HVDC) power transmission. Control of the power converter described in the embodiments above is also applicable to a power converter in another configuration.

FIG. 22 is a diagram showing a configuration of a part of a power conversion device 1B.

A power converter 2B of power conversion device 1B is in a configuration called a single delta. Power converter 2B is mainly used for a static var compensator.

FIG. 23 is a diagram showing a configuration of a part of a power conversion device 1C.

A power converter 2C of power conversion device 1C is in a configuration called a single star. Power converter 2C is also mainly used for a static var compensator.

A scheme for suppressing a harmonic produced due to failure of converter cell 7 as described in the embodiments above is effective also in power converters 2B and 2C. In power converter 2C including an output only on the AC side, a circulating current described in the second embodiment may be a current at a frequency other than a fundamental wave component. For example, a circulating current containing a DC component may flow.

(2) Though PWM modulation based on triangular wave comparison is described by way of example in the embodiments above, PWM modulation based on sawtooth wave comparison in which carriers are sawtooth waves may be applicable and carriers are not restricted. In a case of PWM modulation based on a space voltage vector as well, by adding a function to achieve a similar effect, a power conversion device can continue operating also in case of failure in a converter cell.

(3) Control described in the embodiments above may intermittently operate when imbalance in capacitor voltage among converter cells 7 is aggravated.

(4) In the first and second embodiments, carrier signal generator 203 may determine whether the carrier reference phase is to be delayed at the maximum value or the minimum value of the carrier signal, in order to lessen distortion of an output voltage. Specifically, carrier signal generator 203 may determine whether to delay the carrier reference phase at the maximum value or the minimum value of the carrier signal, in order to lessen influence of update of the carrier reference phase on a ratio between a duration of “1” and a duration of “0” of a generated PWM signal.

(5) In the first and third embodiments, timing of intersection between the carrier signal and the cell voltage command value within the PWM modulator may be detected based on an output from a comparator to compare the carrier signal and the cell voltage command value with each other.

(6) Though an example in which change in carrier reference phase is completed at once is described in the first to third embodiments, change in carrier reference phase may be made as being split across a plurality of steps. For example, in a first step, the carrier reference phase may be varied by Δθ/2, and in a second step, the carrier reference phase may further be varied by Δθ/2. Suppression of influence of arm output voltage distortion or the like is thus expected.

(7) Converter Cell for Circulating Current Control

When an arm includes a common converter cell and a converter cell for controlling a circulating current, the configuration of the basic controller is different from that shown in FIG. 4.

FIG. 24 is a diagram showing a configuration of a basic controller 502A in a modification.

Basic controller 502A in FIG. 24 is different from basic controller 502 in FIG. 4 in that circulation control command value Vzp provided from basic controller 502A is not provided to a command distributor 606A.

Command distributor 606A receives AC control command value Vcp, DC voltage command value Vdcref, neutral point voltage Vsn, and AC voltage Vac. Based on these inputs, command distributor 606A calculates voltages to be supplied by the upper arm and the lower arm. Command distributor 606A determines arm voltage command value krefp for the upper arm and arm voltage command value krefn for the lower arm by subtracting voltage lowering due to an inductance component within the upper arm and the lower arm from the calculated voltages. A signal to control common converter cells within the arm is generated based on arm voltage command value krefp and arm voltage command value krefn for the lower arm, as described in the first embodiment.

A not-shown control block provides a PWM modulated signal to the converter cell for circulator control based on circulation control command value Vzp provided from basic controller 502A.

It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims rather than the description above and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

REFERENCE SIGNS LIST

1, 1A, 1B, 1C power conversion device; 2, 2A, 2B, 2C power converter; 3 control device; 4u, 4v, 4w leg circuit; 5u, 5v, 5w upper arm; 6u, 6v, 6w lower arm; 7 converter cell; 7a redundant converter cell; 8A, 8B reactor; 9A, 9B arm current detector; 10 AC voltage detector; 11A, 11B DC voltage detector; 12 AC circuit; 13 transformer; 14 DC circuit; 16 AC current detector; 31p, 31n, 31p1, 31n1, 31p2, 31n2 switching element; 32 power storage element; 33 voltage detector; 34 bypass switch; 202 individual cell controller; 203 carrier signal generator; 501 switching controller; 502, 502A basic controller; 502U U-phase basic controller; 502V V-phase basic controller; 502W W-phase basic controller; 503UP U-phase upper arm controller; 503UN U-phase lower arm controller; 503VP V-phase upper arm controller; 503VN V-phase lower arm controller; 503WP W-phase upper arm controller; 503WN W-phase lower arm controller; 504 transformer controller; 510 bypass controller; 530 AD converter unit; 531 analog filter; 532 AD converter; 535 arithmetic processing unit; 536 CPU; 537 memory; 538, 539 bus I/F; 540 bus; 543 IO unit; 544 communication circuit; 545 digital input circuit; 546 digital output circuit; 547 settling-and-display unit; 548 touch panel; 555 optical repeater; 601 arm voltage command generator; 602 capacitor voltage command generator; 603 AC current controller; 604 circulating current calculator; 605 circulating current controller; 606 command distributor; 610 cell balancing circulating current controller; 611 first coordinate converter; 612 compensator; 613 second coordinate converter; 2021 individual cell balance controller; 2022 PWM modulator; 2023 signal switch; 2032 normal cell calculator; 2051 adder; Nn low-potential-side DC terminal; Np high-potential-side DC terminal; Nu, Nv, Nw AC input terminal

POWER CONVERSION DEVICE

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