Patent Application
20060189067
1. Field of the Invention
The present invention relates to power converters such as power supplies, battery chargers, DC/DC converters, AC/DC converters, AC adapters, and pulse power generator circuits.
2. Description of the Related Art
Power converters that convert DC power input or AC power input into DC output are utilized in many instruments such as information equipment including mobile information gadgets, home electric appliances, lighting fixtures, and liquid crystal displays. For example, power converters are connected to a 100-V or 200-V AC commercial power source and used for supplying 10- to 20-V DC power to personal computers, battery chargers for cellular phones, and home electric appliances.
One requirement on these power converters is electrical isolation between input and output. For instance, an AC commercial power source and end equipment of power are required to be electrically isolated for safety necessity and so that the commercial power network does not suffer from influence when any of the end equipment of power causes a ground fault; the ground relay set in the commercial power network is required not to operate even if the end equipment of power causes a ground fault. For this isolation, a high-frequency transformer compatible with the switching frequency is employed generally. Incidentally, some pulse power generator may not contain a high-frequency transformer.
One circuit topology achieving electrical isolation between input and output is the forward converter. A forward converter is disclosed in, for example, Haruo Togawa, “Hardware Design Series (Handbook for Practical Power Supply Circuit Design)”, the 22nd edition, CQ Publishing Co., Ltd., Aug. 1, 2003, p. 76.
The switching circuit 101 includes input terminals 103 and 104, a capacitor C11, a field-effect transistor Q100, and a diode D15. The input terminals 103 and 104 are connected to a DC power supply (not shown) and receive DC power supply input Vin. The input terminal 103 is connected to one terminal of a primary winding of the transformer T1, and the input terminal 104 is connected to the source of the transistor Q100. The drain of the transistor Q100 is connected to the other terminal of the primary winding of the transformer T1. The diode D15 is connected in parallel with the transistor Q100.
The transistor Q100 generates a rectangular wave by switching the DC power supply input Vin. The rectangular wave generated by the transistor Q100 is supplied to the primary winding of the transformer T1.
The diode D15 provides the protection for the transistor Q100; the diode D15 is turned on to allow a current to flow therethrough when a reverse voltage is applied to the transistor Q100.
The capacitor C11 has two roles: the capacitor C11 functions as a smoothing capacitor for smoothing the DC power supply input Vin. Furthermore, the capacitor C11 functions as the energy storage which supplies the transistor Q100 with a current for compensating the delay of the current generated immediately after the turn-on of the transistor Q100 from the DC power supply to the transistor Q100, the delay occurring within the DC power supply and by inductances of the wirings.
The transformer T1 receives the rectangular wave from the transistor Q100 at the primary winding, and outputs a rectangular wave with a voltage level in accordance with its transformation ratio from its secondary winding. The rectangular wave output from the transformer T1 is supplied to the rectifying and smoothing circuit 102.
The rectifying and smoothing circuit 102 is composed of diodes D21 and D22, a reactor L21, a capacitor C21, output terminals 105 and 106 outputting a DC output voltage Vout. The diodes D21 and D22 are used to rectify the rectangular wave from the transformer T1, and the reactor L21 and the capacitor C21 are used to smooth the rectified rectangular wave. Specifically, the diode D21 allows the rectangular wave current from the secondary winding of the transformer T1 to flow through the reactor L21 and the capacitor C21, when the transistor Q100 is at on-state. The diode D22 supplies the energy stored across the reactor L21 to the capacitor C21 and thereby smoothes the output voltage Vout, when the transistor Q100 is at off state. In the case where a pulse output is requested for the output voltage Vout, the capacitor C21 is often omitted.
If an AC power supply input is available in place of a DC power supply input, a full-wave rectifier circuit 107 composed of diodes D11 to D14 may be connected to the input of the switching circuit 101, as shown in
In such a power converter, it is important to reduce power losses. Power converters are used in many instruments, and thus power losses in the power converters will lead to stupendous power losses on a society basis even if a loss in each individual instrument is nothing but several watts. Reducing power losses in power converters provides an extremely significant contribution to the improvement of the global environment. In addition to that, the reduction of power losses can downsize power converters; reducing power losses permits cooling mechanisms, such as radiating fins, to be smaller.
On this account, various approaches have been proposed for the reduction of power losses in power converters; the proposed approaches include improvements in control methods and in the existing power transistors. These conventional approaches, however, face limits of power consumption reduction within power converters.
One obstacle to reduction of power losses in power converters is the performance of switching transistors. As a switching transistor, a field-effect transistor (FET) is typically employed; however, the switching FET has a high on-resistance and therefore has a high source-drain voltage (on-voltage) at on-state. In addition, the switching FET suffers from long switching time, that is, time of duration necessary for switching between the on and off states.
For example, the performance of a typical switching FET used in a power converter working on a 142-V DC input voltage (that is, the maximum voltage obtained by full-wave rectifying a 100-V AC voltage) is as follows:
1) Rated drain-source current: 2.0 A
2) Rated drain-to-source withstand voltage: 400V
3) Drain-to-source on-resistance: 3.6Ω
4) Turn-on time: 9.9 ns
5) Turn-off time: 11 ns
It should be noted that the above performances are on condition of the device area of 1 mm2. Furthermore, the values of the on-resistance, turn-on time and turn-off time are on condition of a junction temperature of 100° C. and a gate voltage of 10V; if the gate voltage is lower than 10 V, the on-resistance, turn-on time and turn-off time are further increased. The rated current is set to 2 A because of a design requirement so that the junction temperature can be kept at the rated temperature of 150° C. or less with sufficient margin. The withstand voltage is higher than the input DC voltage for the following reason: a steep overvoltage called switching surge is applied to the switching FET when the switching FET is turned off. In most cases, the switching FET is selected so as to withstand a switching surge by itself; it is not preferable to use a surge absorber to the switching FET due to the occurrence of loss. Generally, the switching FET is chosen so as to have a withstand voltage about twice as high as an input DC voltage.
In the case where the input current is 1 A, the typical switching FET's on-resistance of 3.6Ω undesirably increases the on-voltage up to 3.6 V. This generates an undesirably large power loss. Besides, undesirably large turn-on time and turn-off time of the switching FET would aggravate the power loss.
As a switching transistor, an insulated gate bipolar transistor (IGBT) may be used in place of an FET. The circumstances described above are the same on the IGBT. The switching time of an IGBT is much larger than that of an FET, resulting in a greater switching loss.
As stated above, in the conventional approaches, since the switching transistor suffers from a large loss and is insufficient in switching speed, the switching frequency of the power converter is limited to several hundred kHz, which is 90% at most efficient on the whole; in other words, there is a loss of 10% at least. Due to the loss of 10%, large-sized cooling equipment is required to cool the switching transistor.
Therefore, there is a need to provide a power converter with high efficiency.
Other arts related to the present invention are disclosed in the following documents.
U.S. Pat. No. 6,423,989, the whole disclosure which is incorporated herein by reference, and the corresponding Japanese Laid-open Patent Application No. P2001-338928A disclose the structure and manufacturing method of a SiGe hetero bipolar transistor.
Japanese Laid-open Patent Application No. P2002-299602A discloses a bipolar transistor which suppresses the Kirk effect, which inhibits the increase of a current gain, with high withstand voltage.
An object of the present invention is to provide a power converter with high efficiency.
To accomplish this purpose, the present invention employs a SiGe heterobipolar transistor (hereinafter referred to as SiGe transistor) as a switching transistor. The high-speed switching characteristics of the SiGe transistor effectively reduce a power loss in the power converter.
Conventionally, it has been not conceived to apply a SiGe transistor to a power converter as far as the inventors know. This may be because the SiGe transistor is of high speed but suffers from the low withstand voltage and current gain; the low withstand voltage and current gain are not preferable in principle for application to a power converter. SiGe transistors are most typically used as amplifiers of high-frequency signals in the GHz band within cellular phones, due to the high-speed switching capability. In such applications, low internal noise is most important, while increased withstand voltage and current gain are not so important. Accordingly, researches and developments of the SiGe transistor have been focused on reducing internal noise in general.
However, the inventors have found out that the problems of low withstand voltage and current gain can be overcome by optimization of the structure of the SiGe transistor at the expense of internal noise. In other words, the inventors have discovered that the SiGe transistor can offer compatibility among high-speed switching capability, high withstand voltage, and high current gain, and thereby the inventor has come to conceive the present invention.
More specifically, a power converter according to the present invention is composed of a switching circuit with a bipolar transistor for switching a DC power supply input. A base layer of the bipolar transistor includes a SiGe layer.
Preferably, the power converter further includes a rectifier circuit, and a transformer having a primary winding connected to the switching circuit, and a secondary winding connected to the rectifier circuit. In this case, the power converter may further include another rectifier circuit which receive an AC power supply input, and provides the DC power supply input.
In a preferred embodiment, the switching circuit includes an input terminal for receiving the DC power supply input. The bipolar transistor is installed between the primary winding and the input terminal, and provides an electrical connection between the primary winding and the input terminal in response to a control signal.
Preferably, the power converter further includes a diode connected between a collector and an emitter of the bipolar transistor.
In a preferred embodiment, the base layer of the bipolar transistor includes a Si layer coupled to an emitter layer of the bipolar transistor. The SiGe layer is installed between the Si layer and the collector layer of the bipolar transistor. In this case, the Ge concentration of the SiGe layer preferably ranges from 6 to 16 mol %. Moreover, the base layer preferably has a thickness of 100 to 400 nm, and the collector layer preferably has a thickness of 20 to 90 μm.
In another preferred embodiment, the SiGe layer includes a first SiGe layer connected to the emitter layer of the bipolar transistor, and a second SiGe layer disposed between the first SiGe layer and the collector layer of the bipolar transistor. The Ge concentration of the first SiGe layer is lower than the Ge concentration of the second SiGe layer. In this case, the Ge concentration of the second layer preferably ranges from 6 to 16 mol %. Furthermore, the base layer preferably has a thickness of 100 to 400 nm, and the collector layer preferably has a thickness of 20 to 90 μm.
In still another preferred embodiment, the Ge concentration of the SiGe layer increases with the distance from the emitter layer. In this case, a peak value of Ge concentration of the SiGe layer preferably ranges from 6 to 16%. Moreover, the base layer preferably has a thickness of 100 to 400 nm, and the collector layer preferably has a thickness of 20 to 90 μm.
Such a structure of the power converter may be applied to a power conversion unit which includes a plurality of power conversion circuits sharing an external input terminal for receiving external power supply input.
The embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. It is to be noted that the same or corresponding numerals denotes the same, similar, or corresponding components in the drawings.
The structure of the power converter 200 is basically similar to the structure of the conventional forward converter 100 in r downsizing and reducing costs of the power converter 200.
More specifically, the power converter 200 of this embodiment is composed of a switching circuit 201, a transformer T1, and a rectifying and smoothing circuit 102.
The switching circuit 201 includes input terminals 103 and 104, a capacitor C11, a SiGe transistor Q100, and a diode D15. The input terminals 103 and 104 are connected to a DC power supply (not shown) and receive a DC power supply input Vin. The input terminal 103 is connected to one terminal of the primary winding of the transformer T1. The input terminal 104 is connected to the emitter of the SiGe transistor Q100. The collector of the SiGe transistor Q10 is connected to the other terminal of the primary winding of the transformer T1. The diode D15 is connected in parallel with the SiGe transistor Q10.
The SiGe transistor Q10 generates a rectangular wave by switching the DC power supply input Vin in response to a control signal supplied to the base thereof. The rectangular wave generated by the SiGe transistor Q10 is supplied to the primary winding of the transformer T1.
The diode D15 provides the protection for the SiGe transistor Q10; the diode D15 is turned on and allows a current to flow therethrough, when a reverse voltage is applied to the SiGe transistor Q10.
The capacitor C11 has two roles: the capacitor C11 functions as a smoothing capacitor for smoothing the DC power supply input Vin. Moreover, the capacitor C11 operates as a energy source which supplies the a current to the SiGe transistor Q10 in order to compensate for delay of a current generated immediately after the turn-on of the SiGe transistor Q10 from the DC power supply to the SiGe transistor Q10, the delay occurring within the DC power supply and by the inductances in the wirings.
The transformer T1 receives the rectangular wave from the SiGe transistor Q10 at the primary winding, and outputs a rectangular wave with a voltage level corresponding to the transformation ratio from the secondary winding. The rectangular wave from the transformer T1 is supplied to the rectifying and smoothing circuit 102.
The rectifying and smoothing circuit 102 includes diodes D21 and D22, a reactor L21, a capacitor C21, output terminals 105 and 106 outputting a DC output voltage Vout. The diodes D21 and D22 are used to rectify the rectangular wave from the transformer T1, and the reactor L21 and the capacitor C21 are used to smooth the rectified rectangular wave. More specifically, the diode D21 allows the rectangular wave current from the secondary winding of the transformer T1 to flow through the reactor L21 and the capacitor C21 when the SiGe transistor Q100 is at on-state. The diode D22 supplies the energy stored across the reactor L21 to the capacitor C21, and thereby smoothes the output voltage Vout, when the SiGe transistor Q10 is at off-state. In the case where pulse output is requested as the output voltage Vout, the capacitor C21 is often omitted.
As shown in
As described above, the optimization of structure of the SiGe transistor Q10 is important to for increasing an operating speed and reducing the collector-to-emitter voltage at on-state.
To achieve a high withstand voltage, a low on-state voltage, and a high switching speed, the SiGe transistor Q10 is optimized in the thickness of the base layer 4, the thickness of the collector layer 3, and the Ge profile of the SiGe layer.
The N-type silicon substrate 2 is heavily doped with phosphorus or arsenic as N-type dopants. The dopant concentration therein is preferably 1×1018 to 1×1020/cm3, and the thickness of the N-type silicon substrate 2 is preferably 100 to 500 μm. In this embodiment, the dopant concentration of the N-type silicon substrate 2 is 2×1019/cm3 and the thickness thereof is 100 μm, as shown by the line 12 in
The collector layer 3 is lightly doped with phosphorus or arsenic as N-type dopants. The dopant concentration therein is preferably 1×1014 to 5×1015/cm3. In this embodiment, the dopant concentration of the collector layer 3 is 6×1014/cm3, as shown by the line 13 in
The thickness of the collector layer 3 is preferably 20 to 90 μm. The reason for that can be understood from
The base layer 4 is doped with boron as P-type dopants. The dopant concentration thereof is preferably 1×1017 to 1×1018/cm3. In this embodiment, the dopant concentration of the base layer 4 is 5×1017/cm3 as shown by the line 14 in
In this embodiment, the base layer 4 is composed of a Si layer positioned closer to the emitter layer 5 and a SiGe layer positioned closer to the collector layer 3. In other words, as shown by a dashed line 16 in
The Ge concentration in the SiGe layer (that is, the Ge concentration of the portion other than the boundary portions) is preferably 6 to 16 mol %.
The thickness of the base layer 4 (that is, the sum of the thicknesses of the Si layer and the SiGe layer which form the base layer 4) is preferably 100 to 400 nm. If the base layer 4 is thinner than 100 nm, the withstand voltage undesirably decreases. On the other hand, if the base layer 4 is thicker than 400 nm, the current gain hfe is undesirably decreased.
The emitter layer 5 is heavily doped with phosphorus or arsenic as N-type dopants. The dopant concentration of the emitter layer 5 has a Gaussian distribution near the emitter electrode 7 and is a steady value near the base layer 4. The dopant concentration in the emitter layer 5 is 1×1020/cm3 in the peak value and is 5×1018/cm3 at the boundary P0 between the emitter layer 5 and the base layer 4. The dopant profile in the portion near the emitter electrode 7 may have a trapezoidal distribution, not a Gaussian distribution. The thickness of the emitter layer 5 is preferably 0.5 to 2 μm. In this embodiment, the emitter layer 5 is 1 μm thick.
In another embodiment, the portion between the boundary P0 of the emitter layer 5 and the base layer 4 and the position P1 inside the base layer 4 may contain Ge. In other words, the base layer 4 includes a first SiGe layer positioned closer to the emitter layer 5 and a second SiGe layer positioned closer to the collector layer 3, and the Ge concentration of the first SiGe layer is lower than the Ge concentration of the second SiGe layer. Preferably, the Ge concentration in the portion ranging from the boundary P0 to the position P1 (i.e., the first SiGe layer positioned closer to the emitter layer 5) is 0% to 3%. In this embodiment, the Ge concentration between the position P1 and the boundary P2 is preferably 6 to 16%, more preferably, 8 to 13%.
In still another embodiment, the base layer 4 may be composed of a SiGe layer with a sloped Ge profile, as shown in
In still another embodiment, the SiGe transistor Q10 may adopt a planer structure as shown in
The performance of the SiGe transistor Q10 achieved by the above described structure optimization is as follows:
1) Rated current: 2.0 A
2) Rated drain-to-source withstand voltage: 400V
3) Drain-to-source on-resistance: 400 mΩ
4) Turn-on time: 3 ns
5) Turn-off time: 3 ns
6) Current gain hfe: 100 or more
It should be noted that the above performances are on condition of the bipolar transistor device area of 1 mm2. The values of the on-resistance, turn-on time, turn-off time and current gain hfe are on condition of the junction temperature of 100° C.
The above described structure optimization decreases the on-resistance down to 400 mΩ, thereby decreasing the on-voltage down to 0.4 V during switching an input current of 1 A. This effectively reduces a switching loss in the power converter.
In addition to that, the above stated structure optimization reduces the turn-on time and the turn-off time down to 3 ns, resulting in effective reduction of the switching loss.
Meanwhile, the adoption of the above described SiGe transistor reduces the turn-on time and the turn-off time down to 3 ns, the turn-on time being the time required for switching the switching transistor from the off-state to the on-state, and the turn-off time being the time required for switching the same from the off state to the on state. The reduction in the turn-on time and the turn-off time effectively reduces the loss within the transistor during the switching (that is, the time integral of the product of transient voltage and transient current). In addition, the adoption of the SiGe transistor decreases the on-voltage, thereby effectively reduces the loss within the switching transistor in the on state. Decreasing the loss within the switching transistor allows reducing the size and weight of the cooling mechanism of the switching transistor, such as aluminum cooling fins and a fan. This contributes to the downsizing of the power converter and the products equipped with it.
The reductions in the turn-on and turn-off times allow boosting the switching frequency. This permits the transformer, inductor and capacitor within the power converter to be downsized, which contributes to the reduction in size of the power converter. If a nanotechnology-applied metal/ferrite composite magnetic core is employed in the transformer for improving the high-frequency characteristics and reducing the loss, this allows increasing the switching frequency up to several MHz, which leads to further efficiency enhancement and size reduction.
The utility of the power converter in this embodiment will be more specifically described hereinafter, with considerations given to specifications required by AC adapters or battery chargers for cellular phones, notebook computers and so on.
Below presented are comparisons in the on-state loss, the turn-on loss, and the turn-off loss of the switching transistor, between the case where the FET is used as the switching transistor and the case where the SiGe transistor is used as the switching transistor. The specifications of the power converter are on the assumption that the input voltage Vin is DC 135 V (this is the average DC voltage obtained by rectifying the 100-V AC voltage.), the output voltage is 10 V, and the power supply capacity is 100 W. In this case, the magnitude of the current to be switched by the switching transistor is about 1 A in peak value. Additionally, the switching frequency is set to be 1 MHz in consideration of the current technological trends.
If the FET is used as the switching transistor, the loss in the switching transistor is 2.27 W in total; for a breakdown, the on-state loss is 1.8 W, the turn-on loss is 0.2 W, and the turn-off loss is 0.25 W.
On the other hand, if the SiGe transistor mentioned above is used as a switching transistor, the loss in the switching transistor is 0.34 W in total. For a breakdown, the on-state loss is 0.2 W, the turn-on loss is 0.07 W, and the turn-off loss is 0.07 W. The usage of the SiGe transistor decreases the loss by 1.93 W.
The loss reduction of 1.93 W has an extreme significance. For instance, assuming that the power converter of this embodiment is applied to all AC adapters for notebook computers, about 170 million notebook computers were manufactured in 2002 and thus energy of 328.1 thousand kW would have been saved. The power converter of this embodiment has the potential to achieve overall energy saving of several million kW because it can be applied to many other products, for example, battery chargers for cellular phones, and power supplies for liquid crystal display TVs, OA equipment, and lighting fixtures.
The present invention is described with use of various embodiments, but this does not intend that the present invention is limited to these embodiments. It is self-evident to those skilled in the art that alterations are possible within a range of the claims.
In particular, it is to be noted that the present invention may be also applied to power converters employing other circuit topologies, for example, flyback converters and LCC topologies. As shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-298089 | Aug 2003 | JP | national |
This application is a continuation-in-part of International Application Ser. No. PCT/JP2004/012023, filed on Aug. 20, 2004, which claims a priority based on Japanese Patent Application No. 2003-298089, filed on Aug. 22, 2003. The entire disclosures of these two applications are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP04/12023 | Aug 2004 | US |
| Child | 11355182 | Feb 2006 | US |
