Power converter with an adaptive controller and method of operating the same

Information

  • Patent Grant
  • 9197132
  • Patent Number
    9,197,132
  • Date Filed
    Thursday, February 25, 2010
    14 years ago
  • Date Issued
    Tuesday, November 24, 2015
    9 years ago
Abstract
A controller for a power converter, and method of operating the same. The controller improves power converter operating efficiency by regulating an internal power converter operating characteristic depending on a value of a power converter parameter measured after a manufacturing step, or an environmental parameter, preferably employing a table with entries dependent on the parameter value. The internal operating characteristic may be an internal bus voltage, a voltage level of a drive signal for a power switch, a number of paralleled power switches selectively enabled to conduct, or a basic switching frequency of the power converter. The controller may regulate an internal operating characteristic of the power converter using a functional relationship dependent on the parameter value. The environmental parameter may be received as a signal from an external source. The parameter measured after a manufacturing step may be a parameter measured from representative power converter(s).
Description
TECHNICAL FIELD

The present invention is directed, in general, to electronic power conversion and, more specifically, to a power converter including a controller adapted to improve power conversion efficiency, and a method of operating the same.


BACKGROUND

A switch-mode power converter (also referred to as a “power converter”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. Controllers associated with the power converters manage an operation thereof by controlling the conduction periods of power switches employed therein. Generally, the controllers are coupled between an input and output of the power converter in a feedback loop configuration.


Typically, the controller measures an internal operating characteristic (e.g., an internal bus voltage) or an output characteristic, (e.g., an output voltage or an output current) representing an operating condition of the power converter, and based thereon modifies a duty cycle of a power switch or power switches of the power converter to regulate the internal operating characteristic or the output characteristic. The duty cycle is a ratio represented by a conduction period of a power switch to a switching period thereof. Thus, if a power switch conducts for half of the switching period, the duty cycle for the power switch would be 0.5 (or 50 percent). Additionally, as the needs for systems such as a microprocessor powered by the power converter dynamically change (e.g., as a computational load on the microprocessor changes), the controller should be configured to dynamically increase or decrease the duty cycle of the power switches therein to regulate the internal or the output characteristic at a desired value. In an exemplary application, the power converters have the capability to convert an unregulated dc input voltage such as five volts to a lower, regulated, dc output voltage such as 2.5 volts to power a load. In another exemplary application, the power converters have the capability to convert an unregulated ac input voltage such as 120 volts to a regulated internal dc bus voltage, such as 300 volts dc, and to further convert the regulated internal dc bus voltage into a dc output voltage such as 2.5 volts to power a load.


An important consideration for the design of a power converter and its controller is the efficiency (also referred to as “operating efficiency”) in a particular application, and under particular operating conditions. The efficiency of a power converter is the ratio of its output power to its input power. The practical efficiency of a power converter that delivers at least half its rated output power to a load is typically 80 to 90%. As load current is reduced, the operating efficiency correspondingly goes down. In the limiting case wherein the load current approaches a small percentage of the maximum rated current of the power converter, the operating efficiency approaches zero due to the need to provide power for fixed internal loads such as the controller itself, for drivers for internal high-frequency power switches, and for inherently dissipative circuit elements such as the magnetic core of a high-frequency transformer. Power converter efficiency is accordingly dependent on an internal operating characteristic of the power converter or an output characteristic thereof. Examples of an internal operating characteristic include a temperature of a component part, an internal bus voltage, the voltage level of a drive signal for a power switch, the number of paralleled power switches selectively enabled to conduct, or even the basic switching frequency of the power converter. Examples of an output characteristic include a load current drawn from the power converter and an output voltage. Power converter efficiency is also dependent on a parameter that may be measured after a manufacturing step, which may reflect a dependency of efficiency on particular parts used to manufacture the power converter in question.


Operating efficiency is an important quality indicator for a power converter because of the broad impact efficiency has on equipment reliability and size, operating expense, and corresponding effects on the load equipment that it powers. Thus, system considerations of achieving high operating efficiency have immediate effects on the applicability of a particular power converter design, and the associated price thereof in the marketplace.


Numerous prior art attempts have been made to improve the operating efficiency of a power converter. Most attempts have focused on selection of proper components to provide the maximum operating efficiency for average operating conditions at a chosen operating point, such as a load current at three quarters of a maximum rated value, the environmental temperature at a typical expected value, and for a typical mix of actual components employed to manufacture a particular power converter unit. Recognizing the wide range of possible values for any of these parameters, there is substantial remaining opportunity to improve the efficiency of a power converter for a particular operating condition.


An example of the prior art to provide high power converter efficiency at a particular operating condition is provided in U.S. Pat. No. 6,351,396, entitled “Method and Apparatus for Dynamically Altering Operation of a Converter Device to Improve Conversion Efficiency,” to Jacobs, issued Feb. 26, 2002, which is incorporated herein by reference. Jacobs is directed to a search process that varies parameters accessible to the controller during power converter operation, such as a timing delay between conduction intervals of the power switches, and observes the resulting effect on the duty cycle. The duty cycle is employed as an indicator of operating efficiency, and parameters accessible to the controller are adjusted to produce an extremum in the duty cycle for a particular operating condition, thereby increasing the operating efficiency of the power converter. While Jacobs performs efficiency optimization under actual operating conditions, the reference nonetheless fails to consider constraints of the actual application (such as a requirements document or operating specification document) or the environment during execution of the process of efficiency optimization, or a signal from an external source to limit or alter the optimization process. For example, no attempt is made to measure a parameter of a particular power converter unit after a manufacturing step (or to measure a parameter of a representative power converter unit), or to control, program, or otherwise alter a response of the controller to reflect such measurement, such as by controlling an internal operating characteristic or an output characteristic.


Another attempt to adaptively operate a power converter to improve efficiency is described in U.S. Pat. No. 5,742,491, entitled “Power Converter Adaptively Driven,” to Bowman, et al. (“Bowman”), issued Apr. 21, 1998, which is incorporated herein by reference. Bowman is directed to a drive circuit for a power converter wherein the timing of conduction intervals for the power switches is programmed to increase the efficiency of the power converter while keeping stresses on individual components within acceptable limits. A predetermined delay between drive waveforms supplied to the power switches and to the synchronous rectifiers of the power converter is altered with a predetermined program that is a function of an operating condition of the power converter to allow the power converter to operate efficiently in an anticipated operating environment and with anticipated component realizations. A design objective is to desensitize the operating efficiency to an expected range of changes in the operating environment and with an anticipated range of component realizations, which results in a compromise in a static program to optimize efficiency that might otherwise be achievable with the design of an improved controller not so limited. Bowman relies on a limited set of a priori conditions, and does not adjust controller parameters in response to a measured power converter parameter for the particular power converter unit after a manufacturing step, or to a measured parameter of a representative power converter unit, or in response to a signal from an external source representing an environmental parameter.


A further attempt to optimize power conversion efficiency is described in U.S. Pat. No. 5,734,564, entitled “High-Efficiency Switching Power Converter,” to Brkovic, issued Mar. 31, 1998, which is incorporated herein by reference. Brkovic describes measuring an internal operating characteristic of a power train of the power converter (i.e., a voltage across a power switch) and adjusting a timing of a duty cycle for the power switch in response to the measured power switch voltage to improve power conversion efficiency. Brkovic provides a preconditioned response to a measured parameter of the particular power converter unit after a manufacturing step. Brkovic does not consider adapting or constraining the response to a signal from an external source representing an environmental parameter.


It is well known in the art to couple an input control signal to a power converter to control the setpoint of an output characteristic thereof. For example, the output voltage of a power converter adapted to supply power to a microprocessor load (wherein the operating voltage thereof is not known at the time of manufacture or that is changed during normal operation such as when a microprocessor enters a sleep mode) can be statically or dynamically altered by an input control signal. However, this control mechanism merely changes a setpoint for an output characteristic of the power converter, and is not adapted to optimize the efficiency of the power converter at the signaled setpoint.


Thus, attempts have been made in the prior art to configure controllers to statically optimize power conversion efficiency of a power train. The static responses have included varying an internal operating characteristic of the power converter with a fixed program to alter an internal operating characteristic of the power converter in response to a measured characteristic such as a load current to improve power conversion efficiency. The aforementioned attempts to improve efficiency have been facilitated by inclusion of programmable digital devices such as microprocessors, digital signal processors, application specific integrated circuits, and field-programmable gate arrays in the controller. Nonetheless, the responses of a controller have not included consideration of a measured parameter after a manufacturing step for the particular power converter unit that is being controlled such as a measurement of an actual delay of a particular power switch or an internal circuit after completion of a stage of manufacture.


Considering limitations as described above, a controller for a power converter is presently not available for the more severe applications that lie ahead that depend on achieving higher operating efficiency for a particular operating characteristic constrained or controlled by an environmental parameter. In addition, a controller for a power converter is presently not available that responds to a parameter measured after a manufacturing step for the particular power converter unit, or to a parameter measured after a manufacturing step on a representative power converter unit, or on power converter units in a representative run, to improve the operating efficiency thereof.


Accordingly, what is needed in the art is a controller for a power converter that adaptively improves power conversion efficiency of a power converter in response to a measured parameter of the power converter after a manufacturing step, or to a parameter measured on a representative power converter unit, and includes consideration of operating conditions and a signal from an external source representing an environmental parameter. In accordance therewith, a controller for power converter is provided that adaptively improves power conversion efficiency, including the considerations as provided herein.


SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention which include a controller for a power converter and a method of forming the same. In one embodiment, the controller includes a power switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof. In a preferred embodiment, the controller is configured to provide a signal to control the duty cycle of the power switch as a function of the output characteristic by regulating an internal operating characteristic of the power converter to improve power converter operating efficiency. The internal operating characteristic is regulated depending on a value of one of a parameter of the power converter measured after a manufacturing step and an environmental parameter for the power converter.


In a preferred embodiment, the controller regulates the internal operating characteristic of the power converter in accordance with a table with entries dependent on a value of one of the parameter of the power converter measured after the manufacturing step and the environmental parameter of the power converter. In a further preferred embodiment, the internal operating characteristic is one of an internal bus voltage, a voltage level of a drive signal for the power switch, a number of paralleled power switches selectively enabled to conduct, a temperature of a component part, a timing relationship between two or more power switches, or a basic switching frequency of the power converter. In a further preferred embodiment, the controller regulates an internal operating characteristic of the power converter in accordance with a functional relationship dependent on a value of one of the parameter of the power converter measured after a manufacturing step and an environmental parameter for the power converter, which may be an environmental parameter received as a signal from an external source.


In a further preferred embodiment, the internal operating characteristic is regulated by the controller on a time scale substantially different from a time scale for controlling the duty cycle of the power switch. In a further preferred embodiment, the parameter of the power converter measured after a manufacturing step is measured automatically in a test fixture. In a further preferred embodiment, the parameter of the power converter measured after a manufacturing step is a parameter measured from a representative power converter unit, or from power converter units produced during a run of representative power converter units. In a further preferred embodiment, the internal operating characteristic of the power converter is controlled in a step-by-step manner during an efficiency optimization process. In a further preferred embodiment, the internal operating characteristic of the power converter is controlled in a step-by-step manner during an efficiency optimization process on a time scale substantially different from a time scale for controlling the duty cycle of the power converter.


In another aspect and for use with a power converter couplable to a source of electrical power adapted to provide an input voltage thereto, the power converter includes a power switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof. The present invention provides a method of operating a controller for the power converter to improve power converter operating efficiency so that an internal operating characteristic is regulated depending on a value of one of a parameter of the power converter measured after a manufacturing step and an environmental parameter for the power converter. In a preferred embodiment, the controller provides a signal to control the duty cycle of the power switch as a function of the output characteristic by regulating an internal operating characteristic of the power converter. In a preferred embodiment, the method includes regulating the internal operating characteristic of the power converter in accordance with a table with entries dependent on a value of one of the parameter of the power converter measured after the manufacturing step and the environmental parameter of the power converter. In a further preferred embodiment, the method includes regulating the internal operating characteristic dependent on one of an internal bus voltage, a voltage level of a drive signal for a power switch, a number of paralleled power switches selectively enabled to conduct, a temperature of a component part, a timing relationship between two or more power switches, or a basic switching frequency of the power converter. In a further preferred embodiment, the method includes regulating the internal operating characteristic of the power converter in accordance with a functional relationship dependent on a value of one of the parameter of the power converter measured after a manufacturing step and an environmental parameter for the power converter, which may be an environmental parameter received as a signal from an external source.


In a further preferred embodiment, the method includes regulating the internal operating characteristic on a time scale substantially different from a time scale for controlling the duty cycle of the power switch. In a further preferred embodiment, the method includes measuring a parameter of the power converter automatically in a test fixture after a manufacturing step. In a further preferred embodiment, the method includes measuring a parameter from a representative power converter unit, or from power converter units produced during a run of representative power converter units, to control the parameter of the power converter. In a further preferred embodiment, the method includes adjusting the internal operating characteristic of the power converter to improve an operating efficiency in a step-by-step manner during an efficiency optimization process. In a further preferred embodiment, the method includes adjusting the internal operating characteristic of the power converter on a time scale substantially different from a time scale for controlling the duty cycle of the power converter.


The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.





BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:



FIG. 1 illustrates a block diagram of a power converter controlled by a conventional controller;



FIG. 2 illustrates a schematic diagram of an exemplary power train of a buck power converter;



FIG. 3 illustrates a schematic diagram of an embodiment of a power converter including a controller constructed according to the principles of the present invention;



FIG. 4 illustrates exemplary waveform diagrams to control the conduction intervals of selected power switches of the power converter of FIG. 3 with an intervening delay therebetween;



FIGS. 5A and 5B illustrate diagrams of exemplary multidimensional tables for the time delays for the control signals to control the conduction intervals of synchronous rectifier switches in accordance with a representative operating parameter of the power converter of FIG. 3;



FIG. 6 illustrates an embodiment of a functional representation to improve power conversion efficiency constructed according to the principles of the present invention;



FIG. 7 illustrates a block diagram of an embodiment of a power converter constructed according to the principles of the present invention;



FIG. 8 illustrates a block diagram of an embodiment of a power converter constructed according to the principles of the present invention;



FIGS. 9A to 9F illustrate the dependence of power converter efficiency on various operating parameters and the operating environment in accordance with the principles of the present invention; and



FIG. 10 illustrates an ac input voltage waveform including an exemplary input line voltage dropout transient, showing time histories of possible internal bus voltages in accordance with the principles of the present invention.





DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.


The present invention will be described with respect to exemplary embodiments in a specific context, namely, a controller for a power converter and, more particularly, a controller for a power converter that regulates an output characteristic of the power converter at an output thereof that adaptively controls an internal operating characteristic to increase power conversion efficiency in response to a parameter of the power converter measured after a manufacturing step and/or an environmental parameter of the power converter. The parameters mentioned above are typically measured after the power converter(s) are implemented and/or after a signal is received from an external source representing an environmental parameter. Examples of an environmental parameter include, without limitation, a signal indicating the existence of a paralleled power converter, the operational state of the paralleled power converter, that the powered system is operating from a backup power source, a request for a particular load voltage, an indication that a particular portion of the load has failed, or has been disabled, or is operating at a reduced power level.


Additionally, the controller for a power converter according to the principles of the present invention can control, alter, or otherwise constrain an internal operating characteristic (such as a gate drive voltage level, a switching frequency, an internal voltage or current, etc.) or an output characteristic (such as a regulated voltage setpoint of the power converter) to improve an efficiency thereof in response to a signal from an external source representing an environmental parameter (such as the existence of a parallel-coupled power converter powering a common load). For example, the internal dc bus voltage of a power converter might be adaptively reduced to improve the power conversion efficiency of a front-end boost power converter, but such voltage reduction would directly affect the holdover capability of the power converter during periods of loss of ac input voltage (often referred to as line dropout), which might be a required internal operating characteristic. Holdover capability is generally inversely proportional to the load on the power converter and would depend on the presence and operational state of a paralleled power converter. The data from an external source representing an environmental parameter can be employed by an adaptive controller, for example, to reduce the internal dc bus voltage to a particular level above a lower voltage limit dependent on the measured power converter load and the external data, and thereby improve operating efficiency in view of an internal characteristic or an output characteristic, but constrained by the signal from the external source.


Referring initially to FIG. 1, illustrated is a block diagram of a power converter controlled by a conventional controller 110. The power converter includes a power train 105 coupled to a source of electrical power (represented by a battery, but may be other sources of power, such as ac power) for providing an input voltage Vin for the power converter. The power converter also includes a controller 110, and provides power to a system (not shown) such as a microprocessor coupled to an output thereof. The power train 105 may employ a buck topology as illustrated and described with respect to FIG. 2 below.


The power train 105 receives an input voltage Vin at an input thereof and provides a regulated output characteristic (e.g., an output voltage Vout) to power a microprocessor or other load coupled to an output of the power converter. The controller 110 is typically coupled to a voltage reference representing a desired characteristic such as a desired system voltage from an internal or external source associated with the microprocessor, and to the output voltage Vout of the power converter. In accordance with the aforementioned characteristics, the controller 110 provides a signal to control a duty cycle and a frequency of at least one power switch of the power train 105 to regulate the output voltage Vout or another characteristic thereof. Thus, the controller 110 for the power train 105 of a power converter, particularly a switch-mode power converter, generally measures an internal operating characteristic or an output characteristic of the power converter and controls a duty cycle of a power switch therein in response to the measured characteristic to regulate the internal operating characteristic or the output characteristic thereof.


A driver (not shown) may be interposed between the controller 110 and the power train 105 to provide a drive signal(s) for the power switch(es) with sufficient amplitude and with waveform characteristics to efficiently enable or disable conductivity of the power switch(es). In accordance with the aforementioned characteristics, a drive signal is provided by a driver to control a duty cycle and a frequency of one or more power switches of the power converter, preferably to regulate the output voltage Vout thereof. For a P-channel metal-oxide semiconductor power switch, a gate drive signal is typically driven negative (with respect to the source terminal) to turn on the power switch, and for an N-channel metal-oxide semiconductor power switch, a gate drive signal is typically driven positive (with respect to the source terminal) to turn on the power switch. A driver may employ techniques to provide sufficient signal delays to prevent shoot-through currents when controlling multiple power switches in a power converter.


Turning now to FIG. 2, illustrated is a schematic diagram of an exemplary power train of a buck power converter. The power train of the power converter receives an input voltage Vin (e.g., an unregulated input voltage) from a source of electrical power (represented by a battery) at an input thereof and provides a regulated output voltage Vout to power, for instance, a microprocessor at an output of the power converter. In keeping with the principles of a buck topology, the output voltage Vout is generally less than the input voltage Vin such that a switching operation of the power converter can regulate the output voltage Vout. A main power switch Qmain is enabled to conduct by a gate drive signal D for a primary interval and couples the input voltage Vin to an output filter inductor Lout. During the primary interval, an inductor current ILout flowing through the output filter inductor Lout increases as a current flows from the input to the output of the power train. An ac component of the inductor current ILout is filtered by an output capacitor Cout.


During a complementary interval, the main power switch Qmain is transitioned to a non-conducting state and an auxiliary power switch Qaux is enabled to conduct by a complementary gate drive signal 1-D. The auxiliary power switch Qaux provides a path to maintain a continuity of the inductor current ILout flowing through the output filter inductor Lout. During the complementary interval 1-D, the inductor current ILout through the output filter inductor Lout decreases. In general, the duty cycle of the main and auxiliary power switches Qmain, Qaux may be adjusted to maintain a regulation of the output voltage Vout of the power converter. Those skilled in the art understand that the conduction periods for the main and auxiliary power switches Qmain, Qaux may be separated by a small time interval to avoid cross conduction current therebetween and beneficially to reduce the switching losses associated with the power converter. Thus, the power train of a switch-mode power converter generally includes a plurality of power switches coupled to reactive circuit elements to provide the power conversion function therefore.


Turning now to FIG. 3, illustrated is a schematic diagram of an embodiment of a power converter including a controller 311 constructed according to the principles of the present invention. The power converter includes two exemplary power stages, namely, a first power stage 310 (e.g., a boost power stage possibly employed to perform power factor correction) and a second power stage (e.g., an isolating dc-to-dc power stage) 320. The input power source 301 to the first power stage 310 is an ac power source, which is coupled to a diode bridge rectifier 303. The first power stage 310, controlled by controller 311, produces an internal regulated voltage Vbus across a capacitor C1, which provides the input voltage to the second power stage 320. The first power stage 310 includes boost power switch Qboost and diode D1, which alternately conduct to transfer charge from the input power source 301 through an inductor L1 to the capacitor C1. The controller 311 senses the rectified input voltage Vin and the internal bus voltage Vbus to control a duty cycle of the boost power switch Qboost, to regulate the bus voltage Vbus and to control the power factor of power drawn from the input power source 301.


The second power stage 320 includes isolation transformer TR and a power switch Qpri in series with the primary winding thereof. Synchronous rectifier switches Qfwd, Qfly are power switches coupled in series across a secondary winding of the isolation transformer TR to rectify the voltage therefrom, which winding voltage is coupled to an output filter including an output inductor Lout and an output capacitor Cout. The controller 311 provides control signals (e.g., gate control signals) VGfwd, VGfly to control the synchronous rectifier switches Qfwd, Qfly, respectively. A brief time delay ΔT between conduction intervals of the synchronous rectifier switches Qfwd, Qfly is provided by the controller 311 to prevent cross conduction therebetween. In a preferred embodiment, the controller 311 selects the time delay ΔT dependent on operating conditions of the power converter as described hereinbelow to provide improved power conversion efficiency.


Turning now to FIG. 4, illustrated are exemplary waveform diagrams to control the conduction intervals of selected power switches of the power converter of FIG. 3 with an intervening delay therebetween. More specifically, FIG. 4 illustrates an example of a time delay ΔT between the gate control signals VGfwd, VGfly to control the conduction intervals of the synchronous rectifier switches Qfwd, Qfly, respectively.


Returning now to the description of the power converter of FIG. 3, the output filter attenuates ac components present across the secondary winding of transformer TR to provide a substantially constant dc output voltage Vout. The output voltage Vout, as well as the load current Iload sensed by a sensor (e.g., a current sensing circuit element 315), is sensed by controller 311. Various circuit elements capable of sensing a load current, including a low resistance current-sensing resistor or a current-sensing transformer, are well known in the art and will not be described herein. Although the controller 311 is shown directly coupled to both sides of the isolation transformer TR, circuit elements to provide the necessary level of isolation for a controller 311 for a particular application are well known in the art and will not be described herein. A thermistor (or other suitable thermal sensor) 313 provides a temperature measurement to the controller 311 at a selected point(s) in or about the power converter. Typical points for temperature sensing include a location adjacent to a power switch or to an isolation transformer, and may include the ambient temperature outside the power converter itself. Although one thermistor 313 is illustrated in FIG. 3, a plurality of thermistors may also be included within the scope of the invention to provide multiple temperature measurements to the controller 311. The detailed operation and characteristics of the first and second power stages 310, 320 are well known in the art, and will not be further described herein.


The controller 311 in the exemplary power converter illustrated in FIG. 3 senses and is responsive to the rectified input voltage Vin, the internal bus voltage Vbus, the power converter output voltage Vout, the load current Iload, as well as a signal “Temp” representing a temperature using the thermistor 313. In addition, the controller 311 senses and is responsive to an external signal Vext indicating an environmental parameter from an external source such as a server powered by the power converter, and to a setup signal Vsetup that may provide the result of a parameter measured in a test fixture after a manufacturing step to set or otherwise tailor parameters for the operation of the controller 311. In a preferred embodiment, the controller 311 includes digital processing capability at least comparable to that of a low-end microprocessor (or other digital implementations, such as a microcontroller, digital signal processor, a field-programmable gate array, or complex programmable logic device), and is operative to adaptively improve (e.g., optimize) the efficiency of the power converter from a variety of data and signal sources.


The controller 311 is configured to augment the operating efficiency of the power converter in response to a sensed or signaled internal operating characteristic and/or an output characteristic, a power converter parameter measured after a manufacturing step, and a signal from an external source representing an environmental parameter obtained from an external source such as a signal from a server being powered. Exemplary environmental parameters obtained from an external source, which reflect how the power converter is being used in an application, include a signal indicating parallel operation with a second power converter, an indication that a paralleled power converter has failed, an indication that the power converter is supporting a critical application requiring a modified trade-off between power conversion efficiency and reliability, and an indication that the system is operating from a back-up power source, and may signal, for example, a lower limit for a dc bus voltage, reflecting a modified need for power converter holdover to accommodate altered statistics for a transient power outage condition.


The controller 311 may include a multidimensional table or other functional representation of a value to control an internal operating characteristic or an output characteristic of the power converter. Multidimensional inputs to such a table or other functional representation include signals representing an internal operating characteristic, an output operating characteristic, a power converter parameter measured after a manufacturing stage, a parameter measured on a representative power converter unit, and/or a signal representing an environmental parameter. There are references utilizing lookup tables and other multidimensional functional representations directed to automotive engine map and lookup table systems such as U.S. Pat. No. 5,925,088, entitled “Air-fuel Ratio Detecting Device and Method,” to Nasu, issued Jul. 20, 1999, U.S. Pat. No. 7,076,360, entitled “Auto-Ignition Timing Control and Calibration Method, to Ma, issued Jul. 11, 2006, and U.S. Pat. No. 6,539,299, entitled “Apparatus and Method for Calibrating an Engine Management System,” to Chatfield, et al., issued Mar. 25, 2003, which are incorporated herein by reference.


Turning now to FIGS. 5A and 5B, illustrated are diagrams of exemplary multidimensional tables for the time delays ΔT (in nanoseconds) for the gate control signals VGfwd, VGfly to control the conduction intervals of the synchronous rectifier switches Qfwd, Qfly, respectively, in accordance with a representative operating parameter of the power converter of FIG. 3. More specifically, FIG. 5A demonstrates the time delay ΔT with the input voltage Vin, being below about 48 volts and FIG. 5B demonstrates the time delay ΔT with the input voltage Vin being above about 48 volts. The tables, listing delay in nanoseconds between opening a first power switch and closing a second power switch (e.g., the synchronous rectifier switches Qfwd, Qfly) is accessed along a row with suitably quantized load current Iload, and along a column with suitably quantized temperature. The entries in the table are obtained by experimentally varying switch delay in a test set after manufacture of the power converter, and observing the effect of various delays on power conversion efficiency. The tables reflect a range of different values of input voltage Vin, measured for the particular power converter unit after a manufacturing stage. Of course, tables can be constructed with additional dimensions, accommodating additional parameters such as an output voltage Vout, and internal bus voltage Vbus, an input signal from an external source indicating an environmental parameter, etc., and finer levels of granularity. Various methods of interpolation between entries in the tables are well known in the art, and will not be described in the interest of brevity.


Such multidimensional tables can be used, for example, to control the switching frequency of a power converter. Switching frequency in the prior art is generally set as a design parameter, and is selected and fixed during a stage of design. The selected switching frequency is generally the result of a trade-off that considers, for example, the loss characteristics of the core material of the isolation transformer which depend on, without limitation, transformer core temperature, the primary-to-secondary turns ratio of the transformer, the expected thermal environment of the application, the heat transfer characteristics of the resulting power converter design, and the particular batch of core material from which the magnetic core thereof was formed. The resulting core loss for a particular power converter unit can also be substantially dependent on core characteristics such as a flux gap and core area of the particular core that was installed, all of which are substantially unknown before the power converter is manufactured.


In addition, the selected switching frequency is a result of consideration of other frequency dependent losses within the power converter. For example, gate drive losses are generally proportional to switching frequency and depend on the particular manufacturing run of power switches employed therein. Thus, altering the switching frequency for a particular application using a table constructed according to the principles of the present invention, considering manufacturing data, actual load current, and other measured or sensed variables can result in improved power conversion efficiency within a predetermined set of operating constraints that may be signaled from an external source. A test set can be readily constructed, as is well known in the art, to vary switching frequency and observe the effect on power conversion efficiency. Entries are then made in the table to represent preferable switching frequencies. Static efficiency optimization approaches of the prior art that use a predetermined curve or other fixed approach do not advantageously achieve the benefits of improved efficiency with greater flexibility to respond to additional data as described herein.


Turning now to FIG. 6, illustrated is an embodiment of a functional representation to improve power conversion efficiency constructed according to the principles of the present invention by determining a controllable parameter such as an internal bus voltage setpoint Vbussetpoint of the power converter. An exemplary function is represented dependent on load current Iload, operating temperature, data acquired after a manufacturing step, and data from an external source. The exemplary functional dependence illustrated in FIG. 6 for the internal bus voltage setpoint Vbussetpoint for an internal bus voltage is:

Vbussetpoint=380+0.1·Iload−0.2·Temp+Vsetup+1·Vext,

where “Iload” represents a sensed power converter load current, “Temp” represents a sensed temperature using a thermistor or other temperature sensing element for a location in or about the power converter, “Vsetup” represents a correction constant obtained from a test set after a manufacturing step, and “Vext” represents a signal from an external source that might assume the values 0 and 1 to indicate the presence or absence of a paralleled power converter (see, e.g., FIG. 3 and the related description therefore). A constant “380” is a nominal number to describe the internal bus voltage setpoint Vbussetpoint. Other functional relationships including combinations of curve fits or other algorithmic relationships can be used within the broad scope of the present invention to meet the needs of a particular application. The controller 311 illustrated in FIG. 3 may use the internal bus voltage setpoint Vbussetpoint as a reference voltage to control the internal bus voltage Vbus illustrated and described with reference to FIG. 3.


The use of tables, functional relationships, and curve fits to control an operating parameter for a controller of a power converter, constructed according to the principles of the present invention, can advantageously use the extensive data ordinarily acquired by test fixtures at various stages of the manufacturing process. Such test fixtures are generally configured to sweep a broad range of operating conditions for a particular power converter unit, or from a representative power converter unit, or from power converter units produced during a run of representative power converter units, and can even operate the power converter unit over a range of temperatures and for an extended period of time (e.g., during “burn in”). A test fixture can be arranged to operate a power converter over a range of trial values for a controllable parameter, and select a value that provides a preferable operating efficiency for the particular power converter under test. Thus, the efficiency program for a particular power converter can be tailored to represent the particular characteristics of the individual components from which the power converter unit is built. In a preferred arrangement, the test fixture is programmed to automatically search for the best value for the controllable parameter.


It is recognized that the timescale for the response of a controller to different internal and external stimuli can preferably be different. For example, the voltage level of an internal bus, which generally depends on charging and discharging a capacitor, might be practically changed over a period of hundreds of milliseconds, or even seconds, whereas the switching frequency of a power conversion stage or the timing delay between power switch conduction intervals can be readily changed on a much faster time scale, ultimately on a cycle-by-cycle basis. It may even be inappropriate to substantially change operating parameters such as an internal bus voltage level over intervals of time shorter than several seconds. Some internal operating characteristics or parameters would inherently change or would be inherently varied over a relatively long period, such as the input current of an ac front end, compared to other time scales within a power converter, and require a period of time to sense or alter an average or peak value. Such internal parameters may be monitored over a longer time interval before the controller responds to a change in an internal operating characteristic or an output characteristic to augment power conversion efficiency. Thus, for example, a controller may control an internal operating characteristic of a power converter in a step-by-step manner during an efficiency optimization process on a time scale substantially different from a time scale for controlling the duty cycle of the power converter. A parameter can be controlled on a slow timescale by using a digital representation of a low pass filter to retard changes in a parameter. An exemplary equation representing a low pass filter implemented over discrete time steps is:

Vbus,n=(1−τ)·Vbus,n-1+τ·Vbus,desired

where “Vbus,n” represents a filtered bus reference voltage at time step “n” to control an internal bus voltage on a slow time scale, “τ” represents a parameter that sets the time scale for the filtering process, “Vbus,n-1” represents the filtered bus reference voltage at the previous time step “n-1,” and “Vbus,desired” represents a desired, optimized bus voltage produced by a functional relationship or a table as described hereinabove.


In a related embodiment, a controller for a power converter may optimize the operating efficiency (or other desirable parameter) of the power converter in response to a sensed or signaled internal operating characteristic and/or an output characteristic, using parameters measured on a representative power converter. For example, a multidimensional table or other functional representation of a value to control an internal operating characteristic or an output characteristic of the power converter could be derived from testing one or more representative power converters, as opposed to testing the actual power converter to be controlled. Multidimensional inputs to such a table or other functional representation may include, without limitation, signals representing an internal operating characteristic, an output operating characteristic, a power converter parameter measured during a test or characterization phase, and/or a signal representing an environmental parameter.


During a typical power converter product development process, a product design may proceed through several stages, for example, prototyping, pilot (or small volume) production, characterization and/or qualification testing, safety agency and electromagnetic interference (“EMI”) compliance testing, highly accelerated life testing, highly accelerated stress screening, and final release to production. During the characterization and/or qualification testing phase, one or more representative power supplies may be subjected to extensive testing to ensure compliance with the end specification. This testing may be automated by one or more racks of automated test equipment, enabling possibly many thousands of individual tests to be performed.


During an exemplary characterization testing stage, a representative power converter may be extensively tested over a wide variety of operating conditions. Such a characterization test may measure and collect thousands, or tens of thousands of individual data points. These data may then be compiled into one or more multidimensional tables or other functional representation(s) and used by the control circuit to adjust an internal operating characteristic or an output characteristic of the power converter in order to operate the power converter at or near an optimal efficiency for a given set of conditions, while still enabling the power converter to meet its required specification.


Turning now to FIG. 7, illustrated is a block diagram of an embodiment of a power converter constructed according to the principles of the present invention. In the exemplary embodiment illustrated in FIG. 7, a block diagram of an ac input, power factor correction, dc output power converter is depicted. The power converter operates from a power source providing 85 to 264 V ac input, and provides outputs of +12V and 3.3 VSB (a standby voltage). The power converter also provides output signals PS_ON and POK indicating, respectively, that the power converter is turned on and power is “OK,” as well as other “communications” signals typically provided between a power converter and a host system. It is readily understood by those skilled in the art that there are many ways to design an ac-to-dc power converter, and correspondingly there are many possible block diagrams that could suitably depict an exemplary power converter. It is also understood that the spirit and scope of the present invention is not limited to ac-to-dc power converters, but may encompass any type of power converter, including ac and/or dc input, as well as ac and/or dc output. Multiple input and/or multiple output power converters are also within the spirit and scope of the present invention.



FIG. 7 illustrates many of the constituent blocks of a power converter that may be controlled, as well as many of the internal nodes that may be measured and/or controlled to improve operating efficiency. For example, a switching frequency of the boost field-effect transistors (“FETs”), and/or the bridge, may be adjusted based on operating conditions to improve efficiency. Additionally, the voltage on the 400V bus may be adjusted, or the timing between bridge switches and a synchronous rectifier device (“sync rect”) may be adjusted.


Turning now to FIG. 8, illustrated is a block diagram of an embodiment of a power converter (e.g., an ac-to-dc power converter) constructed according to the principles of the present invention and demonstrating in more detail possible control and alarm circuit connections. These control and alarm circuits may be realized using dedicated firmware-driven microcontrollers, digital control integrated circuits, application specific integrated circuits, field-programmable gate arrays, or any suitable electronic circuitry. The power factor correction (“PFC”) control and primary alarm blocks (part of the primary control) of FIG. 8 illustrate some of the many internal nodes and circuits that may be measured and controlled. For example, the primary controller may monitor the input line voltage, frequency, and current, etc. It may also monitor the PFC output bus voltage (shown here as the 400V bus, although the bus voltage may be controlled to other voltage levels). The primary controller may control the PFC boost power switches using a variety of control techniques, including fixed and variable frequency, continuous current mode, discontinuous current mode, or critically continuous inductor current, to name but a few. The power converter could also employ additional components to achieve, for example, soft switching, with the controller capable of measuring and/or altering operating parameters affecting these additional components. The primary controller may also be capable of communicating with a secondary controller, and this communication may be bidirectional.


The secondary controller, including the pulse-width modulation (“PWM”) control and alarm circuits, may monitor and control the parameters shown in FIG. 8, as well as others not shown. The secondary control can thus be used to control, among other things, switching frequency, operating mode, output voltage, timing relationships, etc. The secondary control may advantageously also enable or disable the operation of individual power switches (or banks of power switches) to improve power conversion efficiency. The illustrated embodiment of FIG. 8 also shows a means of communication allowing the power converter to communicate with a wide variety of devices, including but not limited to, a host processor, one or more pieces of automated test equipment, or another power converter. The communication protocol in the illustrated embodiment is a wired I2C bus, but could be realized with any suitable communication means or protocol, including wired and wireless, optical, radio frequency, etc. Additionally, the communications means need not be restricted to the secondary side, but may be located on the primary side, or be on both primary and secondary sides.


Turning now to FIGS. 9A thru 9F, illustrated are examples of how power converter efficiency can vary as a function of operating conditions and operating environment in accordance with the principles of the present invention. These curves in FIGS. 9A thru 9F are merely illustrative of a few of the parameters or environmental conditions affecting power conversion efficiency, and are by no means meant to be exhaustive. In addition, the curve shapes and variations illustrated in FIGS. 9A thru 9F are meant for illustrative purposes only. The efficiency of different power converter designs may vary in a manner different from the exemplary curves.


In FIG. 9A, the efficiency of the PFC section is illustrated as a function of both output power and input line voltage. In FIGS. 9A thru 9F, the arrows point in the direction of an increasing parameter. In FIG. 9B, the efficiency of the dc-to-dc section is illustrated as a function of both output power and bus voltage. In FIG. 9C, the efficiency of the PFC section is illustrated as a function of both output power and switching frequency at a single line voltage. A family of such curves could be generated at different ac line voltages. In FIG. 9D, the efficiency of the dc-to-dc section is illustrated as a function of both output power and switching frequency at a single bus voltage. A family of such curves could be generated at different dc bus voltages. In FIG. 9E, the efficiency of the power converter (PFC plus dc-to-dc sections) is illustrated as a function of both output power and bus voltage at a single line voltage. A family of such curves could be generated at different ac line voltages. Lastly, in FIG. 9F, the efficiency of the power converter (PFC plus dc-to-dc sections) is illustrated as a function of both output power and the timing delay between the bridge and synchronous rectifier switches, at a single line voltage. A family of such curves could be generated at different ac line voltages. Clearly, many other relationships could be measured for their effect on power converter efficiency, including but not limited to, temperature (internal and/or external), altitude, fan speed, number of power switching devices enabled, etc.


The number of different relationships that could be measured and data points collected is limited only by the ingenuity of the test engineer, time, and data memory resources. Over many such projects, an engineer may learn that certain relationship data has more of an impact on efficiency than others, and may learn how to intelligently limit the number of tests performed and data points collected to only those relationships having the greatest effect on efficiency.


Once the data is collected on one or more representative power converter units, multidimensional data table(s) or other functional representation(s) may be stored into the power converter's internal control memory for use during operation. This stored data could comprise, for example, a look-up table, an algorithm, or any other suitable method of converting test data into an actionable control parameter. For example, assume an exemplary power converter constructed according to the principles of the present invention were operating in a server, perhaps in a data center. The exemplary power converter may measure one or more environmental and operating conditions. The power converter may determine that it is operating at 20% load, at 120V ac input at 59.9 Hz, with an inlet ambient temperature of 35° C. (other parameters could also be measured). The primary and/or secondary controller(s) may then access a stored look-up table that specifies, for example, the proper switching frequency, bus voltage operating conditions, and switch timing relationships in order to improve or optimize efficiency. The controllers may be programmed to wait for a predetermined amount of time at a given operating condition before making any adjustment. This type of delay could allow the power converter to avoid making an unnecessarily large number of adjustments.


It may be advantageous to limit the range of possible adjustments to only those values that allow the power converter to remain within specified operating requirements during any operating condition specified in a requirements document. It may also be advantageous to limit the range of possible adjustments to only those values that ensure that the components of the power converter do not exceed maximum stress levels, thereby improving reliability and reducing component or power converter failures. For example, a requirements document for a power converter may specify operation under a number of transient conditions, such as output load transients, input transients, brown-out conditions, line drop-out conditions, temperature transients, etc.


Turning now to FIG. 10, illustrated is an ac input voltage waveform including an exemplary input line voltage dropout transient, showing time histories of possible internal bus voltages in accordance with the principles of the present invention. The FIGURE shows time histories of possible internal bus voltages, and an ac input voltage waveform with a drop-out period 1003 during which no ac input voltage is present. Illustrated for the internal bus voltages, is a portion in which the slope 1001 of the internal bus voltage is load dependent. Also illustrated in the FIGURE is a bus undervoltage limit 1002. Power converters are often required to continue to provide output power for a period of time with the ac input voltage at or near zero. This time is typically referred to as the holdup time. When the input line voltage drops out, the dc-to-dc power converter section (see, e.g., FIG. 3) will continue to operate, pulling energy from the holdup capacitors, thereby reducing the voltage on the bus (Vbus). The bus voltage will continue to fall until the line voltage is restored. Note that the slope of the bus voltage will be steeper at a higher output load current. If the bus voltage is allowed to reduce below an under voltage limit, the dc-to-dc power converter will not be able to support the load and maintain regulation, thereby resulting in an out-of-specification condition. If the exemplary power converter of FIG. 10 is operating at bus voltage “1,” the power converter can operate within specification, but may be operating at a lower efficiency than desired. If, however, the power converter adjusted its bus voltage to bus voltage “2” in an effort to improve efficiency, the bus voltage will dip below the undervoltage limit before the end of the drop-out period.


A power converter constructed according to the principles of the present invention may sense a variety of input/output operating parameters, and could thus calculate, for example, the minimum (or a safe) bus voltage that could both improve efficiency and ensure that the power converter can maintain the proper holdup time through a line dropout event. This is illustrated by “bus voltage 3” in FIG. 10. For a given output load condition, adjusting the bus voltage to “bus voltage 3” both improves efficiency and ensures compliance with the specification. Thus, the exemplary power converter is capable of using a multidimensional data table(s) or other functional representation(s), in conjunction with sensed operating parameters, to determine an operating point with improved efficiency that also allows the power converter to maintain compliance with a specification.


There are many examples where adjustments to improve efficiency while maintaining compliance with a specification will require a power converter to make intelligent adjustments, possibly combining data stored in a multidimensional data table(s) or other functional representation(s) with sensed operating parameters in the adjustment computation. One such example concerns switching frequency adjustments. It may be advantageous to reduce a switching frequency under, for example, lighter output load conditions. However, if the load were to suddenly increase, the power converter controller must ensure that the magnetic components will not be detrimentally affected (by possibly saturating) at the combination of a higher load condition and a lower frequency operating condition, prior to the controller adjusting the switching frequency to a level more appropriate with the new load condition.


Another example can be found in switch timing adjustments, illustrated in FIG. 9F. Such improved switch timing is often dependant on input or output current levels. For example, switch timing to improve efficiency at lighter load may result in cross conduction at heavier loads (or vice versa), thereby causing detrimental operation and possible failure of the power converter.


Thus, a controller for a power converter that provides improved power conversion efficiency has been introduced. Those skilled in the art should understand that the previously described embodiments of a controller for a power converter and related methods are submitted for illustrative purposes only. Those skilled in the art understand further that various changes, substitutions, and alterations can be made to the controller without departing from the spirit and scope of the invention in its broadest form. In addition, other embodiments capable of providing the advantages as described hereinabove are well within the broad scope of the present invention. While the controller and method have been described as providing advantages in the environment of a power converter, other applications therefor such as a controller for a motor or other electromechanical device are well within the broad scope of the present invention.


For a better understanding of power electronics, see “Principles of Power Electronics,” by J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Addison-Wesley (1991). For a better understanding of semiconductor devices and processes, see “Fundamentals of III-V Devices,” by William Liu, John Wiley and Sons, (1999). For a better understanding of gallium arsenide processing, see “Modern GaAs Processing Methods,” by Ralph Williams, Artech House, Second Ed. (1990). The aforementioned references are incorporated herein by reference.


Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the controllers discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof, to form the devices providing improved efficiency for a power converter as described herein.


Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims
  • 1. A power converter including a power switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof, comprising: a controller configured to provide a signal to control said duty cycle of said power switch as a function of said output characteristic, said controller configured to regulate an internal operating characteristic of said power converter on a time scale different from a time scale for controlling said duty cycle of said power switch and depending on a value of one of a parameter of said power converter measured after a manufacturing step and an environmental parameter for said power converter.
  • 2. The power converter as recited in claim 1 wherein said controller is configured to regulate said internal operating characteristic of said power converter in accordance with a table with entries dependent on a value of one of said parameter of said power converter measured after said manufacturing step and said environmental parameter for said power converter.
  • 3. The power converter as recited in claim 1 wherein said internal operating characteristic is one of an internal bus voltage, a voltage level of a drive signal for said power switch, a number of paralleled power switches selectively enabled to conduct, a temperature of a component part, or a switching frequency of said power converter.
  • 4. The power converter as recited in claim 1 wherein said controller is configured to regulate said internal operating characteristic of said power converter in accordance with a functional relationship dependent on a value of one of said parameter of said power converter measured after said manufacturing step and said environmental parameter for said power converter.
  • 5. The power converter as recited in claim 1 wherein said environmental parameter is received as a signal from an external source.
  • 6. The power converter as recited in claim 1 wherein said internal operating characteristic is configured to be regulated by said controller on a slower time scale from said time scale for controlling said duty cycle of said power.
  • 7. The power converter as recited in claim 1 wherein said parameter of said power converter measured after said manufacturing step is automatically measured in a test fixture.
  • 8. The power converter as recited in claim 1 wherein said parameter of said power converter measured after said manufacturing step is a parameter measured from a representative power converter.
  • 9. The power converter as recited in claim 1 wherein said controller is configured to regulate said internal operating characteristic of said power converter in a step-by-step manner during an efficiency optimization process.
  • 10. The power converter as recited in claim 1 wherein said controller is configured to regulate said internal operating characteristic of said power converter in a step-by-step manner during an efficiency optimization process on a slower time scale from said time scale for controlling said duty cycle of said power converter.
  • 11. A method of controlling a power converter including a power switch configured to conduct for a duty cycle and provide a regulated output characteristic at an output thereof, comprising: providing a signal to control said duty cycle of said power switch as a function of said output characteristic, thereby regulating an internal operating characteristic of said power converter on a time scale different from a time scale for controlling said duty cycle of said power switch and depending on a value of one of a parameter of said power converter measured after a manufacturing step and an environmental parameter for said power converter.
  • 12. The method as recited in claim 11 wherein said method regulates said internal operating characteristic of said power converter in accordance with a table with entries dependent on a value of one of said parameter of said power converter measured after said manufacturing step and said environmental parameter for said power converter.
  • 13. The method as recited in claim 11 wherein said internal operating characteristic is one of an internal bus voltage, a voltage level of a drive signal for said power switch, a number of paralleled power switches selectively enabled to conduct, a temperature of a component part, or a switching frequency of said power converter.
  • 14. The method as recited in claim 11 wherein said method regulates said internal operating characteristic of said power converter in accordance with a functional relationship dependent on a value of one of said parameter of said power converter measured after said manufacturing step and said environmental parameter for said power converter.
  • 15. The method as recited in claim 11 wherein said environmental parameter is received as a signal from an external source.
  • 16. The method as recited in claim 11 wherein said internal operating characteristic is regulated on a slower time scale from said time scale for controlling said duty cycle of said power switch.
  • 17. The method as recited in claim 11 wherein said parameter of said power converter measured after said manufacturing step is automatically measured in a test fixture.
  • 18. The method as recited in claim 11 wherein said parameter of said power converter measured after said manufacturing step is a parameter measured from a representative power converter.
  • 19. The method as recited in claim 11 wherein said method regulates said internal operating characteristic of said power converter in a step-by-step manner during an efficiency optimization process.
  • 20. The method as recited in claim 11 wherein said method regulates said internal operating characteristic of said power converter in a step-by-step manner during an efficiency optimization process on a slower time scale from said time scale for controlling said duty cycle of said power converter.
Parent Case Info

This application is a continuation of and claims priority to U.S. patent application Ser. No. 11/607,325, entitled “Power Converter with an Adaptive Controller and Method of Operating the Same,” filed on Dec. 1, 2006 (now, U.S. Pat. No. 7,675,758).

US Referenced Citations (497)
Number Name Date Kind
1376978 Stoekle May 1921 A
2387943 Putman Oct 1945 A
2473662 Pohm Jun 1949 A
3007060 Guenther Oct 1961 A
3346798 Dinger Oct 1967 A
3358210 Grossoehme Dec 1967 A
3433998 Woelber Mar 1969 A
3484562 Kronfeld Dec 1969 A
3553620 Cielo et al. Jan 1971 A
3602795 Gunn Aug 1971 A
3622868 Todt Nov 1971 A
3681679 Chung Aug 1972 A
3708742 Gunn Jan 1973 A
3708744 Stephens et al. Jan 1973 A
4011498 Hamstra Mar 1977 A
4019122 Ryan Apr 1977 A
4075547 Wroblewski Feb 1978 A
4202031 Hesler et al. May 1980 A
4257087 Cuk Mar 1981 A
4274071 Pfarre Jun 1981 A
4327348 Hirayama Apr 1982 A
4471423 Hase Sep 1984 A
4499481 Greene Feb 1985 A
4570174 Huang et al. Feb 1986 A
4577268 Easter et al. Mar 1986 A
4581691 Hock Apr 1986 A
4613841 Roberts Sep 1986 A
4636823 Margalit et al. Jan 1987 A
4660136 Montorefano Apr 1987 A
4770667 Evans et al. Sep 1988 A
4770668 Skoultchi et al. Sep 1988 A
4780653 Bezos et al. Oct 1988 A
4785387 Lee et al. Nov 1988 A
4799138 Chahabadi et al. Jan 1989 A
4803609 Gillett et al. Feb 1989 A
4823249 Garcia, II Apr 1989 A
4837496 Erdi Jun 1989 A
4866367 Ridley et al. Sep 1989 A
4887061 Matsumura Dec 1989 A
4899271 Seiersen Feb 1990 A
4903089 Hollis et al. Feb 1990 A
4922400 Cook May 1990 A
4962354 Visser et al. Oct 1990 A
4964028 Spataro Oct 1990 A
4999759 Cavagnolo et al. Mar 1991 A
5003277 Sokai et al. Mar 1991 A
5014178 Balakrishnan May 1991 A
5027264 DeDoncker et al. Jun 1991 A
5055991 Carroll Oct 1991 A
5068756 Morris et al. Nov 1991 A
5106778 Hollis et al. Apr 1992 A
5126714 Johnson Jun 1992 A
5132888 Lo et al. Jul 1992 A
5134771 Lee et al. Aug 1992 A
5172309 DeDoncker et al. Dec 1992 A
5177460 Dhyanchand et al. Jan 1993 A
5182535 Dhyanchand Jan 1993 A
5204809 Andresen Apr 1993 A
5206621 Yerman Apr 1993 A
5208739 Sturgeon May 1993 A
5223449 Morris et al. Jun 1993 A
5225971 Spreen Jul 1993 A
5231037 Yuan et al. Jul 1993 A
5244829 Kim Sep 1993 A
5262930 Hua et al. Nov 1993 A
5282126 Husgen Jan 1994 A
5285396 Aoyama Feb 1994 A
5291382 Cohen Mar 1994 A
5303138 Rozman Apr 1994 A
5305191 Loftus, Jr. Apr 1994 A
5335163 Seiersen Aug 1994 A
5336985 McKenzie Aug 1994 A
5342795 Yuan et al. Aug 1994 A
5343140 Gegner Aug 1994 A
5353001 Meinel et al. Oct 1994 A
5369042 Morris et al. Nov 1994 A
5374887 Drobnik Dec 1994 A
5399968 Sheppard et al. Mar 1995 A
5407842 Morris et al. Apr 1995 A
5453923 Scalais et al. Sep 1995 A
5459652 Faulk Oct 1995 A
5468661 Yuan et al. Nov 1995 A
5477175 Tisinger et al. Dec 1995 A
5508903 Alexndrov Apr 1996 A
5523673 Ratliff et al. Jun 1996 A
5539630 Pietkiewicz et al. Jul 1996 A
5554561 Plumton Sep 1996 A
5555494 Morris Sep 1996 A
5581224 Yamaguchi Dec 1996 A
5610085 Yuan et al. Mar 1997 A
5624860 Plumton et al. Apr 1997 A
5636116 Milavec et al. Jun 1997 A
5661642 Shimashita Aug 1997 A
5663876 Newton et al. Sep 1997 A
5671131 Brown Sep 1997 A
5700703 Huang et al. Dec 1997 A
5712189 Plumton et al. Jan 1998 A
5719544 Vinciarelli et al. Feb 1998 A
5734564 Brkovic Mar 1998 A
5736842 Jovanovic Apr 1998 A
5742491 Bowman et al. Apr 1998 A
5747842 Plumton May 1998 A
5756375 Celii et al. May 1998 A
5760671 Lahr et al. Jun 1998 A
5783984 Keuneke Jul 1998 A
5784266 Chen Jul 1998 A
5804943 Kollman et al. Sep 1998 A
5815383 Lei Sep 1998 A
5815386 Gordon Sep 1998 A
5864110 Moriguchi et al. Jan 1999 A
5870296 Schaffer Feb 1999 A
5870299 Rozman Feb 1999 A
5880942 Leu Mar 1999 A
5886508 Jutras Mar 1999 A
5889298 Plumton et al. Mar 1999 A
5889660 Taranowski et al. Mar 1999 A
5900822 Sand et al. May 1999 A
5907231 Watanabe et al. May 1999 A
5907481 Svardsjo May 1999 A
5909110 Yuan et al. Jun 1999 A
5910665 Plumton et al. Jun 1999 A
5920475 Boylan et al. Jul 1999 A
5925088 Nasu Jul 1999 A
5929665 Ichikawa et al. Jul 1999 A
5933338 Wallace Aug 1999 A
5940287 Brkovic Aug 1999 A
5946207 Schoofs Aug 1999 A
5956245 Rozman Sep 1999 A
5956578 Weitzel et al. Sep 1999 A
5959850 Lim Sep 1999 A
5977853 Ooi et al. Nov 1999 A
5982640 Naveed Nov 1999 A
5999066 Saito et al. Dec 1999 A
5999429 Brown Dec 1999 A
6003139 McKenzie Dec 1999 A
6008519 Yuan et al. Dec 1999 A
6011703 Boylan et al. Jan 2000 A
6038154 Boylan et al. Mar 2000 A
6046664 Weller et al. Apr 2000 A
6055166 Jacobs et al. Apr 2000 A
6060943 Jansen May 2000 A
6067237 Nguyen May 2000 A
6069798 Liu May 2000 A
6069799 Bowman et al. May 2000 A
6078510 Spampinato et al. Jun 2000 A
6084792 Chen et al. Jul 2000 A
6094038 Lethellier Jul 2000 A
6097046 Plumton Aug 2000 A
6125046 Jang et al. Sep 2000 A
6144187 Bryson Nov 2000 A
6147886 Wittenbreder Nov 2000 A
6156611 Lan et al. Dec 2000 A
6160374 Hayes Dec 2000 A
6160721 Kossives et al. Dec 2000 A
6163466 Davila, Jr. et al. Dec 2000 A
6181231 Bartilson Jan 2001 B1
6188586 Farrington et al. Feb 2001 B1
6191964 Boylan et al. Feb 2001 B1
6208535 Parks Mar 2001 B1
6215290 Yang et al. Apr 2001 B1
6218891 Lotfi et al. Apr 2001 B1
6229197 Plumton et al. May 2001 B1
6262564 Kanamori Jul 2001 B1
6288501 Nakamura et al. Sep 2001 B1
6288920 Jacobs et al. Sep 2001 B1
6295217 Yang et al. Sep 2001 B1
6304460 Cuk Oct 2001 B1
6309918 Huang et al. Oct 2001 B1
6317021 Jansen Nov 2001 B1
6317337 Yasumura Nov 2001 B1
6320490 Clayton Nov 2001 B1
6323090 Zommer Nov 2001 B1
6325035 Codina et al. Dec 2001 B1
6344986 Jain et al. Feb 2002 B1
6345364 Lee Feb 2002 B1
6348848 Herbert Feb 2002 B1
6351396 Jacobs Feb 2002 B1
6356462 Jang et al. Mar 2002 B1
6362986 Schultz et al. Mar 2002 B1
6373727 Hedenskog et al. Apr 2002 B1
6373734 Martinelli Apr 2002 B1
6380836 Matsumoto et al. Apr 2002 B2
6388898 Fan et al. May 2002 B1
6392902 Jang et al. May 2002 B1
6396718 Ng et al. May 2002 B1
6400579 Cuk Jun 2002 B2
6414578 Jitaru Jul 2002 B1
6418039 Lentini et al. Jul 2002 B2
6438009 Assow Aug 2002 B2
6445598 Yamada Sep 2002 B1
6462965 Uesono Oct 2002 B1
6466461 Mao et al. Oct 2002 B2
6469564 Jansen Oct 2002 B1
6477065 Parks Nov 2002 B2
6483724 Blair et al. Nov 2002 B1
6489754 Blom Dec 2002 B2
6498367 Chang et al. Dec 2002 B1
6501193 Krugly Dec 2002 B1
6504321 Giannopoulos et al. Jan 2003 B2
6512352 Qian Jan 2003 B2
6525603 Morgan Feb 2003 B1
6539299 Chatfield et al. Mar 2003 B2
6545453 Glinkowski et al. Apr 2003 B2
6548992 Alcantar et al. Apr 2003 B1
6549436 Sun Apr 2003 B1
6552917 Bourdillon Apr 2003 B1
6570268 Perry et al. May 2003 B1
6580627 Toshio Jun 2003 B2
6597588 Matsumoto Jul 2003 B2
6597592 Carsten Jul 2003 B2
6608768 Sula Aug 2003 B2
6611132 Nakagawa et al. Aug 2003 B2
6614206 Wong et al. Sep 2003 B1
6636025 Irissou Oct 2003 B1
6654259 Koshita et al. Nov 2003 B2
6661276 Chang Dec 2003 B1
6668296 Dougherty et al. Dec 2003 B1
6674658 Mao et al. Jan 2004 B2
6683797 Zaitsu et al. Jan 2004 B2
6687137 Yasumura Feb 2004 B1
6696910 Nuytkens et al. Feb 2004 B2
6731486 Holt et al. May 2004 B2
6741099 Krugly May 2004 B1
6751106 Zhang et al. Jun 2004 B2
6753723 Zhang Jun 2004 B2
6765810 Perry Jul 2004 B2
6775159 Webb et al. Aug 2004 B2
6784644 Xu et al. Aug 2004 B2
6804125 Brkovic Oct 2004 B2
6813170 Yang Nov 2004 B2
6831847 Perry Dec 2004 B2
6856149 Yang Feb 2005 B2
6862194 Yang et al. Mar 2005 B2
6867678 Yang Mar 2005 B2
6867986 Amei Mar 2005 B2
6873237 Chandrasekaran et al. Mar 2005 B2
6882548 Jacobs et al. Apr 2005 B1
6906934 Yang et al. Jun 2005 B2
6943553 Zimmermann et al. Sep 2005 B2
6944033 Xu et al. Sep 2005 B1
6977824 Yang et al. Dec 2005 B1
6980077 Chandrasekaran et al. Dec 2005 B1
6982887 Batarseh et al. Jan 2006 B2
7009486 Goeke et al. Mar 2006 B1
7012414 Mehrotra et al. Mar 2006 B1
7016204 Yang et al. Mar 2006 B2
7023679 Tomiyama Apr 2006 B2
7026807 Anderson et al. Apr 2006 B2
7034586 Mehas et al. Apr 2006 B2
7034647 Yan et al. Apr 2006 B2
7046523 Sun et al. May 2006 B2
7061358 Yang Jun 2006 B1
7072189 Kim et al. Jul 2006 B2
7075799 Qu Jul 2006 B2
7076360 Ma Jul 2006 B1
7095638 Uusitalo Aug 2006 B2
7098640 Brown Aug 2006 B2
7099163 Ying Aug 2006 B1
7148669 Maksimovic et al. Dec 2006 B2
7170268 Kim Jan 2007 B2
7176662 Chandrasekaran Feb 2007 B2
7209024 Nakahori Apr 2007 B2
7269038 Shekhawat et al. Sep 2007 B2
7280026 Chandrasekaran et al. Oct 2007 B2
7285807 Brar et al. Oct 2007 B2
7298118 Chandrasekaran Nov 2007 B2
7301785 Yasumura Nov 2007 B2
7312686 Bruno Dec 2007 B2
7321283 Mehrotra et al. Jan 2008 B2
7332992 Iwai Feb 2008 B2
7339208 Brar et al. Mar 2008 B2
7339801 Yasumura Mar 2008 B2
7348612 Sriram et al. Mar 2008 B2
7362592 Yang et al. Apr 2008 B2
7362593 Yang et al. Apr 2008 B2
7375607 Lee et al. May 2008 B2
7375994 Andreycak May 2008 B2
7385375 Rozman Jun 2008 B2
7386404 Cargonja et al. Jun 2008 B2
7417875 Chandrasekaran et al. Aug 2008 B2
7427910 Mehrotra et al. Sep 2008 B2
7431862 Mehrotra et al. Oct 2008 B2
7439556 Brar et al. Oct 2008 B2
7439557 Brar et al. Oct 2008 B2
7446512 Nishihara et al. Nov 2008 B2
7447049 Garner et al. Nov 2008 B2
7462891 Brar et al. Dec 2008 B2
7468649 Chandrasekaran Dec 2008 B2
7471523 Yang Dec 2008 B2
7471527 Chen Dec 2008 B2
7489225 Dadafshar Feb 2009 B2
7499295 Indika de Silva et al. Mar 2009 B2
7541640 Brar et al. Jun 2009 B2
7554430 Mehrotra et al. Jun 2009 B2
7558037 Gong et al. Jul 2009 B1
7558082 Jitaru Jul 2009 B2
7567445 Coulson et al. Jul 2009 B2
7583555 Kang et al. Sep 2009 B2
7626370 Mei et al. Dec 2009 B1
7630219 Lee Dec 2009 B2
7633369 Chandrasekaran et al. Dec 2009 B2
7663183 Brar et al. Feb 2010 B2
7667986 Artusi et al. Feb 2010 B2
7675758 Artusi et al. Mar 2010 B2
7675759 Artusi et al. Mar 2010 B2
7675764 Chandrasekaran et al. Mar 2010 B2
7715217 Manabe et al. May 2010 B2
7733679 Luger et al. Jun 2010 B2
7746041 Xu et al. Jun 2010 B2
7778050 Yamashita Aug 2010 B2
7778051 Yang Aug 2010 B2
7787264 Yang et al. Aug 2010 B2
7791903 Zhang et al. Sep 2010 B2
7795849 Sohma Sep 2010 B2
7813101 Morikawa Oct 2010 B2
7847535 Meynard et al. Dec 2010 B2
7889517 Artusi et al. Feb 2011 B2
7889521 Hsu Feb 2011 B2
7906941 Jayaraman et al. Mar 2011 B2
7940035 Yang May 2011 B2
7965528 Yang et al. Jun 2011 B2
7983063 Lu et al. Jul 2011 B2
8004112 Koga et al. Aug 2011 B2
8134443 Chandrasekaran et al. Mar 2012 B2
8179699 Tumminaro et al. May 2012 B2
8184456 Jain et al. May 2012 B1
8278889 Tateishi Oct 2012 B2
8467199 Lee et al. Jun 2013 B2
8488355 Berghegger Jul 2013 B2
8520414 Garrity et al. Aug 2013 B2
8520420 Jungreis et al. Aug 2013 B2
8638578 Zhang Jan 2014 B2
8643222 Brinlee et al. Feb 2014 B2
8767418 Jungreis et al. Jul 2014 B2
8787043 Berghegger Jul 2014 B2
8792256 Berghegger Jul 2014 B2
8792257 Berghegger Jul 2014 B2
8976549 Berghegger Mar 2015 B2
20010020886 Matsumoto et al. Sep 2001 A1
20010024373 Cuk Sep 2001 A1
20010055216 Shirato Dec 2001 A1
20020044463 Bontempo et al. Apr 2002 A1
20020057080 Telefus et al. May 2002 A1
20020071295 Nishikawa Jun 2002 A1
20020101741 Brkovic Aug 2002 A1
20020110005 Mao et al. Aug 2002 A1
20020114172 Webb et al. Aug 2002 A1
20020121647 Taylor Sep 2002 A1
20020126512 Nakagawa et al. Sep 2002 A1
20020167385 Ackermann Nov 2002 A1
20020176262 Tripathi et al. Nov 2002 A1
20030026115 Miyazaki Feb 2003 A1
20030039129 Miyazaki et al. Feb 2003 A1
20030063483 Carsten Apr 2003 A1
20030063484 Carsten Apr 2003 A1
20030076079 Alcantar et al. Apr 2003 A1
20030086279 Bourdillon May 2003 A1
20030197585 Chandrasekaran et al. Oct 2003 A1
20030198067 Sun et al. Oct 2003 A1
20040017689 Zhang et al. Jan 2004 A1
20040032754 Yang Feb 2004 A1
20040034555 Dismukes et al. Apr 2004 A1
20040148047 Dismukes et al. Jul 2004 A1
20040156220 Kim et al. Aug 2004 A1
20040174147 Vinciarelli Sep 2004 A1
20040196672 Amei Oct 2004 A1
20040200631 Chen Oct 2004 A1
20040217794 Strysko Nov 2004 A1
20040257095 Yang Dec 2004 A1
20050024179 Chandrasekaran et al. Feb 2005 A1
20050046404 Uusitalo Mar 2005 A1
20050052224 Yang et al. Mar 2005 A1
20050052886 Yang et al. Mar 2005 A1
20050207189 Chen Sep 2005 A1
20050245658 Mehrotra et al. Nov 2005 A1
20050254266 Jitaru Nov 2005 A1
20050254268 Reinhard et al. Nov 2005 A1
20050281058 Batarseh et al. Dec 2005 A1
20050286270 Petkov et al. Dec 2005 A1
20060006975 Jitaru et al. Jan 2006 A1
20060006976 Bruno Jan 2006 A1
20060007713 Brown Jan 2006 A1
20060038549 Mehrotra et al. Feb 2006 A1
20060038649 Mehrotra et al. Feb 2006 A1
20060038650 Mehrotra et al. Feb 2006 A1
20060044845 Fahlenkamp Mar 2006 A1
20060091430 Sriram et al. May 2006 A1
20060109698 Qu May 2006 A1
20060187684 Chandrasekaran et al. Aug 2006 A1
20060197510 Chandrasekaran Sep 2006 A1
20060198173 Rozman Sep 2006 A1
20060226477 Brar et al. Oct 2006 A1
20060226478 Brar et al. Oct 2006 A1
20060227576 Yasumura Oct 2006 A1
20060237968 Chandrasekaran Oct 2006 A1
20060255360 Brar et al. Nov 2006 A1
20060271315 Cargonja et al. Nov 2006 A1
20060286865 Chou et al. Dec 2006 A1
20070007945 King et al. Jan 2007 A1
20070010298 Chang Jan 2007 A1
20070019356 Morikawa Jan 2007 A1
20070030717 Luger et al. Feb 2007 A1
20070045765 Brar et al. Mar 2007 A1
20070058402 Shekhawat et al. Mar 2007 A1
20070069286 Brar et al. Mar 2007 A1
20070114979 Chandrasekaran May 2007 A1
20070120953 Koga et al. May 2007 A1
20070121351 Zhang et al. May 2007 A1
20070139984 Lo Jun 2007 A1
20070159857 Lee Jul 2007 A1
20070206523 Huynh et al. Sep 2007 A1
20070222463 Qahouq et al. Sep 2007 A1
20070241721 Weinstein et al. Oct 2007 A1
20070274106 Coulson et al. Nov 2007 A1
20070274107 Garner et al. Nov 2007 A1
20070296028 Brar et al. Dec 2007 A1
20070296383 Xu Dec 2007 A1
20070298559 Brar et al. Dec 2007 A1
20070298564 Brar et al. Dec 2007 A1
20080012423 Mimran Jan 2008 A1
20080012802 Lin Jan 2008 A1
20080024094 Nishihara et al. Jan 2008 A1
20080024259 Chandrasekaran et al. Jan 2008 A1
20080030178 Leonard et al. Feb 2008 A1
20080031021 Ros et al. Feb 2008 A1
20080037294 Indika de Silva et al. Feb 2008 A1
20080043503 Yang Feb 2008 A1
20080054874 Chandrasekaran et al. Mar 2008 A1
20080080219 Sohma Apr 2008 A1
20080111657 Mehrotra et al. May 2008 A1
20080130321 Artusi et al. Jun 2008 A1
20080130322 Artusi et al. Jun 2008 A1
20080137381 Beasley Jun 2008 A1
20080150666 Chandrasekaran et al. Jun 2008 A1
20080198638 Reinberger et al. Aug 2008 A1
20080205104 Lev et al. Aug 2008 A1
20080224812 Chandrasekaran Sep 2008 A1
20080232141 Artusi et al. Sep 2008 A1
20080298106 Tateishi Dec 2008 A1
20080310190 Chandrasekaran et al. Dec 2008 A1
20080315852 Jayaraman et al. Dec 2008 A1
20080316779 Jayaraman et al. Dec 2008 A1
20090002054 Tsunoda et al. Jan 2009 A1
20090027926 Yang et al. Jan 2009 A1
20090046486 Lu et al. Feb 2009 A1
20090072626 Watanabe et al. Mar 2009 A1
20090097290 Chandrasekaran Apr 2009 A1
20090109711 Hsu Apr 2009 A1
20090257250 Liu Oct 2009 A1
20090273957 Feldtkeller Nov 2009 A1
20090284994 Lin et al. Nov 2009 A1
20090289557 Itoh et al. Nov 2009 A1
20090290385 Jungreis et al. Nov 2009 A1
20090302986 Bedea Dec 2009 A1
20090310388 Yang Dec 2009 A1
20090315530 Baranwal Dec 2009 A1
20100020578 Ryu et al. Jan 2010 A1
20100054000 Huynh Mar 2010 A1
20100066336 Araki et al. Mar 2010 A1
20100091522 Chandrasekaran et al. Apr 2010 A1
20100123486 Berghegger May 2010 A1
20100149838 Artusi et al. Jun 2010 A1
20100164400 Adragna Jul 2010 A1
20100182806 Garrity et al. Jul 2010 A1
20100188876 Garrity et al. Jul 2010 A1
20100219802 Lin et al. Sep 2010 A1
20100254168 Chandrasekaran Oct 2010 A1
20100321958 Brinlee et al. Dec 2010 A1
20100321964 Brinlee et al. Dec 2010 A1
20110025289 Wang et al. Feb 2011 A1
20110038179 Zhang Feb 2011 A1
20110062926 Qiu et al. Mar 2011 A1
20110080102 Ge et al. Apr 2011 A1
20110089917 Chen et al. Apr 2011 A1
20110095730 Strijker et al. Apr 2011 A1
20110134664 Berghegger Jun 2011 A1
20110149607 Jungreis et al. Jun 2011 A1
20110182089 Berghegger Jul 2011 A1
20110239008 Lam et al. Sep 2011 A1
20110241738 Tamaoka Oct 2011 A1
20110267856 Pansier Nov 2011 A1
20110291591 Shiu et al. Dec 2011 A1
20110305047 Jungreis et al. Dec 2011 A1
20120020119 Tang et al. Jan 2012 A1
20120243271 Berghegger Sep 2012 A1
20120250378 Kok et al. Oct 2012 A1
20120294048 Brinlee Nov 2012 A1
20130003430 Reddy Jan 2013 A1
20130134894 Kuang May 2013 A1
20130229829 Zhang et al. Sep 2013 A1
20130250627 Herfurth Sep 2013 A1
20140091718 Brinlee Apr 2014 A1
20140091720 Brinlee Apr 2014 A1
20140254215 Brinlee et al. Sep 2014 A1
20140301111 Jungreis et al. Oct 2014 A1
20150098254 Brinlee et al. Apr 2015 A1
20150138857 Ye et al. May 2015 A1
Foreign Referenced Citations (25)
Number Date Country
2904469 May 2007 CN
101106850 Jan 2008 CN
101123395 Feb 2008 CN
101141099 Mar 2008 CN
101202509 Jun 2008 CN
201252294 Jun 2009 CN
101834541 Sep 2010 CN
102412727 Apr 2012 CN
102695325 Sep 2012 CN
101489335 Dec 2012 CN
10112820 Oct 2002 DE
10310361 Sep 2004 DE
10352509 Jun 2005 DE
102013104899 Nov 2014 DE
0 665 634 Jan 1994 EP
57097361 Jun 1982 JP
3-215911 Sep 1991 JP
2000-68132 Mar 2000 JP
2008283818 Nov 2008 JP
WO8700991 Feb 1987 WO
03088463 Oct 2003 WO
WO2010-083511 Jul 2010 WO
WO2010-083514 Jul 2010 WO
WO2010-114914 Oct 2010 WO
WO2011-116225 Sep 2011 WO
Non-Patent Literature Citations (61)
Entry
Chhawchharia, P., et al., “On the Reduction of Component Count in Switched Capacitor DC/DC Convertors,” Hong Kong Polytechnic University, IEEE, 1997, Hung Hom, Kowloon, Hong King, pp. 1395-1401.
Freescale Semiconductor, “Implementing a Digital AC/DC Switched-Mode Power Supply using a 56F8300 Digital Signal Controller,” Application Note AN3115, Aug. 2005, 24 pp., Chandler, AZ.
Kuwabara, K., et al., “Switched-Capacitor DC-DC Converters,” Fujitsu Limited, IEEE, 1988, Kawasaki, Japan, pp. 213-218.
Maxim, Application Note 725, www.maxim-ic.com/an725, Maxim Integrated Products, Nov. 29, 2001, 8 pages.
National Semiconductor Corporation, “LM2665 Switched Capacitor Voltage Converter,” www.national.com, Sep. 2005, 9 pages.
National Semiconductor Corporation, “LMC7660 Switched Capacitor Voltage Converter,” www.national.com, Apr. 1997, 12 pages.
Texas Instruments Incorporated, “LT1054, LT1054Y Switched-Capacitor Voltage Converters With Regulators,” SLVS033C, Feb. 1990—Revised Jul. 1998, 25 pages.
Vallamkonda, S., “Limitations of Switching Voltage Regulators,” A Thesis in Electrical Engineering, Texas Tech University, May 2004, 89 pages.
Xu, M., et al., “Voltage Divider and its Application in the Two-stage Power Architecture,” Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, IEEE, 2006, Blacksburg, Virginia, pp. 499-505.
Freescale Semiconductor, “56F8323 Evaluation Module User Manual, 56F8300 16-bit Digital Signal Controllers”,MC56F8323EVMUM, Rev. 2, Jul. 2005 (72 pages).
Freescale Semiconductor, “56F8323-56F8123 Data Sheet Preliminary Technical Data, 56F8300 16-bit Digital Signal Controllers,” MC56F8323 Rev. 17, Apr. 2007 (140 pages).
Freescale Semiconductor, “Design of a Digital AC-DC SMPS using the 56F8323 Device, Designer Reference Manual, 56800E 16-bit Digital Signal Controllers”, DRM074, Rev. 0, Aug. 2005 (108 pages).
Power Integrations, Inc., “TOP200-4-14 TOPSwitch® Family Three-terminal Off-line PWM Switch,” Internet Citation http:--www.datasheet4u.com-.download.php?id=311769, Jul. 1996, XP002524650, pp. 1-16.
ANIOO: Application NoteusingLxIOO Family of High Performance N-Ch JFET Transistors, ANIOO.Rev 1.01, Sep. 2003, 5 pp., Lovoltech, Inc., Santa Clara, CA.
Bill Andreycak, Active Clamp and Reset Technique Enhances Forward Converter Performance, Oct. 1994, Texas Instruments, 19 pages.
ANIOIA: Gate Drive Network for a Power JFET, ANIOIA.Rev 1.2, Nov. 2003, 2 pp., Lovoltech, Inc., Santa Clara, CA.
AN108: Applications Note: How to Use Power JFETs® and MOSFETs Interchangeably in Low-Side Applications, Rev. 1.0.1, Feb. 14, 2005, 4 pp. Lovoltech, Inc., Santa Clara, CA.
Biernacki, J., et al., “Radio Frequency DC-DC Flyback Converter,” Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Aug. 8-11, 2000, pp. 94-97, vol. 1, IEEE, Los Alamitos, CA.
Ajram, S., et al., “Ultrahigh Frequency DC-to-DC Converters Using GaAs Power Switches,” IEEE Transactions on Power Electronics, Sep. 2001, pp. 594-602, vol. 16, No. 5, IEEE, Los Alamitos, CA.
Chen, W., et al., “Design of High Efficiency, Low Profile, Low Voltage Converter with Integrated Magnetics,” Proceedings of 1997 IEEE Applied Power Electronics Conference (APEC '97), 1997, pp. 911-917, IEEE, Los Alamitos, CA.
Bergman, J., “Development ofIndium Arsenide Quantum Well Electronic Circuits: A Dissertation Presented to the Academic Faculty,” http://smartech.gatech.edu/bitstream/ 1853/ 5033/ 11 bergman—joshua—i—200407—phd.pdf, Jul. 2004, 225 pp., Georgia Institute of Technology, Atlanta, GA.
Chen, W., et al., “Integrated Planar Inductor Scheme for Multi-module Interleaved Quasi-Square-Wave (QSW) DC/DC Converter,” 30th Annual IEEE Power Electronics Specialists Conference (PESC '99), 1999, pp. 759-762, vol. 2, IEEE, Los Alamitos, CA.
Curtis, K., “Advances in Microcontroller Peripherals Facilitate Current-Mode for Digital Power Supplies,” Digital Power Forum '06, 4 pp., Sep. 2006, Darnell Group, Richardson, TX.
Eisenbeiser, K., et al., “Manufacturable GaAs VFET for Power Switching Applications,” IEEE Electron Device Letters, Apr. 2000, pp. 144-145, vol. 21, No. 4, IEEE.
Gaye, M., et al., “A50-IOO MHz 5V to−5V, IW Cuk Converter Using Gallium Arsenide Power Switches,” ISCAS 2000—IEEE International Symposium on Circuits and Systems, May 28-31, 2000, pp. I-264-I-267, vol. 1, IEEE, Geneva, Switzerland.
Goldberg, A.F., et al., “Issues Related to 1-10-MHz Transformer Design,” IEEE Transactions on Power Electronics, Jan. 1989, pp. 113-123, vol. 4, No. 1, IEEE, Los Alamitos, CA.
Jitaru, I.D., et al., “Quasi-Integrated Magnetic an Avenue for Higher Power Density and Efficiency in Power Converters,” Twelfth Annual Applied Power Electronics Conference and Exposition, Feb. 23-27, 1997, pp. 395-402, vol. 1, IEEE, Los Alamitos, CA.
Kollman, R., et al., “10 MHz PWM Converters with GaAs VFETs,” IEEE Eleventh Annual Applied Power Electronics Conference and Exposition, Mar. 1996, pp. 264-269, vol. 1, IEEE.
Lee, P.-W., et al., “Steady-State Analysis of an Interleaved Boost Converter with Coupled Inductors,” IEEE Transactions on Industrial Electronics, Aug. 2000, pp. 787-795, vol. 47, No. 4, IEEE, Los Alamitos, CA.
Lenk, R., “Introduction to the Tapped Buck Converter,” PCIM 2000, HFPC 2000 Proceedings, Oct. 2000, pp. 155-166.
Liu, W., “Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs,” §5-5: Modulation Doping, 1999, pp. 323-330, John Wiley & Sons, New York, NY.
Maksimović, D., et al., “Switching Converters with Wide DC Conversion Range,” IEEE Transactions on Power Electronics, Jan. 1991, pp. 151-157, vol. 6, No. 1, IEEE, Los Alamitos, CA.
Miwa, B.A., et al., “High Efficiency Power Factor Correction Using Interleaving Techniques,” IEEE Proceedings of APEC, 1992, pp. 557-568, IEEE, Los Alamitos, CA.
Middlebrook, R.D., “Transformerless DC-to-DC Converters with Large Conversion Ratios,” IEEE Transactions on Power Electronics, Oct. 1988, pp. 484-488, vol. 3, No. 4, IEEE, Los Alamitos, CA.
Nguyen, L.D., et al., “Ultra-High-Speed Modulation-Doped Field Effect Transistors: A Tutorial Review,” Proceedings of the IEEE, Apr. 1992, pp. 494-518, vol. 80, No. 4, IEEE.
Niemela, V.A., et al., “Comparison ofGaAs and Silicon Synchronous Rectifiers in a3.3V Out, SOW DC-DC Converter,” 27th Annual, IEEE Power Electronics Specialists Conference, Jun. 1996, pp. 861-867, vol. 1, IEEE.
Ninomiya, T., et al., “Static and Dynamic Analysis of Zero-Voltage Switched Half-Bridge Converter with PWM Control,” Proceedings of 1991 IEEE Power Electronics Specialists Conference (PESC '91 ), 1991, pp. 230-237, IEEE, Los Alamitos, CA.
O'Meara, K., “A New Output Rectifier Configuration Optimized for High Frequency Operation,” Proceedings of 1991 High Frequency Power Conversion (HFPC '91) Conference, Jun. 1991, pp. 219-225, Toronto, CA.
Pietkiewicz, A., et al. “Coupled-Inductor Current-Doubler Topology in Phase-Shifted Full-Bridge DC-DC Converter,” Proceedings of INTELEC '98, 1998, 9 pp., Paper 2-3, IEEE, Los Alamitos, CA.
Plumton, D.L., et al., “A Low On-Resistance High-Current GaAs Power VFET,” IEEE Electron Device Letters, Apr. 1995, pp. 142- 144, vol. 16, No. 4, IEEE.
Rajeev, M., “An Input Current Shaper with Boost and Flyback Converter Using Integrated Magnetics,” Power Electronics and Drive Systems, Fifth International Conference on Power Electronics and Drive Systems 2003, Nov. 17-20, 2003, pp. 327-331, vol. 1, IEEE, Los Alamitos, CA.
Rico, M., et al., “Static and Dynamic Modeling of Tapped-Inductor DC-to-DC Converters,” 1987, pp. 281-288, IEEE, Los Alamitos, CA.
Severns, R., “Circuit Reinvention in Power Electronics and Identification of Prior Work,” Proceedings of 1997 IEEE Applied Power Electronics Conference (APEC '97), 1997, pp. 3-9, IEEE, Los Alamitos, CA.
Severns, R., “Circuit Reinvention in Power Electronics and Identification of Prior Work,” IEEE Transactions on Power Electronics, Jan. 2001, pp. 1-7, vol. 16, No. 1, IEEE, Los Alamitos, CA.
Sun, J., et al., “Unified Analysis of Half-Bridge Converters with Current-Doubler Rectifier,” Proceedings of 2001 IEEE Applied Power Electronics Conference, 2001, pp. 514-520, IEEE, Los Alamitos, CA.
Sun, J., et al., “An Improved current-Doubler Rectifier with Integrated Magnetics,” 17th Annual Applied Power Electronics Conference and Exposition (APEC), 2002, 831-837, vol. 2, IEEEE, Dallas, TX.
Thaker, M. et al., “Adaptive/Intelligent Control and Power Management Reduce Power Dissipation and Consumption,” Digital Power Forum '06, 11 pp., Sep. 2006, Darnell Group, Richardson, TX.
Wei, J., et al., “Comparison of Three Topology Candidates for 12V VRM,” IEEE APEC, 2001, pp. 245-251, IEEE, Los Alamitos, CA.
Weitzel, C.E., “RF Power Devices for Wireless Communications,” 2002, 2002 IEEE MTT-S CDROM, paper TU4B-I, IEEE, 4 pages.
Williams, R., “Modern GaAs Processing Methods,” 1990, pp. 66-67, Artech House, Inc., Norwood, MA.
Wong, P.-L., et al., “Investigating Coupling Inductors in the Interleaving QSW VRM,” 15th Annual Applied Power Electronics Conference and Exposition (APEC 2000), Feb. 2000, pp. 973-978, vol. 2, IEEE, Los Alamitos, CA.
Xu, P., et al., “A Novel Integrated Current Doubler Rectifier,” IEEE 2000 Applied Power Electronics Conference, Mar. 2000, pp. 735-740, IEEE, Los Alamitos, CA.
Xu, et al., Design of 48V Voltage Regulator Modules with a Novel Integrated Magnetics, IEEE Transactions on Power Electronics, vol. 17, No. 6 (Nov. 2002), pp. 990-998.
Xu, P., et al., “Design and Performance Evaluation of Multi-Channel Interleaved Quasi-Square-Wave Buck Voltage Regulator Module,” HFPC 2000 Proceedings, Oct. 2000, pp. 82-88.
Xu, P., et al., “A Family of Novel Interleaved DC/DC Converters for Low-Voltage High-Current VoltageRegulator Module Applications,” IEEE Power Electronics Specialists Conference, Jun. 2001, pp. 1507-1511, IEEE, Los Alamitos, CA.
Yan, L., et al., “Integrated Magnetic Full Wave Converter with Flexible Output Inductor,” IEEE Transactions on Power Electronics, Mar. 2003, pp. 670-678, vol. 18, No. 2, IEEE, Los Alamitos, CA.
Yan, L., et al., “Integrated Magnetic Full Wave Converter with Flexible Output Inductor,” 17th Annual Applied Power Electronics Conference and Exposition (APEC), 2002, pp. 824-830, vol. 2, IEEE, Dallas, TX.
Zhou, X., et al., “A High Power Density, High Efficiency and Fast Transient Voltage Regulator Module with a Novel Current Sensing and Current Sharing Technique,” IEEE Applied Power Electronics Conference, Mar. 1999, pp. 289-294, IEEE, Los Alamitos, CA.
Zhou, X., et al., “Investigation of Candidate VRM Topologies for Future Microprocessors,” IEEE Applied Power Electronics Conference, Mar. 1998, pp. 145-150; IEEE, Los Alamitos, CA.
Goldberg, A.F., et al., “Finite-Element Analysis of Copper Loss in 1-10-MHz Transformers,” IEEE Transactions on Power Electronics, Apr. 1989, pp. 157-167, vol. 4, No. 2, IEEE, Los Alamitos, CA.
Ridley, R., Designing with the TL431, Switching Power Magazine, Designer Series XV, pp. 1-5, 2005.
Related Publications (1)
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20110205763 A1 Aug 2011 US
Continuations (1)
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Parent 11607325 Dec 2006 US
Child 12712894 US